usb: dwc3: omap: Adds dwc3_omap_readl/writel wrappers
This patch adds wrappers to dwc3_omap_readl/writel calls to accomodate both OMAP5 and AM437x reg maps (It uses the cached register offsets). Also renames OMAP5 IRQ1 as IRQMISC and IRQ1 bits as IRQMISC bits. Signed-off-by: George Cherian <george.cherian@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
George Cherian
Felipe Balbi
Родитель
ff7307b534
Коммит
b1fd6cb5ee
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@ -67,10 +67,18 @@
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#define USBOTGSS_IRQENABLE_SET_0 0x002c
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#define USBOTGSS_IRQENABLE_CLR_0 0x0030
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#define USBOTGSS_IRQ0_OFFSET 0x0004
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#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
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#define USBOTGSS_IRQSTATUS_1 0x0038
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#define USBOTGSS_IRQENABLE_SET_1 0x003c
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#define USBOTGSS_IRQENABLE_CLR_1 0x0040
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#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
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#define USBOTGSS_IRQSTATUS_1 0x0034
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#define USBOTGSS_IRQENABLE_SET_1 0x0038
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#define USBOTGSS_IRQENABLE_CLR_1 0x003c
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#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
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#define USBOTGSS_IRQSTATUS_2 0x0044
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#define USBOTGSS_IRQENABLE_SET_2 0x0048
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#define USBOTGSS_IRQENABLE_CLR_2 0x004c
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#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
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#define USBOTGSS_IRQSTATUS_3 0x0054
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#define USBOTGSS_IRQENABLE_SET_3 0x0058
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#define USBOTGSS_IRQENABLE_CLR_3 0x005c
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#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
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#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
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#define USBOTGSS_IRQSTATUS_MISC 0x0038
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@ -102,17 +110,17 @@
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/* IRQS0 BITS */
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#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
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/* IRQ1 BITS */
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#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
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#define USBOTGSS_IRQ1_OEVT (1 << 16)
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#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
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#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
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#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
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#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
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#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
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#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
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#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
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#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
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/* IRQMISC BITS */
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#define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
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#define USBOTGSS_IRQMISC_OEVT (1 << 16)
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#define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
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#define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
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#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
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#define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
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#define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
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#define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
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#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
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#define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
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/* UTMI_OTG_CTRL REGISTER */
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#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
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@ -161,6 +169,58 @@ static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
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writel(value, base + offset);
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}
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static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
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omap->utmi_otg_offset);
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}
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static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
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omap->utmi_otg_offset, value);
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}
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static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
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omap->irq0_offset);
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}
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static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
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omap->irq0_offset, value);
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}
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static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
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omap->irqmisc_offset);
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}
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static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
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omap->irqmisc_offset, value);
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}
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static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
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omap->irqmisc_offset, value);
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}
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static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
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omap->irq0_offset, value);
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}
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int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
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{
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u32 val;
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@ -173,38 +233,38 @@ int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
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case OMAP_DWC3_ID_GROUND:
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dev_dbg(omap->dev, "ID GND\n");
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val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
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val = dwc3_omap_read_utmi_status(omap);
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val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
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| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
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| USBOTGSS_UTMI_OTG_STATUS_SESSEND);
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val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
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| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
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dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
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dwc3_omap_write_utmi_status(omap, val);
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break;
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case OMAP_DWC3_VBUS_VALID:
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dev_dbg(omap->dev, "VBUS Connect\n");
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val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
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val = dwc3_omap_read_utmi_status(omap);
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val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
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val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
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| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
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| USBOTGSS_UTMI_OTG_STATUS_SESSVALID
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| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
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dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
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dwc3_omap_write_utmi_status(omap, val);
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break;
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case OMAP_DWC3_ID_FLOAT:
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case OMAP_DWC3_VBUS_OFF:
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dev_dbg(omap->dev, "VBUS Disconnect\n");
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val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
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val = dwc3_omap_read_utmi_status(omap);
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val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
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| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
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| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
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val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
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| USBOTGSS_UTMI_OTG_STATUS_IDDIG;
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dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
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dwc3_omap_write_utmi_status(omap, val);
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break;
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default:
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@ -222,44 +282,45 @@ static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
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spin_lock(&omap->lock);
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reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
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reg = dwc3_omap_read_irqmisc_status(omap);
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if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
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if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
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dev_dbg(omap->dev, "DMA Disable was Cleared\n");
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omap->dma_status = false;
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}
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if (reg & USBOTGSS_IRQ1_OEVT)
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if (reg & USBOTGSS_IRQMISC_OEVT)
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dev_dbg(omap->dev, "OTG Event\n");
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if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
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if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
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dev_dbg(omap->dev, "DRVVBUS Rise\n");
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if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
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if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
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dev_dbg(omap->dev, "CHRGVBUS Rise\n");
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if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
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if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
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dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
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if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
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if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
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dev_dbg(omap->dev, "IDPULLUP Rise\n");
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if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
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if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
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dev_dbg(omap->dev, "DRVVBUS Fall\n");
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if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
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if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
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dev_dbg(omap->dev, "CHRGVBUS Fall\n");
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if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
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if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
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dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
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if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
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if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
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dev_dbg(omap->dev, "IDPULLUP Fall\n");
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dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
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dwc3_omap_write_irqmisc_status(omap, reg);
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reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
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dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
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reg = dwc3_omap_read_irq0_status(omap);
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dwc3_omap_write_irq0_status(omap, reg);
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spin_unlock(&omap->lock);
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@ -281,26 +342,26 @@ static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
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/* enable all IRQs */
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reg = USBOTGSS_IRQO_COREIRQ_ST;
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
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dwc3_omap_write_irq0_set(omap, reg);
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reg = (USBOTGSS_IRQ1_OEVT |
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USBOTGSS_IRQ1_DRVVBUS_RISE |
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USBOTGSS_IRQ1_CHRGVBUS_RISE |
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USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
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USBOTGSS_IRQ1_IDPULLUP_RISE |
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USBOTGSS_IRQ1_DRVVBUS_FALL |
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USBOTGSS_IRQ1_CHRGVBUS_FALL |
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USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
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USBOTGSS_IRQ1_IDPULLUP_FALL);
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reg = (USBOTGSS_IRQMISC_OEVT |
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USBOTGSS_IRQMISC_DRVVBUS_RISE |
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USBOTGSS_IRQMISC_CHRGVBUS_RISE |
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USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
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USBOTGSS_IRQMISC_IDPULLUP_RISE |
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USBOTGSS_IRQMISC_DRVVBUS_FALL |
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USBOTGSS_IRQMISC_CHRGVBUS_FALL |
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USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
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USBOTGSS_IRQMISC_IDPULLUP_FALL);
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
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dwc3_omap_write_irqmisc_set(omap, reg);
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}
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static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
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{
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/* disable all IRQs */
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, 0x00);
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x00);
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dwc3_omap_write_irqmisc_set(omap, 0x00);
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dwc3_omap_write_irq0_set(omap, 0x00);
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}
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static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
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@ -378,7 +439,7 @@ static int dwc3_omap_probe(struct platform_device *pdev)
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omap->revision = reg;
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x_major = USBOTGSS_REVISION_XMAJOR(reg);
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/* Differentiate between OMAP5,AM437x and others*/
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/* Differentiate between OMAP5 and AM437x */
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switch (x_major) {
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case USBOTGSS_REVISION_XMAJOR1:
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case USBOTGSS_REVISION_XMAJOR2:
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@ -410,7 +471,7 @@ static int dwc3_omap_probe(struct platform_device *pdev)
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omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
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}
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reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
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reg = dwc3_omap_read_utmi_status(omap);
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of_property_read_u32(node, "utmi-mode", &utmi_mode);
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@ -425,7 +486,7 @@ static int dwc3_omap_probe(struct platform_device *pdev)
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dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
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}
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dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
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dwc3_omap_write_utmi_status(omap, reg);
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/* check the DMA Status */
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reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
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@ -505,8 +566,7 @@ static int dwc3_omap_suspend(struct device *dev)
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{
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struct dwc3_omap *omap = dev_get_drvdata(dev);
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omap->utmi_otg_status = dwc3_omap_readl(omap->base,
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USBOTGSS_UTMI_OTG_STATUS);
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omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);
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return 0;
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}
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@ -515,8 +575,7 @@ static int dwc3_omap_resume(struct device *dev)
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{
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struct dwc3_omap *omap = dev_get_drvdata(dev);
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dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS,
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omap->utmi_otg_status);
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dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);
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pm_runtime_disable(dev);
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pm_runtime_set_active(dev);
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