Merge branch 'kvm-arm/timer' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into next/virt
From Marc Zyngier, this branch enables virtual GIC and timer for KVM/ARM. * 'kvm-arm/timer' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms: ARM: KVM: arch_timers: Wire the init code and config option ARM: KVM: arch_timers: Add timer world switch ARM: KVM: arch_timers: Add guest timer core support ARM: KVM: Add VGIC configuration option ARM: KVM: VGIC initialisation code ARM: KVM: VGIC control interface world switch ARM: KVM: VGIC interrupt injection ARM: KVM: vgic: retire queued, disabled interrupts ARM: KVM: VGIC virtual CPU interface management ARM: KVM: VGIC distributor handling ARM: KVM: VGIC accept vcpu and dist base addresses from user space ARM: KVM: Initial VGIC infrastructure code ARM: KVM: Keep track of currently running vcpus KVM: ARM: Introduce KVM_ARM_SET_DEVICE_ADDR ioctl ARM: gic: add __ASSEMBLY__ guard to C definitions ARM: gic: define GICH offsets for VGIC support ARM: gic: add missing distributor defintions
This commit is contained in:
Olof Johansson
Коммит
b221498e5d
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@ -2210,6 +2210,44 @@ This ioctl returns the guest registers that are supported for the
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KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.
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4.80 KVM_ARM_SET_DEVICE_ADDR
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Capability: KVM_CAP_ARM_SET_DEVICE_ADDR
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Architectures: arm
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Type: vm ioctl
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Parameters: struct kvm_arm_device_address (in)
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Returns: 0 on success, -1 on error
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Errors:
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ENODEV: The device id is unknown
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ENXIO: Device not supported on current system
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EEXIST: Address already set
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E2BIG: Address outside guest physical address space
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EBUSY: Address overlaps with other device range
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struct kvm_arm_device_addr {
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__u64 id;
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__u64 addr;
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};
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Specify a device address in the guest's physical address space where guests
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can access emulated or directly exposed devices, which the host kernel needs
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to know about. The id field is an architecture specific identifier for a
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specific device.
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ARM divides the id field into two parts, a device id and an address type id
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specific to the individual device.
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bits: | 63 ... 32 | 31 ... 16 | 15 ... 0 |
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field: | 0x00000000 | device id | addr type id |
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ARM currently only require this when using the in-kernel GIC support for the
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hardware VGIC features, using KVM_ARM_DEVICE_VGIC_V2 as the device id. When
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setting the base address for the guest's mapping of the VGIC virtual CPU
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and distributor interface, the ioctl must be called after calling
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KVM_CREATE_IRQCHIP, but before calling KVM_RUN on any of the VCPUs. Calling
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this ioctl twice for any of the base addresses will return -EEXIST.
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5. The kvm_run structure
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------------------------
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@ -0,0 +1,85 @@
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/*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_KVM_ARCH_TIMER_H
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#define __ASM_ARM_KVM_ARCH_TIMER_H
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#include <linux/clocksource.h>
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#include <linux/hrtimer.h>
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#include <linux/workqueue.h>
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struct arch_timer_kvm {
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#ifdef CONFIG_KVM_ARM_TIMER
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/* Is the timer enabled */
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bool enabled;
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/* Virtual offset */
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cycle_t cntvoff;
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#endif
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};
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struct arch_timer_cpu {
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#ifdef CONFIG_KVM_ARM_TIMER
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/* Registers: control register, timer value */
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u32 cntv_ctl; /* Saved/restored */
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cycle_t cntv_cval; /* Saved/restored */
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/*
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* Anything that is not used directly from assembly code goes
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* here.
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*/
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/* Background timer used when the guest is not running */
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struct hrtimer timer;
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/* Work queued with the above timer expires */
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struct work_struct expired;
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/* Background timer active */
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bool armed;
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/* Timer IRQ */
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const struct kvm_irq_level *irq;
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#endif
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};
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#ifdef CONFIG_KVM_ARM_TIMER
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int kvm_timer_hyp_init(void);
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int kvm_timer_init(struct kvm *kvm);
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void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
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void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
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void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
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void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
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#else
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static inline int kvm_timer_hyp_init(void)
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{
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return 0;
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};
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static inline int kvm_timer_init(struct kvm *kvm)
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{
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return 0;
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}
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static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
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static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
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static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
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static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
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#endif
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#endif
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@ -45,7 +45,8 @@
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#define c13_TID_URW 23 /* Thread ID, User R/W */
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#define c13_TID_URO 24 /* Thread ID, User R/O */
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#define c13_TID_PRIV 25 /* Thread ID, Privileged */
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#define NR_CP15_REGS 26 /* Number of regs (incl. invalid) */
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#define c14_CNTKCTL 26 /* Timer Control Register (PL1) */
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#define NR_CP15_REGS 27 /* Number of regs (incl. invalid) */
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#define ARM_EXCEPTION_RESET 0
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#define ARM_EXCEPTION_UNDEFINED 1
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@ -23,6 +23,7 @@
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmio.h>
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#include <asm/fpstate.h>
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#include <asm/kvm_arch_timer.h>
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#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
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#define KVM_MEMORY_SLOTS 32
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@ -37,6 +38,8 @@
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#define KVM_NR_PAGE_SIZES 1
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#define KVM_PAGES_PER_HPAGE(x) (1UL<<31)
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#include <asm/kvm_vgic.h>
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struct kvm_vcpu;
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u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
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int kvm_target_cpu(void);
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@ -47,6 +50,9 @@ struct kvm_arch {
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/* VTTBR value associated with below pgd and vmid */
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u64 vttbr;
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/* Timer */
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struct arch_timer_kvm timer;
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/*
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* Anything that is not used directly from assembly code goes
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* here.
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@ -58,6 +64,9 @@ struct kvm_arch {
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/* Stage-2 page table */
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pgd_t *pgd;
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/* Interrupt controller */
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struct vgic_dist vgic;
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};
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#define KVM_NR_MEM_OBJS 40
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@ -92,6 +101,10 @@ struct kvm_vcpu_arch {
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struct vfp_hard_struct vfp_guest;
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struct vfp_hard_struct *vfp_host;
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/* VGIC state */
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struct vgic_cpu vgic_cpu;
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struct arch_timer_cpu timer_cpu;
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/*
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* Anything that is not used directly from assembly code goes
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* here.
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@ -158,4 +171,14 @@ static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
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{
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return 0;
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}
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struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
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struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
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int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
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unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
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struct kvm_one_reg;
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int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
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int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
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#endif /* __ARM_KVM_HOST_H__ */
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@ -0,0 +1,221 @@
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/*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_KVM_VGIC_H
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#define __ASM_ARM_KVM_VGIC_H
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#include <linux/kernel.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/irqreturn.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/irqchip/arm-gic.h>
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#define VGIC_NR_IRQS 128
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#define VGIC_NR_SGIS 16
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#define VGIC_NR_PPIS 16
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#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
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#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
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#define VGIC_MAX_CPUS KVM_MAX_VCPUS
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#define VGIC_MAX_LRS (1 << 6)
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/* Sanity checks... */
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#if (VGIC_MAX_CPUS > 8)
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#error Invalid number of CPU interfaces
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#endif
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#if (VGIC_NR_IRQS & 31)
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#error "VGIC_NR_IRQS must be a multiple of 32"
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#endif
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#if (VGIC_NR_IRQS > 1024)
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#error "VGIC_NR_IRQS must be <= 1024"
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#endif
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/*
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* The GIC distributor registers describing interrupts have two parts:
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* - 32 per-CPU interrupts (SGI + PPI)
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* - a bunch of shared interrupts (SPI)
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*/
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struct vgic_bitmap {
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union {
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u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
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DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
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} percpu[VGIC_MAX_CPUS];
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union {
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u32 reg[VGIC_NR_SHARED_IRQS / 32];
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DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
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} shared;
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};
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struct vgic_bytemap {
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u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
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u32 shared[VGIC_NR_SHARED_IRQS / 4];
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};
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struct vgic_dist {
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#ifdef CONFIG_KVM_ARM_VGIC
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spinlock_t lock;
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bool ready;
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/* Virtual control interface mapping */
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void __iomem *vctrl_base;
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/* Distributor and vcpu interface mapping in the guest */
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phys_addr_t vgic_dist_base;
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phys_addr_t vgic_cpu_base;
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/* Distributor enabled */
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u32 enabled;
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/* Interrupt enabled (one bit per IRQ) */
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struct vgic_bitmap irq_enabled;
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/* Interrupt 'pin' level */
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struct vgic_bitmap irq_state;
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/* Level-triggered interrupt in progress */
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struct vgic_bitmap irq_active;
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/* Interrupt priority. Not used yet. */
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struct vgic_bytemap irq_priority;
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/* Level/edge triggered */
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struct vgic_bitmap irq_cfg;
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|
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/* Source CPU per SGI and target CPU */
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u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
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|
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/* Target CPU for each IRQ */
|
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u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
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struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
|
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|
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/* Bitmap indicating which CPU has something pending */
|
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unsigned long irq_pending_on_cpu;
|
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#endif
|
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};
|
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|
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struct vgic_cpu {
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#ifdef CONFIG_KVM_ARM_VGIC
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/* per IRQ to LR mapping */
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u8 vgic_irq_lr_map[VGIC_NR_IRQS];
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|
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/* Pending interrupts on this VCPU */
|
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DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
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DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
|
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|
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/* Bitmap of used/free list registers */
|
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DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
|
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|
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/* Number of list registers on this CPU */
|
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int nr_lr;
|
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|
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/* CPU vif control registers for world switch */
|
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u32 vgic_hcr;
|
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u32 vgic_vmcr;
|
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u32 vgic_misr; /* Saved only */
|
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u32 vgic_eisr[2]; /* Saved only */
|
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u32 vgic_elrsr[2]; /* Saved only */
|
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u32 vgic_apr;
|
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u32 vgic_lr[VGIC_MAX_LRS];
|
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#endif
|
||||
};
|
||||
|
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#define LR_EMPTY 0xff
|
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|
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struct kvm;
|
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struct kvm_vcpu;
|
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struct kvm_run;
|
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struct kvm_exit_mmio;
|
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|
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#ifdef CONFIG_KVM_ARM_VGIC
|
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int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
|
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int kvm_vgic_hyp_init(void);
|
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int kvm_vgic_init(struct kvm *kvm);
|
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int kvm_vgic_create(struct kvm *kvm);
|
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int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
|
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void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
|
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void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
|
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int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
|
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bool level);
|
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int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
|
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bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
|
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struct kvm_exit_mmio *mmio);
|
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|
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#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
|
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#define vgic_initialized(k) ((k)->arch.vgic.ready)
|
||||
|
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#else
|
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static inline int kvm_vgic_hyp_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int kvm_vgic_init(struct kvm *kvm)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int kvm_vgic_create(struct kvm *kvm)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
|
||||
static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
|
||||
|
||||
static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
|
||||
unsigned int irq_num, bool level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
|
||||
struct kvm_exit_mmio *mmio)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int irqchip_in_kernel(struct kvm *kvm)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool vgic_initialized(struct kvm *kvm)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -65,6 +65,22 @@ struct kvm_regs {
|
|||
#define KVM_ARM_TARGET_CORTEX_A15 0
|
||||
#define KVM_ARM_NUM_TARGETS 1
|
||||
|
||||
/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
|
||||
#define KVM_ARM_DEVICE_TYPE_SHIFT 0
|
||||
#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
|
||||
#define KVM_ARM_DEVICE_ID_SHIFT 16
|
||||
#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
|
||||
|
||||
/* Supported device IDs */
|
||||
#define KVM_ARM_DEVICE_VGIC_V2 0
|
||||
|
||||
/* Supported VGIC address types */
|
||||
#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
|
||||
#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
|
||||
|
||||
#define KVM_VGIC_V2_DIST_SIZE 0x1000
|
||||
#define KVM_VGIC_V2_CPU_SIZE 0x2000
|
||||
|
||||
#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
|
||||
|
||||
struct kvm_vcpu_init {
|
||||
|
|
|
|||
|
|
@ -169,6 +169,24 @@ int main(void)
|
|||
DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.hxfar));
|
||||
DEFINE(VCPU_HPFAR, offsetof(struct kvm_vcpu, arch.hpfar));
|
||||
DEFINE(VCPU_HYP_PC, offsetof(struct kvm_vcpu, arch.hyp_pc));
|
||||
#ifdef CONFIG_KVM_ARM_VGIC
|
||||
DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu));
|
||||
DEFINE(VGIC_CPU_HCR, offsetof(struct vgic_cpu, vgic_hcr));
|
||||
DEFINE(VGIC_CPU_VMCR, offsetof(struct vgic_cpu, vgic_vmcr));
|
||||
DEFINE(VGIC_CPU_MISR, offsetof(struct vgic_cpu, vgic_misr));
|
||||
DEFINE(VGIC_CPU_EISR, offsetof(struct vgic_cpu, vgic_eisr));
|
||||
DEFINE(VGIC_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_elrsr));
|
||||
DEFINE(VGIC_CPU_APR, offsetof(struct vgic_cpu, vgic_apr));
|
||||
DEFINE(VGIC_CPU_LR, offsetof(struct vgic_cpu, vgic_lr));
|
||||
DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr));
|
||||
#ifdef CONFIG_KVM_ARM_TIMER
|
||||
DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
|
||||
DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
|
||||
DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff));
|
||||
DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled));
|
||||
#endif
|
||||
DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base));
|
||||
#endif
|
||||
DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr));
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -51,6 +51,22 @@ config KVM_ARM_MAX_VCPUS
|
|||
large, so only choose a reasonable number that you expect to
|
||||
actually use.
|
||||
|
||||
config KVM_ARM_VGIC
|
||||
bool "KVM support for Virtual GIC"
|
||||
depends on KVM_ARM_HOST && OF
|
||||
select HAVE_KVM_IRQCHIP
|
||||
default y
|
||||
---help---
|
||||
Adds support for a hardware assisted, in-kernel GIC emulation.
|
||||
|
||||
config KVM_ARM_TIMER
|
||||
bool "KVM support for Architected Timers"
|
||||
depends on KVM_ARM_VGIC && ARM_ARCH_TIMER
|
||||
select HAVE_KVM_IRQCHIP
|
||||
default y
|
||||
---help---
|
||||
Adds support for the Architected Timers in virtual machines
|
||||
|
||||
source drivers/virtio/Kconfig
|
||||
|
||||
endif # VIRTUALIZATION
|
||||
|
|
|
|||
|
|
@ -19,3 +19,5 @@ kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
|
|||
obj-y += kvm-arm.o init.o interrupts.o
|
||||
obj-y += arm.o guest.o mmu.o emulate.o reset.o
|
||||
obj-y += coproc.o coproc_a15.o mmio.o psci.o
|
||||
obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
|
||||
obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,271 @@
|
|||
/*
|
||||
* Copyright (C) 2012 ARM Ltd.
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/kvm.h>
|
||||
#include <linux/kvm_host.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/arch_timer.h>
|
||||
|
||||
#include <asm/kvm_vgic.h>
|
||||
#include <asm/kvm_arch_timer.h>
|
||||
|
||||
static struct timecounter *timecounter;
|
||||
static struct workqueue_struct *wqueue;
|
||||
static struct kvm_irq_level timer_irq = {
|
||||
.level = 1,
|
||||
};
|
||||
|
||||
static cycle_t kvm_phys_timer_read(void)
|
||||
{
|
||||
return timecounter->cc->read(timecounter->cc);
|
||||
}
|
||||
|
||||
static bool timer_is_armed(struct arch_timer_cpu *timer)
|
||||
{
|
||||
return timer->armed;
|
||||
}
|
||||
|
||||
/* timer_arm: as in "arm the timer", not as in ARM the company */
|
||||
static void timer_arm(struct arch_timer_cpu *timer, u64 ns)
|
||||
{
|
||||
timer->armed = true;
|
||||
hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns),
|
||||
HRTIMER_MODE_ABS);
|
||||
}
|
||||
|
||||
static void timer_disarm(struct arch_timer_cpu *timer)
|
||||
{
|
||||
if (timer_is_armed(timer)) {
|
||||
hrtimer_cancel(&timer->timer);
|
||||
cancel_work_sync(&timer->expired);
|
||||
timer->armed = false;
|
||||
}
|
||||
}
|
||||
|
||||
static void kvm_timer_inject_irq(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
|
||||
|
||||
timer->cntv_ctl |= 1 << 1; /* Mask the interrupt in the guest */
|
||||
kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
|
||||
vcpu->arch.timer_cpu.irq->irq,
|
||||
vcpu->arch.timer_cpu.irq->level);
|
||||
}
|
||||
|
||||
static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id;
|
||||
|
||||
/*
|
||||
* We disable the timer in the world switch and let it be
|
||||
* handled by kvm_timer_sync_hwstate(). Getting a timer
|
||||
* interrupt at this point is a sure sign of some major
|
||||
* breakage.
|
||||
*/
|
||||
pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void kvm_timer_inject_irq_work(struct work_struct *work)
|
||||
{
|
||||
struct kvm_vcpu *vcpu;
|
||||
|
||||
vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
|
||||
vcpu->arch.timer_cpu.armed = false;
|
||||
kvm_timer_inject_irq(vcpu);
|
||||
}
|
||||
|
||||
static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)
|
||||
{
|
||||
struct arch_timer_cpu *timer;
|
||||
timer = container_of(hrt, struct arch_timer_cpu, timer);
|
||||
queue_work(wqueue, &timer->expired);
|
||||
return HRTIMER_NORESTART;
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_timer_flush_hwstate - prepare to move the virt timer to the cpu
|
||||
* @vcpu: The vcpu pointer
|
||||
*
|
||||
* Disarm any pending soft timers, since the world-switch code will write the
|
||||
* virtual timer state back to the physical CPU.
|
||||
*/
|
||||
void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
|
||||
|
||||
/*
|
||||
* We're about to run this vcpu again, so there is no need to
|
||||
* keep the background timer running, as we're about to
|
||||
* populate the CPU timer again.
|
||||
*/
|
||||
timer_disarm(timer);
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_timer_sync_hwstate - sync timer state from cpu
|
||||
* @vcpu: The vcpu pointer
|
||||
*
|
||||
* Check if the virtual timer was armed and either schedule a corresponding
|
||||
* soft timer or inject directly if already expired.
|
||||
*/
|
||||
void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
|
||||
cycle_t cval, now;
|
||||
u64 ns;
|
||||
|
||||
/* Check if the timer is enabled and unmasked first */
|
||||
if ((timer->cntv_ctl & 3) != 1)
|
||||
return;
|
||||
|
||||
cval = timer->cntv_cval;
|
||||
now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
|
||||
|
||||
BUG_ON(timer_is_armed(timer));
|
||||
|
||||
if (cval <= now) {
|
||||
/*
|
||||
* Timer has already expired while we were not
|
||||
* looking. Inject the interrupt and carry on.
|
||||
*/
|
||||
kvm_timer_inject_irq(vcpu);
|
||||
return;
|
||||
}
|
||||
|
||||
ns = cyclecounter_cyc2ns(timecounter->cc, cval - now);
|
||||
timer_arm(timer, ns);
|
||||
}
|
||||
|
||||
void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
|
||||
|
||||
INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);
|
||||
hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
|
||||
timer->timer.function = kvm_timer_expire;
|
||||
timer->irq = &timer_irq;
|
||||
}
|
||||
|
||||
static void kvm_timer_init_interrupt(void *info)
|
||||
{
|
||||
enable_percpu_irq(timer_irq.irq, 0);
|
||||
}
|
||||
|
||||
|
||||
static int kvm_timer_cpu_notify(struct notifier_block *self,
|
||||
unsigned long action, void *cpu)
|
||||
{
|
||||
switch (action) {
|
||||
case CPU_STARTING:
|
||||
case CPU_STARTING_FROZEN:
|
||||
kvm_timer_init_interrupt(NULL);
|
||||
break;
|
||||
case CPU_DYING:
|
||||
case CPU_DYING_FROZEN:
|
||||
disable_percpu_irq(timer_irq.irq);
|
||||
break;
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block kvm_timer_cpu_nb = {
|
||||
.notifier_call = kvm_timer_cpu_notify,
|
||||
};
|
||||
|
||||
static const struct of_device_id arch_timer_of_match[] = {
|
||||
{ .compatible = "arm,armv7-timer", },
|
||||
{},
|
||||
};
|
||||
|
||||
int kvm_timer_hyp_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned int ppi;
|
||||
int err;
|
||||
|
||||
timecounter = arch_timer_get_timecounter();
|
||||
if (!timecounter)
|
||||
return -ENODEV;
|
||||
|
||||
np = of_find_matching_node(NULL, arch_timer_of_match);
|
||||
if (!np) {
|
||||
kvm_err("kvm_arch_timer: can't find DT node\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ppi = irq_of_parse_and_map(np, 2);
|
||||
if (!ppi) {
|
||||
kvm_err("kvm_arch_timer: no virtual timer interrupt\n");
|
||||
err = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
err = request_percpu_irq(ppi, kvm_arch_timer_handler,
|
||||
"kvm guest timer", kvm_get_running_vcpus());
|
||||
if (err) {
|
||||
kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n",
|
||||
ppi, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
timer_irq.irq = ppi;
|
||||
|
||||
err = register_cpu_notifier(&kvm_timer_cpu_nb);
|
||||
if (err) {
|
||||
kvm_err("Cannot register timer CPU notifier\n");
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
wqueue = create_singlethread_workqueue("kvm_arch_timer");
|
||||
if (!wqueue) {
|
||||
err = -ENOMEM;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
kvm_info("%s IRQ%d\n", np->name, ppi);
|
||||
on_each_cpu(kvm_timer_init_interrupt, NULL, 1);
|
||||
|
||||
goto out;
|
||||
out_free:
|
||||
free_percpu_irq(ppi, kvm_get_running_vcpus());
|
||||
out:
|
||||
of_node_put(np);
|
||||
return err;
|
||||
}
|
||||
|
||||
void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
|
||||
|
||||
timer_disarm(timer);
|
||||
}
|
||||
|
||||
int kvm_timer_init(struct kvm *kvm)
|
||||
{
|
||||
if (timecounter && wqueue) {
|
||||
kvm->arch.timer.cntvoff = kvm_phys_timer_read();
|
||||
kvm->arch.timer.enabled = 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -54,11 +54,40 @@ static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page);
|
|||
static struct vfp_hard_struct __percpu *kvm_host_vfp_state;
|
||||
static unsigned long hyp_default_vectors;
|
||||
|
||||
/* Per-CPU variable containing the currently running vcpu. */
|
||||
static DEFINE_PER_CPU(struct kvm_vcpu *, kvm_arm_running_vcpu);
|
||||
|
||||
/* The VMID used in the VTTBR */
|
||||
static atomic64_t kvm_vmid_gen = ATOMIC64_INIT(1);
|
||||
static u8 kvm_next_vmid;
|
||||
static DEFINE_SPINLOCK(kvm_vmid_lock);
|
||||
|
||||
static bool vgic_present;
|
||||
|
||||
static void kvm_arm_set_running_vcpu(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
BUG_ON(preemptible());
|
||||
__get_cpu_var(kvm_arm_running_vcpu) = vcpu;
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_arm_get_running_vcpu - get the vcpu running on the current CPU.
|
||||
* Must be called from non-preemptible context
|
||||
*/
|
||||
struct kvm_vcpu *kvm_arm_get_running_vcpu(void)
|
||||
{
|
||||
BUG_ON(preemptible());
|
||||
return __get_cpu_var(kvm_arm_running_vcpu);
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_arm_get_running_vcpus - get the per-CPU array of currently running vcpus.
|
||||
*/
|
||||
struct kvm_vcpu __percpu **kvm_get_running_vcpus(void)
|
||||
{
|
||||
return &kvm_arm_running_vcpu;
|
||||
}
|
||||
|
||||
int kvm_arch_hardware_enable(void *garbage)
|
||||
{
|
||||
return 0;
|
||||
|
|
@ -157,6 +186,9 @@ int kvm_dev_ioctl_check_extension(long ext)
|
|||
{
|
||||
int r;
|
||||
switch (ext) {
|
||||
case KVM_CAP_IRQCHIP:
|
||||
r = vgic_present;
|
||||
break;
|
||||
case KVM_CAP_USER_MEMORY:
|
||||
case KVM_CAP_SYNC_MMU:
|
||||
case KVM_CAP_DESTROY_MEMORY_REGION_WORKS:
|
||||
|
|
@ -167,6 +199,8 @@ int kvm_dev_ioctl_check_extension(long ext)
|
|||
case KVM_CAP_COALESCED_MMIO:
|
||||
r = KVM_COALESCED_MMIO_PAGE_OFFSET;
|
||||
break;
|
||||
case KVM_CAP_ARM_SET_DEVICE_ADDR:
|
||||
r = 1;
|
||||
case KVM_CAP_NR_VCPUS:
|
||||
r = num_online_cpus();
|
||||
break;
|
||||
|
|
@ -255,6 +289,7 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
|
|||
void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
kvm_mmu_free_memory_caches(vcpu);
|
||||
kvm_timer_vcpu_terminate(vcpu);
|
||||
kmem_cache_free(kvm_vcpu_cache, vcpu);
|
||||
}
|
||||
|
||||
|
|
@ -286,8 +321,19 @@ int __attribute_const__ kvm_target_cpu(void)
|
|||
|
||||
int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Force users to call KVM_ARM_VCPU_INIT */
|
||||
vcpu->arch.target = -1;
|
||||
|
||||
/* Set up VGIC */
|
||||
ret = kvm_vgic_vcpu_init(vcpu);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set up the timer */
|
||||
kvm_timer_vcpu_init(vcpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -308,10 +354,13 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|||
*/
|
||||
if (cpumask_test_and_clear_cpu(cpu, &vcpu->arch.require_dcache_flush))
|
||||
flush_cache_all(); /* We'd really want v7_flush_dcache_all() */
|
||||
|
||||
kvm_arm_set_running_vcpu(vcpu);
|
||||
}
|
||||
|
||||
void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
kvm_arm_set_running_vcpu(NULL);
|
||||
}
|
||||
|
||||
int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
|
||||
|
|
@ -342,7 +391,7 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
|
|||
*/
|
||||
int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
|
||||
{
|
||||
return !!v->arch.irq_lines;
|
||||
return !!v->arch.irq_lines || kvm_vgic_vcpu_pending_irq(v);
|
||||
}
|
||||
|
||||
/* Just ensure a guest exit from a particular CPU */
|
||||
|
|
@ -596,6 +645,17 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
|
|||
|
||||
vcpu->arch.has_run_once = true;
|
||||
|
||||
/*
|
||||
* Initialize the VGIC before running a vcpu the first time on
|
||||
* this VM.
|
||||
*/
|
||||
if (irqchip_in_kernel(vcpu->kvm) &&
|
||||
unlikely(!vgic_initialized(vcpu->kvm))) {
|
||||
int ret = kvm_vgic_init(vcpu->kvm);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle the "start in power-off" case by calling into the
|
||||
* PSCI code.
|
||||
|
|
@ -661,6 +721,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
|
|||
if (vcpu->arch.pause)
|
||||
vcpu_pause(vcpu);
|
||||
|
||||
kvm_vgic_flush_hwstate(vcpu);
|
||||
kvm_timer_flush_hwstate(vcpu);
|
||||
|
||||
local_irq_disable();
|
||||
|
||||
/*
|
||||
|
|
@ -673,6 +736,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
|
|||
|
||||
if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) {
|
||||
local_irq_enable();
|
||||
kvm_timer_sync_hwstate(vcpu);
|
||||
kvm_vgic_sync_hwstate(vcpu);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -705,6 +770,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
|
|||
* Back from guest
|
||||
*************************************************************/
|
||||
|
||||
kvm_timer_sync_hwstate(vcpu);
|
||||
kvm_vgic_sync_hwstate(vcpu);
|
||||
|
||||
ret = handle_exit(vcpu, run, ret);
|
||||
}
|
||||
|
||||
|
|
@ -760,20 +828,49 @@ int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level)
|
|||
|
||||
trace_kvm_irq_line(irq_type, vcpu_idx, irq_num, irq_level->level);
|
||||
|
||||
if (irq_type != KVM_ARM_IRQ_TYPE_CPU)
|
||||
return -EINVAL;
|
||||
switch (irq_type) {
|
||||
case KVM_ARM_IRQ_TYPE_CPU:
|
||||
if (irqchip_in_kernel(kvm))
|
||||
return -ENXIO;
|
||||
|
||||
if (vcpu_idx >= nrcpus)
|
||||
return -EINVAL;
|
||||
if (vcpu_idx >= nrcpus)
|
||||
return -EINVAL;
|
||||
|
||||
vcpu = kvm_get_vcpu(kvm, vcpu_idx);
|
||||
if (!vcpu)
|
||||
return -EINVAL;
|
||||
vcpu = kvm_get_vcpu(kvm, vcpu_idx);
|
||||
if (!vcpu)
|
||||
return -EINVAL;
|
||||
|
||||
if (irq_num > KVM_ARM_IRQ_CPU_FIQ)
|
||||
return -EINVAL;
|
||||
if (irq_num > KVM_ARM_IRQ_CPU_FIQ)
|
||||
return -EINVAL;
|
||||
|
||||
return vcpu_interrupt_line(vcpu, irq_num, level);
|
||||
return vcpu_interrupt_line(vcpu, irq_num, level);
|
||||
case KVM_ARM_IRQ_TYPE_PPI:
|
||||
if (!irqchip_in_kernel(kvm))
|
||||
return -ENXIO;
|
||||
|
||||
if (vcpu_idx >= nrcpus)
|
||||
return -EINVAL;
|
||||
|
||||
vcpu = kvm_get_vcpu(kvm, vcpu_idx);
|
||||
if (!vcpu)
|
||||
return -EINVAL;
|
||||
|
||||
if (irq_num < VGIC_NR_SGIS || irq_num >= VGIC_NR_PRIVATE_IRQS)
|
||||
return -EINVAL;
|
||||
|
||||
return kvm_vgic_inject_irq(kvm, vcpu->vcpu_id, irq_num, level);
|
||||
case KVM_ARM_IRQ_TYPE_SPI:
|
||||
if (!irqchip_in_kernel(kvm))
|
||||
return -ENXIO;
|
||||
|
||||
if (irq_num < VGIC_NR_PRIVATE_IRQS ||
|
||||
irq_num > KVM_ARM_IRQ_GIC_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
return kvm_vgic_inject_irq(kvm, 0, irq_num, level);
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
long kvm_arch_vcpu_ioctl(struct file *filp,
|
||||
|
|
@ -827,10 +924,49 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int kvm_vm_ioctl_set_device_addr(struct kvm *kvm,
|
||||
struct kvm_arm_device_addr *dev_addr)
|
||||
{
|
||||
unsigned long dev_id, type;
|
||||
|
||||
dev_id = (dev_addr->id & KVM_ARM_DEVICE_ID_MASK) >>
|
||||
KVM_ARM_DEVICE_ID_SHIFT;
|
||||
type = (dev_addr->id & KVM_ARM_DEVICE_TYPE_MASK) >>
|
||||
KVM_ARM_DEVICE_TYPE_SHIFT;
|
||||
|
||||
switch (dev_id) {
|
||||
case KVM_ARM_DEVICE_VGIC_V2:
|
||||
if (!vgic_present)
|
||||
return -ENXIO;
|
||||
return kvm_vgic_set_addr(kvm, type, dev_addr->addr);
|
||||
default:
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
long kvm_arch_vm_ioctl(struct file *filp,
|
||||
unsigned int ioctl, unsigned long arg)
|
||||
{
|
||||
return -EINVAL;
|
||||
struct kvm *kvm = filp->private_data;
|
||||
void __user *argp = (void __user *)arg;
|
||||
|
||||
switch (ioctl) {
|
||||
case KVM_CREATE_IRQCHIP: {
|
||||
if (vgic_present)
|
||||
return kvm_vgic_create(kvm);
|
||||
else
|
||||
return -ENXIO;
|
||||
}
|
||||
case KVM_ARM_SET_DEVICE_ADDR: {
|
||||
struct kvm_arm_device_addr dev_addr;
|
||||
|
||||
if (copy_from_user(&dev_addr, argp, sizeof(dev_addr)))
|
||||
return -EFAULT;
|
||||
return kvm_vm_ioctl_set_device_addr(kvm, &dev_addr);
|
||||
}
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static void cpu_init_hyp_mode(void *vector)
|
||||
|
|
@ -960,6 +1096,24 @@ static int init_hyp_mode(void)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Init HYP view of VGIC
|
||||
*/
|
||||
err = kvm_vgic_hyp_init();
|
||||
if (err)
|
||||
goto out_free_vfp;
|
||||
|
||||
#ifdef CONFIG_KVM_ARM_VGIC
|
||||
vgic_present = true;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Init HYP architected timer support
|
||||
*/
|
||||
err = kvm_timer_hyp_init();
|
||||
if (err)
|
||||
goto out_free_mappings;
|
||||
|
||||
kvm_info("Hyp mode initialized successfully\n");
|
||||
return 0;
|
||||
out_free_vfp:
|
||||
|
|
|
|||
|
|
@ -222,6 +222,10 @@ static const struct coproc_reg cp15_regs[] = {
|
|||
NULL, reset_unknown, c13_TID_URO },
|
||||
{ CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
|
||||
NULL, reset_unknown, c13_TID_PRIV },
|
||||
|
||||
/* CNTKCTL: swapped by interrupt.S. */
|
||||
{ CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
|
||||
NULL, reset_val, c14_CNTKCTL, 0x00000000 },
|
||||
};
|
||||
|
||||
/* Target specific emulation tables */
|
||||
|
|
|
|||
|
|
@ -94,6 +94,9 @@ ENTRY(__kvm_vcpu_run)
|
|||
|
||||
save_host_regs
|
||||
|
||||
restore_vgic_state
|
||||
restore_timer_state
|
||||
|
||||
@ Store hardware CP15 state and load guest state
|
||||
read_cp15_state store_to_vcpu = 0
|
||||
write_cp15_state read_from_vcpu = 1
|
||||
|
|
@ -187,6 +190,9 @@ after_vfp_restore:
|
|||
read_cp15_state store_to_vcpu = 1
|
||||
write_cp15_state read_from_vcpu = 0
|
||||
|
||||
save_timer_state
|
||||
save_vgic_state
|
||||
|
||||
restore_host_regs
|
||||
clrex @ Clear exclusive monitor
|
||||
mov r0, r1 @ Return the return code
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4))
|
||||
#define VCPU_USR_SP (VCPU_USR_REG(13))
|
||||
#define VCPU_USR_LR (VCPU_USR_REG(14))
|
||||
|
|
@ -298,6 +300,14 @@ vcpu .req r0 @ vcpu pointer always in r0
|
|||
str r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
|
||||
str r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
|
||||
.endif
|
||||
|
||||
mrc p15, 0, r2, c14, c1, 0 @ CNTKCTL
|
||||
|
||||
.if \store_to_vcpu == 0
|
||||
push {r2}
|
||||
.else
|
||||
str r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
|
|
@ -308,6 +318,14 @@ vcpu .req r0 @ vcpu pointer always in r0
|
|||
* Assumes vcpu pointer in vcpu reg
|
||||
*/
|
||||
.macro write_cp15_state read_from_vcpu
|
||||
.if \read_from_vcpu == 0
|
||||
pop {r2}
|
||||
.else
|
||||
ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
|
||||
.endif
|
||||
|
||||
mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL
|
||||
|
||||
.if \read_from_vcpu == 0
|
||||
pop {r2-r12}
|
||||
.else
|
||||
|
|
@ -369,6 +387,49 @@ vcpu .req r0 @ vcpu pointer always in r0
|
|||
* Assumes vcpu pointer in vcpu reg
|
||||
*/
|
||||
.macro save_vgic_state
|
||||
#ifdef CONFIG_KVM_ARM_VGIC
|
||||
/* Get VGIC VCTRL base into r2 */
|
||||
ldr r2, [vcpu, #VCPU_KVM]
|
||||
ldr r2, [r2, #KVM_VGIC_VCTRL]
|
||||
cmp r2, #0
|
||||
beq 2f
|
||||
|
||||
/* Compute the address of struct vgic_cpu */
|
||||
add r11, vcpu, #VCPU_VGIC_CPU
|
||||
|
||||
/* Save all interesting registers */
|
||||
ldr r3, [r2, #GICH_HCR]
|
||||
ldr r4, [r2, #GICH_VMCR]
|
||||
ldr r5, [r2, #GICH_MISR]
|
||||
ldr r6, [r2, #GICH_EISR0]
|
||||
ldr r7, [r2, #GICH_EISR1]
|
||||
ldr r8, [r2, #GICH_ELRSR0]
|
||||
ldr r9, [r2, #GICH_ELRSR1]
|
||||
ldr r10, [r2, #GICH_APR]
|
||||
|
||||
str r3, [r11, #VGIC_CPU_HCR]
|
||||
str r4, [r11, #VGIC_CPU_VMCR]
|
||||
str r5, [r11, #VGIC_CPU_MISR]
|
||||
str r6, [r11, #VGIC_CPU_EISR]
|
||||
str r7, [r11, #(VGIC_CPU_EISR + 4)]
|
||||
str r8, [r11, #VGIC_CPU_ELRSR]
|
||||
str r9, [r11, #(VGIC_CPU_ELRSR + 4)]
|
||||
str r10, [r11, #VGIC_CPU_APR]
|
||||
|
||||
/* Clear GICH_HCR */
|
||||
mov r5, #0
|
||||
str r5, [r2, #GICH_HCR]
|
||||
|
||||
/* Save list registers */
|
||||
add r2, r2, #GICH_LR0
|
||||
add r3, r11, #VGIC_CPU_LR
|
||||
ldr r4, [r11, #VGIC_CPU_NR_LR]
|
||||
1: ldr r6, [r2], #4
|
||||
str r6, [r3], #4
|
||||
subs r4, r4, #1
|
||||
bne 1b
|
||||
2:
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
|
|
@ -377,6 +438,109 @@ vcpu .req r0 @ vcpu pointer always in r0
|
|||
* Assumes vcpu pointer in vcpu reg
|
||||
*/
|
||||
.macro restore_vgic_state
|
||||
#ifdef CONFIG_KVM_ARM_VGIC
|
||||
/* Get VGIC VCTRL base into r2 */
|
||||
ldr r2, [vcpu, #VCPU_KVM]
|
||||
ldr r2, [r2, #KVM_VGIC_VCTRL]
|
||||
cmp r2, #0
|
||||
beq 2f
|
||||
|
||||
/* Compute the address of struct vgic_cpu */
|
||||
add r11, vcpu, #VCPU_VGIC_CPU
|
||||
|
||||
/* We only restore a minimal set of registers */
|
||||
ldr r3, [r11, #VGIC_CPU_HCR]
|
||||
ldr r4, [r11, #VGIC_CPU_VMCR]
|
||||
ldr r8, [r11, #VGIC_CPU_APR]
|
||||
|
||||
str r3, [r2, #GICH_HCR]
|
||||
str r4, [r2, #GICH_VMCR]
|
||||
str r8, [r2, #GICH_APR]
|
||||
|
||||
/* Restore list registers */
|
||||
add r2, r2, #GICH_LR0
|
||||
add r3, r11, #VGIC_CPU_LR
|
||||
ldr r4, [r11, #VGIC_CPU_NR_LR]
|
||||
1: ldr r6, [r3], #4
|
||||
str r6, [r2], #4
|
||||
subs r4, r4, #1
|
||||
bne 1b
|
||||
2:
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#define CNTHCTL_PL1PCTEN (1 << 0)
|
||||
#define CNTHCTL_PL1PCEN (1 << 1)
|
||||
|
||||
/*
|
||||
* Save the timer state onto the VCPU and allow physical timer/counter access
|
||||
* for the host.
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
* Clobbers r2-r5
|
||||
*/
|
||||
.macro save_timer_state
|
||||
#ifdef CONFIG_KVM_ARM_TIMER
|
||||
ldr r4, [vcpu, #VCPU_KVM]
|
||||
ldr r2, [r4, #KVM_TIMER_ENABLED]
|
||||
cmp r2, #0
|
||||
beq 1f
|
||||
|
||||
mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
str r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
|
||||
bic r2, #1 @ Clear ENABLE
|
||||
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
isb
|
||||
|
||||
mrrc p15, 3, r2, r3, c14 @ CNTV_CVAL
|
||||
ldr r4, =VCPU_TIMER_CNTV_CVAL
|
||||
add r5, vcpu, r4
|
||||
strd r2, r3, [r5]
|
||||
|
||||
1:
|
||||
#endif
|
||||
@ Allow physical timer/counter access for the host
|
||||
mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
orr r2, r2, #(CNTHCTL_PL1PCEN | CNTHCTL_PL1PCTEN)
|
||||
mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Load the timer state from the VCPU and deny physical timer/counter access
|
||||
* for the host.
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
* Clobbers r2-r5
|
||||
*/
|
||||
.macro restore_timer_state
|
||||
@ Disallow physical timer access for the guest
|
||||
@ Physical counter access is allowed
|
||||
mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
orr r2, r2, #CNTHCTL_PL1PCTEN
|
||||
bic r2, r2, #CNTHCTL_PL1PCEN
|
||||
mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
|
||||
#ifdef CONFIG_KVM_ARM_TIMER
|
||||
ldr r4, [vcpu, #VCPU_KVM]
|
||||
ldr r2, [r4, #KVM_TIMER_ENABLED]
|
||||
cmp r2, #0
|
||||
beq 1f
|
||||
|
||||
ldr r2, [r4, #KVM_TIMER_CNTVOFF]
|
||||
ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
|
||||
mcrr p15, 4, r2, r3, c14 @ CNTVOFF
|
||||
|
||||
ldr r4, =VCPU_TIMER_CNTV_CVAL
|
||||
add r5, vcpu, r4
|
||||
ldrd r2, r3, [r5]
|
||||
mcrr p15, 3, r2, r3, c14 @ CNTV_CVAL
|
||||
isb
|
||||
|
||||
ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
|
||||
and r2, r2, #3
|
||||
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
1:
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.equ vmentry, 0
|
||||
|
|
|
|||
|
|
@ -148,6 +148,9 @@ int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
|
|||
if (mmio.is_write)
|
||||
memcpy(mmio.data, vcpu_reg(vcpu, rt), mmio.len);
|
||||
|
||||
if (vgic_handle_mmio(vcpu, run, &mmio))
|
||||
return 1;
|
||||
|
||||
kvm_prepare_mmio(run, &mmio);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -20,16 +20,45 @@
|
|||
|
||||
#define GIC_DIST_CTRL 0x000
|
||||
#define GIC_DIST_CTR 0x004
|
||||
#define GIC_DIST_IGROUP 0x080
|
||||
#define GIC_DIST_ENABLE_SET 0x100
|
||||
#define GIC_DIST_ENABLE_CLEAR 0x180
|
||||
#define GIC_DIST_PENDING_SET 0x200
|
||||
#define GIC_DIST_PENDING_CLEAR 0x280
|
||||
#define GIC_DIST_ACTIVE_BIT 0x300
|
||||
#define GIC_DIST_ACTIVE_SET 0x300
|
||||
#define GIC_DIST_ACTIVE_CLEAR 0x380
|
||||
#define GIC_DIST_PRI 0x400
|
||||
#define GIC_DIST_TARGET 0x800
|
||||
#define GIC_DIST_CONFIG 0xc00
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||||
#define GIC_DIST_SOFTINT 0xf00
|
||||
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||||
#define GICH_HCR 0x0
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||||
#define GICH_VTR 0x4
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||||
#define GICH_VMCR 0x8
|
||||
#define GICH_MISR 0x10
|
||||
#define GICH_EISR0 0x20
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||||
#define GICH_EISR1 0x24
|
||||
#define GICH_ELRSR0 0x30
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||||
#define GICH_ELRSR1 0x34
|
||||
#define GICH_APR 0xf0
|
||||
#define GICH_LR0 0x100
|
||||
|
||||
#define GICH_HCR_EN (1 << 0)
|
||||
#define GICH_HCR_UIE (1 << 1)
|
||||
|
||||
#define GICH_LR_VIRTUALID (0x3ff << 0)
|
||||
#define GICH_LR_PHYSID_CPUID_SHIFT (10)
|
||||
#define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT)
|
||||
#define GICH_LR_STATE (3 << 28)
|
||||
#define GICH_LR_PENDING_BIT (1 << 28)
|
||||
#define GICH_LR_ACTIVE_BIT (1 << 29)
|
||||
#define GICH_LR_EOI (1 << 19)
|
||||
|
||||
#define GICH_MISR_EOI (1 << 0)
|
||||
#define GICH_MISR_U (1 << 1)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct device_node;
|
||||
|
||||
extern struct irq_chip gic_arch_extn;
|
||||
|
|
@ -45,4 +74,6 @@ static inline void gic_init(unsigned int nr, int start,
|
|||
gic_init_bases(nr, start, dist, cpu, 0, NULL);
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -637,6 +637,7 @@ struct kvm_ppc_smmu_info {
|
|||
#define KVM_CAP_PPC_BOOKE_WATCHDOG 83
|
||||
#define KVM_CAP_PPC_HTAB_FD 84
|
||||
#define KVM_CAP_ARM_PSCI 87
|
||||
#define KVM_CAP_ARM_SET_DEVICE_ADDR 88
|
||||
|
||||
#ifdef KVM_CAP_IRQ_ROUTING
|
||||
|
||||
|
|
@ -784,6 +785,11 @@ struct kvm_msi {
|
|||
__u8 pad[16];
|
||||
};
|
||||
|
||||
struct kvm_arm_device_addr {
|
||||
__u64 id;
|
||||
__u64 addr;
|
||||
};
|
||||
|
||||
/*
|
||||
* ioctls for VM fds
|
||||
*/
|
||||
|
|
@ -869,6 +875,8 @@ struct kvm_s390_ucas_mapping {
|
|||
#define KVM_ALLOCATE_RMA _IOR(KVMIO, 0xa9, struct kvm_allocate_rma)
|
||||
/* Available with KVM_CAP_PPC_HTAB_FD */
|
||||
#define KVM_PPC_GET_HTAB_FD _IOW(KVMIO, 0xaa, struct kvm_get_htab_fd)
|
||||
/* Available with KVM_CAP_ARM_SET_DEVICE_ADDR */
|
||||
#define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
|
||||
|
||||
/*
|
||||
* ioctls for vcpu fds
|
||||
|
|
|
|||
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