ARM: SoC: late updates
A few updates that we merged late but are low risk for regressions for
other platforms (and a few other straggling patches):
- I mis-tagged the 'drivers' branch, and missed 3 patches. Merged in
here. They're for a driver for the PL353 SRAM controller and a build
fix for the qualcomm scm driver.
- A new platform, RDA Micro RDA8810PL (Cortex-A5 w/ integrated Vivante
GPU, 256MB RAM, Wifi). This includes some acked platform-specific
drivers (serial, etc). This also include DTs for two boards with this
SoC, OrangePi 2G and OrangePi i86.
- i.MX8 is another new platform (NXP, 4x Cortex-A53 + Cortex-M4, 4K
video playback offload). This is the first i.MX 64-bit SoC.
- Some minor updates to Samsung boards (adding a few peripherals in
DTs).
- Small rework for SMP bootup on STi platforms.
- A couple of TEE driver fixes.
- A couple of new config options (bcm2835 thermal, Uniphier MDMAC)
enabled in defconfigs.
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlwv4lAPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3JQsQAIcvwnI8rKPEskd20kNaj5bCUlG2hcIN/VoT
scq1iCXpICOF53jBQvDoe48n+Ji4mI2VD7AIZD8XVppR+aHgpy8fkjX+uz8Ap0dG
8B2y9vJ6nomrxKslnFEUk6LxpsaadpzTQDlcHAQvPdJxkvmMuA2b8LMGZhoAQ+dB
lCw/qbjmoMEAV+dKXqRu62wwjZ10j4B7ex1XB1gnfjJYy+Splnd5fkdFCvd3wk+7
BOH2iGROyLC0TC6ggqv45NNm6EykO9XqI5nq/3VHq9aBVJVWtFUQhDScjNf6qyYM
mvUg6ZxmiTyIjhN+erttFXtxSKCH0BIdlBLZzaQ9W2XbTKMgzUlgK5GjQGqKCG6A
QZHs9oe/TQuaHZ2ghMRbxcTWZC8Zdi1hYYa8fB7yNCZKnPNLRaA5P7O/3/s796B6
DXpIHlU4lpyRdg26Zxh+FXYIXLsUYk9WNcwhjFbUQ/WXP3L9qf7FUU1EeSQeGDHU
yRCE+kuKFs5FJnAZYXQ+0BCv0v8GFLMKTXDTbYtVFt0QDWVeeWwRt6gCOcHv1vBI
IbZ0QLn1fzW2efgsXXB9i9VXO5AiP3EMx2A9Lqvrv+ufRXzQlBPbYZhN/Lp+BuDC
moWdT5Cmye00uu35wY6H7Ycd+CO29dJ/B+hKbgqjyzFkZJiwWnPoeVQH2M1IkjOj
IydIEbEo
=qgZw
-----END PGP SIGNATURE-----
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull more ARM SoC updates from Olof Johansson:
"A few updates that we merged late but are low risk for regressions for
other platforms (and a few other straggling patches):
- I mis-tagged the 'drivers' branch, and missed 3 patches. Merged in
here. They're for a driver for the PL353 SRAM controller and a
build fix for the qualcomm scm driver.
- A new platform, RDA Micro RDA8810PL (Cortex-A5 w/ integrated
Vivante GPU, 256MB RAM, Wifi). This includes some acked
platform-specific drivers (serial, etc). This also include DTs for
two boards with this SoC, OrangePi 2G and OrangePi i86.
- i.MX8 is another new platform (NXP, 4x Cortex-A53 + Cortex-M4, 4K
video playback offload). This is the first i.MX 64-bit SoC.
- Some minor updates to Samsung boards (adding a few peripherals in
DTs).
- Small rework for SMP bootup on STi platforms.
- A couple of TEE driver fixes.
- A couple of new config options (bcm2835 thermal, Uniphier MDMAC)
enabled in defconfigs"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits)
ARM: multi_v7_defconfig: enable CONFIG_UNIPHIER_MDMAC
arm64: defconfig: Re-enable bcm2835-thermal driver
MAINTAINERS: Add entry for RDA Micro SoC architecture
tty: serial: Add RDA8810PL UART driver
ARM: dts: rda8810pl: Add interrupt support for UART
dt-bindings: serial: Document RDA Micro UART
ARM: dts: rda8810pl: Add timer support
ARM: dts: Add devicetree for OrangePi i96 board
ARM: dts: Add devicetree for OrangePi 2G IoT board
ARM: dts: Add devicetree for RDA8810PL SoC
ARM: Prepare RDA8810PL SoC
dt-bindings: arm: Document RDA8810PL and reference boards
dt-bindings: Add RDA Micro vendor prefix
ARM: sti: remove pen_release and boot_lock
arm64: dts: exynos: Add Bluetooth chip to TM2(e) boards
arm64: dts: imx8mq-evk: enable watchdog
arm64: dts: imx8mq: add watchdog devices
MAINTAINERS: add i.MX8 DT path to i.MX architecture
arm64: add support for i.MX8M EVK board
arm64: add basic DTS for i.MX8MQ
...
This commit is contained in:
Linus Torvalds
Коммит
b23b0ea370
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|
@ -1028,6 +1028,12 @@
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specified address. The serial port must already be
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setup and configured. Options are not yet supported.
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rda,<addr>
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Start an early, polled-mode console on a serial port
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of an RDA Micro SoC, such as RDA8810PL, at the
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specified address. The serial port must already be
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setup and configured. Options are not yet supported.
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smh Use ARM semihosting calls for early console.
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s3c2410,<addr>
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|
|
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@ -0,0 +1,17 @@
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RDA Micro platforms device tree bindings
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----------------------------------------
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RDA8810PL SoC
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=============
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Required root node properties:
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- compatible : must contain "rda,8810pl"
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Boards:
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Root node property compatible must contain, depending on board:
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- Orange Pi 2G-IoT: "xunlong,orangepi-2g-iot"
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- Orange Pi i96: "xunlong,orangepi-i96"
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@ -0,0 +1,47 @@
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Device tree bindings for ARM PL353 static memory controller
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PL353 static memory controller supports two kinds of memory
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interfaces.i.e NAND and SRAM/NOR interfaces.
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The actual devices are instantiated from the child nodes of pl353 smc node.
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Required properties:
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- compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell".
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- reg : Controller registers map and length.
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- clock-names : List of input clock names - "memclk", "apb_pclk"
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(See clock bindings for details).
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- clocks : Clock phandles (see clock bindings for details).
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- address-cells : Must be 2.
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- size-cells : Must be 1.
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Child nodes:
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For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
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supported as child nodes.
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for NAND partition information please refer the below file
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Documentation/devicetree/bindings/mtd/partition.txt
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Example:
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smcc: memory-controller@e000e000
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compatible = "arm,pl353-smc-r2p1", "arm,primecell";
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clock-names = "memclk", "apb_pclk";
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clocks = <&clkc 11>, <&clkc 44>;
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reg = <0xe000e000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
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0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
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0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
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nand_0: flash@e1000000 {
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compatible = "arm,pl353-nand-r2p1"
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reg = <0 0 0x1000000>;
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(...)
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};
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nor0: flash@e2000000 {
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compatible = "cfi-flash";
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reg = <1 0 0x2000000>;
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};
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nor1: flash@e4000000 {
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compatible = "cfi-flash";
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reg = <2 0 0x2000000>;
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};
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};
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|
|
@ -0,0 +1,17 @@
|
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RDA Micro UART
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|
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Required properties:
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- compatible : "rda,8810pl-uart" for RDA8810PL SoCs.
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- reg : Offset and length of the register set for the device.
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- interrupts : Should contain UART interrupt.
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- clocks : Phandle to the input clock.
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Example:
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uart2: serial@20a90000 {
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compatible = "rda,8810pl-uart";
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reg = <0x20a90000 0x1000>;
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interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_clk>;
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};
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|
@ -325,6 +325,7 @@ ralink Mediatek/Ralink Technology Corp.
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ramtron Ramtron International
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raspberrypi Raspberry Pi Foundation
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raydium Raydium Semiconductor Corp.
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rda Unisoc Communications, Inc.
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realtek Realtek Semiconductor Corp.
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renesas Renesas Electronics Corporation
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richtek Richtek Technology Corporation
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|
|
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15
MAINTAINERS
15
MAINTAINERS
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|
@ -1540,6 +1540,7 @@ F: arch/arm/mach-imx/
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F: arch/arm/mach-mxs/
|
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F: arch/arm/boot/dts/imx*
|
||||
F: arch/arm/configs/imx*_defconfig
|
||||
F: arch/arm64/boot/dts/freescale/imx*
|
||||
F: drivers/clk/imx/
|
||||
F: drivers/firmware/imx/
|
||||
F: drivers/soc/imx/
|
||||
|
|
@ -1967,6 +1968,20 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
|
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|
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ARM/RDA MICRO ARCHITECTURE
|
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M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-unisoc@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/boot/dts/rda8810pl-*
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F: drivers/clocksource/timer-rda.c
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F: drivers/irqchip/irq-rda-intc.c
|
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F: drivers/tty/serial/rda-uart.c
|
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F: Documentation/devicetree/bindings/arm/rda.txt
|
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F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt
|
||||
F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt
|
||||
F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt
|
||||
|
||||
ARM/REALTEK ARCHITECTURE
|
||||
M: Andreas Färber <afaerber@suse.de>
|
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
|
|||
|
|
@ -787,6 +787,8 @@ source "arch/arm/plat-pxa/Kconfig"
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|||
|
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source "arch/arm/mach-qcom/Kconfig"
|
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|
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source "arch/arm/mach-rda/Kconfig"
|
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|
||||
source "arch/arm/mach-realview/Kconfig"
|
||||
|
||||
source "arch/arm/mach-rockchip/Kconfig"
|
||||
|
|
|
|||
|
|
@ -202,6 +202,7 @@ machine-$(CONFIG_ARCH_ORION5X) += orion5x
|
|||
machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
|
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machine-$(CONFIG_ARCH_PXA) += pxa
|
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machine-$(CONFIG_ARCH_QCOM) += qcom
|
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machine-$(CONFIG_ARCH_RDA) += rda
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machine-$(CONFIG_ARCH_REALVIEW) += realview
|
||||
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
|
||||
machine-$(CONFIG_ARCH_RPC) += rpc
|
||||
|
|
|
|||
|
|
@ -822,6 +822,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
|||
qcom-msm8974-sony-xperia-castor.dtb \
|
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qcom-msm8974-sony-xperia-honami.dtb \
|
||||
qcom-mdm9615-wp8548-mangoh-green.dtb
|
||||
dtb-$(CONFIG_ARCH_RDA) += \
|
||||
rda8810pl-orangepi-2g-iot.dtb \
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rda8810pl-orangepi-i96.dtb
|
||||
dtb-$(CONFIG_ARCH_REALVIEW) += \
|
||||
arm-realview-pb1176.dtb \
|
||||
arm-realview-pb11mp.dtb \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
* Copyright (c) 2018 Manivannan Sadhasivam
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
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#include "rda8810pl.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xunlong,orangepi-2g-iot", "rda,8810pl";
|
||||
model = "Orange Pi 2G-IoT";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:921600n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <921600>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
* Copyright (c) 2018 Manivannan Sadhasivam
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rda8810pl.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xunlong,orangepi-i96", "rda,8810pl";
|
||||
model = "Orange Pi i96";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart2;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:921600n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <921600>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* RDA8810PL SoC
|
||||
*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
* Copyright (c) 2018 Manivannan Sadhasivam
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "rda,8810pl";
|
||||
interrupt-parent = <&intc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
sram@100000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x100000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
apb@20800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x20800000 0x100000>;
|
||||
|
||||
intc: interrupt-controller@0 {
|
||||
compatible = "rda,8810pl-intc";
|
||||
reg = <0x0 0x1000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
apb@20900000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x20900000 0x100000>;
|
||||
|
||||
timer@10000 {
|
||||
compatible = "rda,8810pl-timer";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hwtimer", "ostimer";
|
||||
};
|
||||
};
|
||||
|
||||
apb@20a00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x20a00000 0x100000>;
|
||||
|
||||
uart1: serial@0 {
|
||||
compatible = "rda,8810pl-uart";
|
||||
reg = <0x0 0x1000>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@10000 {
|
||||
compatible = "rda,8810pl-uart";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@90000 {
|
||||
compatible = "rda,8810pl-uart";
|
||||
reg = <0x90000 0x1000>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
l2: cache-controller@21100000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x21100000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -867,6 +867,7 @@ CONFIG_STM32_DMA=y
|
|||
CONFIG_STM32_DMAMUX=y
|
||||
CONFIG_STM32_MDMA=y
|
||||
CONFIG_TEGRA20_APB_DMA=y
|
||||
CONFIG_UNIPHIER_MDMAC=y
|
||||
CONFIG_XILINX_DMA=y
|
||||
CONFIG_QCOM_BAM_DMA=y
|
||||
CONFIG_DW_DMAC=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
menuconfig ARCH_RDA
|
||||
bool "RDA Micro SoCs"
|
||||
depends on ARCH_MULTI_V7
|
||||
select RDA_INTC
|
||||
select RDA_TIMER
|
||||
help
|
||||
This enables support for the RDA Micro 8810PL SoC family.
|
||||
|
|
@ -0,0 +1 @@
|
|||
obj- += dummy.o
|
||||
|
|
@ -1,2 +1,2 @@
|
|||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
obj-$(CONFIG_ARCH_STI) += board-dt.o
|
||||
|
|
|
|||
|
|
@ -1,43 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-sti/headsmp.S
|
||||
*
|
||||
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
|
||||
* http://www.st.com
|
||||
*
|
||||
* Cloned from linux/arch/arm/mach-vexpress/headsmp.S
|
||||
*
|
||||
* Copyright (c) 2003 ARM Limited
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
/*
|
||||
* ST specific entry point for secondary CPUs. This provides
|
||||
* a "holding pen" into which all secondary cores are held until we're
|
||||
* ready for them to initialise.
|
||||
*/
|
||||
ENTRY(sti_secondary_startup)
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #15
|
||||
adr r4, 1f
|
||||
ldmia r4, {r5, r6}
|
||||
sub r4, r4, r5
|
||||
add r6, r6, r4
|
||||
pen: ldr r7, [r6]
|
||||
cmp r7, r0
|
||||
bne pen
|
||||
|
||||
/*
|
||||
* we've been released from the holding pen: secondary_stack
|
||||
* should now contain the SVC stack for this core
|
||||
*/
|
||||
b secondary_startup
|
||||
ENDPROC(sti_secondary_startup)
|
||||
|
||||
1: .long .
|
||||
.long pen_release
|
||||
|
|
@ -28,82 +28,33 @@
|
|||
|
||||
#include "smp.h"
|
||||
|
||||
static void write_pen_release(int val)
|
||||
{
|
||||
pen_release = val;
|
||||
smp_wmb();
|
||||
sync_cache_w(&pen_release);
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
static void sti_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
*/
|
||||
write_pen_release(-1);
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
static u32 __iomem *cpu_strt_ptr;
|
||||
|
||||
static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned long timeout;
|
||||
unsigned long entry_pa = __pa_symbol(secondary_startup);
|
||||
|
||||
/*
|
||||
* set synchronisation state between this boot processor
|
||||
* and the secondary one
|
||||
* Secondary CPU is initialised and started by a U-BOOTROM firmware.
|
||||
* Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.
|
||||
* Writing secondary_startup address at cpu_strt_ptr makes it to
|
||||
* jump directly to secondary_startup().
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
__raw_writel(entry_pa, cpu_strt_ptr);
|
||||
|
||||
/*
|
||||
* The secondary processor is waiting to be released from
|
||||
* the holding pen - release it, then wait for it to flag
|
||||
* that it has been released by resetting pen_release.
|
||||
*
|
||||
* Note that "pen_release" is the hardware CPU ID, whereas
|
||||
* "cpu" is Linux's internal ID.
|
||||
*/
|
||||
write_pen_release(cpu_logical_map(cpu));
|
||||
/* wmb so that data is actually written before cache flush is done */
|
||||
smp_wmb();
|
||||
sync_cache_w(cpu_strt_ptr);
|
||||
|
||||
/*
|
||||
* Send the secondary CPU a soft interrupt, thereby causing
|
||||
* it to jump to the secondary entrypoint.
|
||||
*/
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
smp_rmb();
|
||||
if (pen_release == -1)
|
||||
break;
|
||||
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return pen_release != -1 ? -ENOSYS : 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *scu_base;
|
||||
u32 __iomem *cpu_strt_ptr;
|
||||
u32 release_phys;
|
||||
int cpu;
|
||||
unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
|
||||
|
||||
|
|
@ -131,8 +82,8 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
|
|||
}
|
||||
|
||||
/*
|
||||
* holding pen is usually configured in SBC DMEM but can also be
|
||||
* in RAM.
|
||||
* cpu-release-addr is usually configured in SBC DMEM but can
|
||||
* also be in RAM.
|
||||
*/
|
||||
|
||||
if (!memblock_is_memory(release_phys))
|
||||
|
|
@ -142,22 +93,11 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
|
|||
cpu_strt_ptr =
|
||||
(u32 __iomem *)phys_to_virt(release_phys);
|
||||
|
||||
__raw_writel(entry_pa, cpu_strt_ptr);
|
||||
|
||||
/*
|
||||
* wmb so that data is actually written
|
||||
* before cache flush is done
|
||||
*/
|
||||
smp_wmb();
|
||||
sync_cache_w(cpu_strt_ptr);
|
||||
|
||||
if (!memblock_is_memory(release_phys))
|
||||
iounmap(cpu_strt_ptr);
|
||||
set_cpu_possible(cpu, true);
|
||||
}
|
||||
}
|
||||
|
||||
const struct smp_operations sti_smp_ops __initconst = {
|
||||
.smp_prepare_cpus = sti_smp_prepare_cpus,
|
||||
.smp_secondary_init = sti_secondary_init,
|
||||
.smp_boot_secondary = sti_boot_secondary,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -142,6 +142,14 @@ config ARCH_MVEBU
|
|||
- Armada 7K SoC Family
|
||||
- Armada 8K SoC Family
|
||||
|
||||
config ARCH_MXC
|
||||
bool "ARMv8 based NXP i.MX SoC family"
|
||||
select ARM64_ERRATUM_843419
|
||||
select ARM64_ERRATUM_845719
|
||||
help
|
||||
This enables support for the ARMv8 based SoCs in the
|
||||
NXP i.MX family.
|
||||
|
||||
config ARCH_QCOM
|
||||
bool "Qualcomm Platforms"
|
||||
select GPIOLIB
|
||||
|
|
|
|||
|
|
@ -1202,6 +1202,20 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&serial_3 {
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
max-speed = <3000000>;
|
||||
shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
|
||||
device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
|
||||
host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
|
||||
clock-names = "extclk";
|
||||
};
|
||||
};
|
||||
|
||||
&spi_1 {
|
||||
cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -544,6 +544,21 @@
|
|||
power-domains = <&pd_cam1>;
|
||||
};
|
||||
|
||||
cmu_imem: clock-controller@11060000 {
|
||||
compatible = "samsung,exynos5433-cmu-imem";
|
||||
reg = <0x11060000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"aclk_imem_sssx_266",
|
||||
"aclk_imem_266",
|
||||
"aclk_imem_200";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
|
||||
<&cmu_top CLK_DIV_ACLK_IMEM_266>,
|
||||
<&cmu_top CLK_DIV_ACLK_IMEM_200>;
|
||||
};
|
||||
|
||||
pd_gscl: power-domain@105c4000 {
|
||||
compatible = "samsung,exynos5433-pd";
|
||||
reg = <0x105c4000 0x20>;
|
||||
|
|
|
|||
|
|
@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
|
|||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
|
||||
|
|
|
|||
|
|
@ -0,0 +1,303 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mq.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP i.MX8MQ EVK";
|
||||
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-vsd-3v3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic@8 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x8>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3ab {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1675000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1625000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3625000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
vqmmc-supply = <&sw4_reg>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
||||
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2: regusdhc2grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
||||
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdog1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,623 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX8MQ_PINFUNC_H
|
||||
#define __DTS_IMX8MQ_PINFUNC_H
|
||||
|
||||
/*
|
||||
* The pin function ID is a tuple of
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
|
||||
#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
|
||||
|
||||
#endif /* __DTS_IMX8MQ_PINFUNC_H */
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "imx8mq-pinfunc.h"
|
||||
|
||||
/ {
|
||||
/* This should really be the GPC, but we need a driver for this first */
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
ckil: clock-ckil {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "ckil";
|
||||
};
|
||||
|
||||
osc_25m: clock-osc-25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "osc_25m";
|
||||
};
|
||||
|
||||
osc_27m: clock-osc-27m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
clock-output-names = "osc_27m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
clk_ext2: clock-ext2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext2";
|
||||
};
|
||||
|
||||
clk_ext3: clock-ext3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext3";
|
||||
};
|
||||
|
||||
clk_ext4: clock-ext4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency= <133000000>;
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
|
||||
interrupt-parent = <&gic>;
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x0 0x3e000000>;
|
||||
|
||||
bus@30000000 { /* AIPS1 */
|
||||
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30000000 0x30000000 0x400000>;
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30210000 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30220000 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30230000 0x10000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30240000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@30330000 {
|
||||
compatible = "fsl,imx8mq-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
|
||||
iomuxc_gpr: syscon@30340000 {
|
||||
compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
|
||||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
anatop: syscon@30360000 {
|
||||
compatible = "fsl,imx8mq-anatop", "syscon";
|
||||
reg = <0x30360000 0x10000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mq-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
|
||||
<&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "ckil", "osc_25m", "osc_27m",
|
||||
"clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog2: watchdog@30290000 {
|
||||
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30290000 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: watchdog@302a0000 {
|
||||
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x302a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
bus@30400000 { /* AIPS2 */
|
||||
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30400000 0x30400000 0x400000>;
|
||||
};
|
||||
|
||||
bus@30800000 { /* AIPS3 */
|
||||
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>;
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx8mq-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_UART1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx8mq-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
|
||||
<&clk IMX8MQ_CLK_UART3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx8mq-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
|
||||
<&clk IMX8MQ_CLK_UART2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a20000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a30000 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a40000 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a50000 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@30a60000 {
|
||||
compatible = "fsl,imx8mq-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a60000 0x10000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
|
||||
<&clk IMX8MQ_CLK_UART4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mq-usdhc",
|
||||
"fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: mmc@30b50000 {
|
||||
compatible = "fsl,imx8mq-usdhc",
|
||||
"fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MQ_CLK_ENET_REF>,
|
||||
<&clk IMX8MQ_CLK_ENET_PHY_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
fsl,num-tx-queues = <3>;
|
||||
fsl,num-rx-queues = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x38800000 0x10000>, /* GIC Dist */
|
||||
<0x38880000 0xc0000>, /* GICR */
|
||||
<0x31000000 0x2000>, /* GICC */
|
||||
<0x31010000 0x2000>, /* GICV */
|
||||
<0x31020000 0x2000>; /* GICH */
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -403,6 +403,7 @@ CONFIG_THERMAL_EMULATION=y
|
|||
CONFIG_ROCKCHIP_THERMAL=m
|
||||
CONFIG_RCAR_GEN3_THERMAL=y
|
||||
CONFIG_ARMADA_THERMAL=y
|
||||
CONFIG_BCM2835_THERMAL=m
|
||||
CONFIG_BRCMSTB_THERMAL=m
|
||||
CONFIG_EXYNOS_THERMAL=y
|
||||
CONFIG_TEGRA_BPMP_THERMAL=m
|
||||
|
|
|
|||
|
|
@ -145,6 +145,15 @@ config DA8XX_DDRCTL
|
|||
Texas Instruments da8xx SoCs. It's used to tweak various memory
|
||||
controller configuration options.
|
||||
|
||||
config PL353_SMC
|
||||
tristate "ARM PL35X Static Memory Controller(SMC) driver"
|
||||
default y
|
||||
depends on ARM
|
||||
depends on ARM_AMBA
|
||||
help
|
||||
This driver is for the ARM PL351/PL353 Static Memory
|
||||
Controller(SMC) module.
|
||||
|
||||
source "drivers/memory/samsung/Kconfig"
|
||||
source "drivers/memory/tegra/Kconfig"
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
|
|||
obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o
|
||||
obj-$(CONFIG_MTK_SMI) += mtk-smi.o
|
||||
obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
|
||||
obj-$(CONFIG_PL353_SMC) += pl353-smc.o
|
||||
|
||||
obj-$(CONFIG_SAMSUNG_MC) += samsung/
|
||||
obj-$(CONFIG_TEGRA_MC) += tegra/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,463 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM PL353 SMC driver
|
||||
*
|
||||
* Copyright (C) 2012 - 2018 Xilinx, Inc
|
||||
* Author: Punnaiah Choudary Kalluri <punnaiah@xilinx.com>
|
||||
* Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/pl353-smc.h>
|
||||
#include <linux/amba/bus.h>
|
||||
|
||||
/* Register definitions */
|
||||
#define PL353_SMC_MEMC_STATUS_OFFS 0 /* Controller status reg, RO */
|
||||
#define PL353_SMC_CFG_CLR_OFFS 0xC /* Clear config reg, WO */
|
||||
#define PL353_SMC_DIRECT_CMD_OFFS 0x10 /* Direct command reg, WO */
|
||||
#define PL353_SMC_SET_CYCLES_OFFS 0x14 /* Set cycles register, WO */
|
||||
#define PL353_SMC_SET_OPMODE_OFFS 0x18 /* Set opmode register, WO */
|
||||
#define PL353_SMC_ECC_STATUS_OFFS 0x400 /* ECC status register */
|
||||
#define PL353_SMC_ECC_MEMCFG_OFFS 0x404 /* ECC mem config reg */
|
||||
#define PL353_SMC_ECC_MEMCMD1_OFFS 0x408 /* ECC mem cmd1 reg */
|
||||
#define PL353_SMC_ECC_MEMCMD2_OFFS 0x40C /* ECC mem cmd2 reg */
|
||||
#define PL353_SMC_ECC_VALUE0_OFFS 0x418 /* ECC value 0 reg */
|
||||
|
||||
/* Controller status register specific constants */
|
||||
#define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT 6
|
||||
|
||||
/* Clear configuration register specific constants */
|
||||
#define PL353_SMC_CFG_CLR_INT_CLR_1 0x10
|
||||
#define PL353_SMC_CFG_CLR_ECC_INT_DIS_1 0x40
|
||||
#define PL353_SMC_CFG_CLR_INT_DIS_1 0x2
|
||||
#define PL353_SMC_CFG_CLR_DEFAULT_MASK (PL353_SMC_CFG_CLR_INT_CLR_1 | \
|
||||
PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \
|
||||
PL353_SMC_CFG_CLR_INT_DIS_1)
|
||||
|
||||
/* Set cycles register specific constants */
|
||||
#define PL353_SMC_SET_CYCLES_T0_MASK 0xF
|
||||
#define PL353_SMC_SET_CYCLES_T0_SHIFT 0
|
||||
#define PL353_SMC_SET_CYCLES_T1_MASK 0xF
|
||||
#define PL353_SMC_SET_CYCLES_T1_SHIFT 4
|
||||
#define PL353_SMC_SET_CYCLES_T2_MASK 0x7
|
||||
#define PL353_SMC_SET_CYCLES_T2_SHIFT 8
|
||||
#define PL353_SMC_SET_CYCLES_T3_MASK 0x7
|
||||
#define PL353_SMC_SET_CYCLES_T3_SHIFT 11
|
||||
#define PL353_SMC_SET_CYCLES_T4_MASK 0x7
|
||||
#define PL353_SMC_SET_CYCLES_T4_SHIFT 14
|
||||
#define PL353_SMC_SET_CYCLES_T5_MASK 0x7
|
||||
#define PL353_SMC_SET_CYCLES_T5_SHIFT 17
|
||||
#define PL353_SMC_SET_CYCLES_T6_MASK 0xF
|
||||
#define PL353_SMC_SET_CYCLES_T6_SHIFT 20
|
||||
|
||||
/* ECC status register specific constants */
|
||||
#define PL353_SMC_ECC_STATUS_BUSY BIT(6)
|
||||
#define PL353_SMC_ECC_REG_SIZE_OFFS 4
|
||||
|
||||
/* ECC memory config register specific constants */
|
||||
#define PL353_SMC_ECC_MEMCFG_MODE_MASK 0xC
|
||||
#define PL353_SMC_ECC_MEMCFG_MODE_SHIFT 2
|
||||
#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK 0xC
|
||||
|
||||
#define PL353_SMC_DC_UPT_NAND_REGS ((4 << 23) | /* CS: NAND chip */ \
|
||||
(2 << 21)) /* UpdateRegs operation */
|
||||
|
||||
#define PL353_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
|
||||
(0 << 8) | /* Read command */ \
|
||||
(0x30 << 16) | /* Read End command */ \
|
||||
(1 << 24)) /* Read End command calid */
|
||||
|
||||
#define PL353_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
|
||||
(5 << 8) | /* Read col change cmd */ \
|
||||
(0xE0 << 16) | /* Read col change end cmd */ \
|
||||
(1 << 24)) /* Read col change end cmd valid */
|
||||
#define PL353_NAND_ECC_BUSY_TIMEOUT (1 * HZ)
|
||||
/**
|
||||
* struct pl353_smc_data - Private smc driver structure
|
||||
* @memclk: Pointer to the peripheral clock
|
||||
* @aclk: Pointer to the APER clock
|
||||
*/
|
||||
struct pl353_smc_data {
|
||||
struct clk *memclk;
|
||||
struct clk *aclk;
|
||||
};
|
||||
|
||||
/* SMC virtual register base */
|
||||
static void __iomem *pl353_smc_base;
|
||||
|
||||
/**
|
||||
* pl353_smc_set_buswidth - Set memory buswidth
|
||||
* @bw: Memory buswidth (8 | 16)
|
||||
* Return: 0 on success or negative errno.
|
||||
*/
|
||||
int pl353_smc_set_buswidth(unsigned int bw)
|
||||
{
|
||||
if (bw != PL353_SMC_MEM_WIDTH_8 && bw != PL353_SMC_MEM_WIDTH_16)
|
||||
return -EINVAL;
|
||||
|
||||
writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS);
|
||||
writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
|
||||
PL353_SMC_DIRECT_CMD_OFFS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth);
|
||||
|
||||
/**
|
||||
* pl353_smc_set_cycles - Set memory timing parameters
|
||||
* @timings: NAND controller timing parameters
|
||||
*
|
||||
* Sets NAND chip specific timing parameters.
|
||||
*/
|
||||
void pl353_smc_set_cycles(u32 timings[])
|
||||
{
|
||||
/*
|
||||
* Set write pulse timing. This one is easy to extract:
|
||||
*
|
||||
* NWE_PULSE = tWP
|
||||
*/
|
||||
timings[0] &= PL353_SMC_SET_CYCLES_T0_MASK;
|
||||
timings[1] = (timings[1] & PL353_SMC_SET_CYCLES_T1_MASK) <<
|
||||
PL353_SMC_SET_CYCLES_T1_SHIFT;
|
||||
timings[2] = (timings[2] & PL353_SMC_SET_CYCLES_T2_MASK) <<
|
||||
PL353_SMC_SET_CYCLES_T2_SHIFT;
|
||||
timings[3] = (timings[3] & PL353_SMC_SET_CYCLES_T3_MASK) <<
|
||||
PL353_SMC_SET_CYCLES_T3_SHIFT;
|
||||
timings[4] = (timings[4] & PL353_SMC_SET_CYCLES_T4_MASK) <<
|
||||
PL353_SMC_SET_CYCLES_T4_SHIFT;
|
||||
timings[5] = (timings[5] & PL353_SMC_SET_CYCLES_T5_MASK) <<
|
||||
PL353_SMC_SET_CYCLES_T5_SHIFT;
|
||||
timings[6] = (timings[6] & PL353_SMC_SET_CYCLES_T6_MASK) <<
|
||||
PL353_SMC_SET_CYCLES_T6_SHIFT;
|
||||
timings[0] |= timings[1] | timings[2] | timings[3] |
|
||||
timings[4] | timings[5] | timings[6];
|
||||
|
||||
writel(timings[0], pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS);
|
||||
writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
|
||||
PL353_SMC_DIRECT_CMD_OFFS);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pl353_smc_set_cycles);
|
||||
|
||||
/**
|
||||
* pl353_smc_ecc_is_busy - Read ecc busy flag
|
||||
* Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle
|
||||
*/
|
||||
bool pl353_smc_ecc_is_busy(void)
|
||||
{
|
||||
return ((readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) &
|
||||
PL353_SMC_ECC_STATUS_BUSY) == PL353_SMC_ECC_STATUS_BUSY);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy);
|
||||
|
||||
/**
|
||||
* pl353_smc_get_ecc_val - Read ecc_valueN registers
|
||||
* @ecc_reg: Index of the ecc_value reg (0..3)
|
||||
* Return: the content of the requested ecc_value register.
|
||||
*
|
||||
* There are four valid ecc_value registers. The argument is truncated to stay
|
||||
* within this valid boundary.
|
||||
*/
|
||||
u32 pl353_smc_get_ecc_val(int ecc_reg)
|
||||
{
|
||||
u32 addr, reg;
|
||||
|
||||
addr = PL353_SMC_ECC_VALUE0_OFFS +
|
||||
(ecc_reg * PL353_SMC_ECC_REG_SIZE_OFFS);
|
||||
reg = readl(pl353_smc_base + addr);
|
||||
|
||||
return reg;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val);
|
||||
|
||||
/**
|
||||
* pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit
|
||||
* Return: the raw_int_status1 bit from the memc_status register
|
||||
*/
|
||||
int pl353_smc_get_nand_int_status_raw(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS);
|
||||
reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT;
|
||||
reg &= 1;
|
||||
|
||||
return reg;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw);
|
||||
|
||||
/**
|
||||
* pl353_smc_clr_nand_int - Clear NAND interrupt
|
||||
*/
|
||||
void pl353_smc_clr_nand_int(void)
|
||||
{
|
||||
writel(PL353_SMC_CFG_CLR_INT_CLR_1,
|
||||
pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int);
|
||||
|
||||
/**
|
||||
* pl353_smc_set_ecc_mode - Set SMC ECC mode
|
||||
* @mode: ECC mode (BYPASS, APB, MEM)
|
||||
* Return: 0 on success or negative errno.
|
||||
*/
|
||||
int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode)
|
||||
{
|
||||
u32 reg;
|
||||
int ret = 0;
|
||||
|
||||
switch (mode) {
|
||||
case PL353_SMC_ECCMODE_BYPASS:
|
||||
case PL353_SMC_ECCMODE_APB:
|
||||
case PL353_SMC_ECCMODE_MEM:
|
||||
|
||||
reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
|
||||
reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK;
|
||||
reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT;
|
||||
writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
|
||||
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode);
|
||||
|
||||
/**
|
||||
* pl353_smc_set_ecc_pg_size - Set SMC ECC page size
|
||||
* @pg_sz: ECC page size
|
||||
* Return: 0 on success or negative errno.
|
||||
*/
|
||||
int pl353_smc_set_ecc_pg_size(unsigned int pg_sz)
|
||||
{
|
||||
u32 reg, sz;
|
||||
|
||||
switch (pg_sz) {
|
||||
case 0:
|
||||
sz = 0;
|
||||
break;
|
||||
case SZ_512:
|
||||
sz = 1;
|
||||
break;
|
||||
case SZ_1K:
|
||||
sz = 2;
|
||||
break;
|
||||
case SZ_2K:
|
||||
sz = 3;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
|
||||
reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK;
|
||||
reg |= sz;
|
||||
writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size);
|
||||
|
||||
static int __maybe_unused pl353_smc_suspend(struct device *dev)
|
||||
{
|
||||
struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable(pl353_smc->memclk);
|
||||
clk_disable(pl353_smc->aclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused pl353_smc_resume(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
|
||||
|
||||
ret = clk_enable(pl353_smc->aclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot enable axi domain clock.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(pl353_smc->memclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot enable memory clock.\n");
|
||||
clk_disable(pl353_smc->aclk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct amba_driver pl353_smc_driver;
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend,
|
||||
pl353_smc_resume);
|
||||
|
||||
/**
|
||||
* pl353_smc_init_nand_interface - Initialize the NAND interface
|
||||
* @adev: Pointer to the amba_device struct
|
||||
* @nand_node: Pointer to the pl353_nand device_node struct
|
||||
*/
|
||||
static void pl353_smc_init_nand_interface(struct amba_device *adev,
|
||||
struct device_node *nand_node)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8);
|
||||
writel(PL353_SMC_CFG_CLR_INT_CLR_1,
|
||||
pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
|
||||
writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
|
||||
PL353_SMC_DIRECT_CMD_OFFS);
|
||||
|
||||
timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
|
||||
/* Wait till the ECC operation is complete */
|
||||
do {
|
||||
if (pl353_smc_ecc_is_busy())
|
||||
cpu_relax();
|
||||
else
|
||||
break;
|
||||
} while (!time_after_eq(jiffies, timeout));
|
||||
|
||||
if (time_after_eq(jiffies, timeout))
|
||||
return;
|
||||
|
||||
writel(PL353_NAND_ECC_CMD1,
|
||||
pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS);
|
||||
writel(PL353_NAND_ECC_CMD2,
|
||||
pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS);
|
||||
}
|
||||
|
||||
static const struct of_device_id pl353_smc_supported_children[] = {
|
||||
{
|
||||
.compatible = "cfi-flash"
|
||||
},
|
||||
{
|
||||
.compatible = "arm,pl353-nand-r2p1",
|
||||
.data = pl353_smc_init_nand_interface
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id)
|
||||
{
|
||||
struct pl353_smc_data *pl353_smc;
|
||||
struct device_node *child;
|
||||
struct resource *res;
|
||||
int err;
|
||||
struct device_node *of_node = adev->dev.of_node;
|
||||
static void (*init)(struct amba_device *adev,
|
||||
struct device_node *nand_node);
|
||||
const struct of_device_id *match = NULL;
|
||||
|
||||
pl353_smc = devm_kzalloc(&adev->dev, sizeof(*pl353_smc), GFP_KERNEL);
|
||||
if (!pl353_smc)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Get the NAND controller virtual address */
|
||||
res = &adev->res;
|
||||
pl353_smc_base = devm_ioremap_resource(&adev->dev, res);
|
||||
if (IS_ERR(pl353_smc_base))
|
||||
return PTR_ERR(pl353_smc_base);
|
||||
|
||||
pl353_smc->aclk = devm_clk_get(&adev->dev, "apb_pclk");
|
||||
if (IS_ERR(pl353_smc->aclk)) {
|
||||
dev_err(&adev->dev, "aclk clock not found.\n");
|
||||
return PTR_ERR(pl353_smc->aclk);
|
||||
}
|
||||
|
||||
pl353_smc->memclk = devm_clk_get(&adev->dev, "memclk");
|
||||
if (IS_ERR(pl353_smc->memclk)) {
|
||||
dev_err(&adev->dev, "memclk clock not found.\n");
|
||||
return PTR_ERR(pl353_smc->memclk);
|
||||
}
|
||||
|
||||
err = clk_prepare_enable(pl353_smc->aclk);
|
||||
if (err) {
|
||||
dev_err(&adev->dev, "Unable to enable AXI clock.\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_prepare_enable(pl353_smc->memclk);
|
||||
if (err) {
|
||||
dev_err(&adev->dev, "Unable to enable memory clock.\n");
|
||||
goto out_clk_dis_aper;
|
||||
}
|
||||
|
||||
amba_set_drvdata(adev, pl353_smc);
|
||||
|
||||
/* clear interrupts */
|
||||
writel(PL353_SMC_CFG_CLR_DEFAULT_MASK,
|
||||
pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
|
||||
|
||||
/* Find compatible children. Only a single child is supported */
|
||||
for_each_available_child_of_node(of_node, child) {
|
||||
match = of_match_node(pl353_smc_supported_children, child);
|
||||
if (!match) {
|
||||
dev_warn(&adev->dev, "unsupported child node\n");
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (!match) {
|
||||
dev_err(&adev->dev, "no matching children\n");
|
||||
goto out_clk_disable;
|
||||
}
|
||||
|
||||
init = match->data;
|
||||
if (init)
|
||||
init(adev, child);
|
||||
of_platform_device_create(child, NULL, &adev->dev);
|
||||
|
||||
return 0;
|
||||
|
||||
out_clk_disable:
|
||||
clk_disable_unprepare(pl353_smc->memclk);
|
||||
out_clk_dis_aper:
|
||||
clk_disable_unprepare(pl353_smc->aclk);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int pl353_smc_remove(struct amba_device *adev)
|
||||
{
|
||||
struct pl353_smc_data *pl353_smc = amba_get_drvdata(adev);
|
||||
|
||||
clk_disable_unprepare(pl353_smc->memclk);
|
||||
clk_disable_unprepare(pl353_smc->aclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct amba_id pl353_ids[] = {
|
||||
{
|
||||
.id = 0x00041353,
|
||||
.mask = 0x000fffff,
|
||||
},
|
||||
{ 0, 0 },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(amba, pl353_ids);
|
||||
|
||||
static struct amba_driver pl353_smc_driver = {
|
||||
.drv = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "pl353-smc",
|
||||
.pm = &pl353_smc_dev_pm_ops,
|
||||
},
|
||||
.id_table = pl353_ids,
|
||||
.probe = pl353_smc_probe,
|
||||
.remove = pl353_smc_remove,
|
||||
};
|
||||
|
||||
module_amba_driver(pl353_smc_driver);
|
||||
|
||||
MODULE_AUTHOR("Xilinx, Inc.");
|
||||
MODULE_DESCRIPTION("ARM PL353 SMC Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -631,6 +631,9 @@ static struct optee *optee_probe(struct device_node *np)
|
|||
|
||||
optee_enable_shm_cache(optee);
|
||||
|
||||
if (optee->sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM)
|
||||
pr_info("dynamic shared memory is enabled\n");
|
||||
|
||||
pr_info("initialized driver\n");
|
||||
return optee;
|
||||
err:
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
struct optee_supp_req {
|
||||
struct list_head link;
|
||||
|
||||
bool busy;
|
||||
bool in_queue;
|
||||
u32 func;
|
||||
u32 ret;
|
||||
size_t num_params;
|
||||
|
|
@ -54,7 +54,6 @@ void optee_supp_release(struct optee_supp *supp)
|
|||
|
||||
/* Abort all request retrieved by supplicant */
|
||||
idr_for_each_entry(&supp->idr, req, id) {
|
||||
req->busy = false;
|
||||
idr_remove(&supp->idr, id);
|
||||
req->ret = TEEC_ERROR_COMMUNICATION;
|
||||
complete(&req->c);
|
||||
|
|
@ -63,6 +62,7 @@ void optee_supp_release(struct optee_supp *supp)
|
|||
/* Abort all queued requests */
|
||||
list_for_each_entry_safe(req, req_tmp, &supp->reqs, link) {
|
||||
list_del(&req->link);
|
||||
req->in_queue = false;
|
||||
req->ret = TEEC_ERROR_COMMUNICATION;
|
||||
complete(&req->c);
|
||||
}
|
||||
|
|
@ -103,6 +103,7 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params,
|
|||
/* Insert the request in the request list */
|
||||
mutex_lock(&supp->mutex);
|
||||
list_add_tail(&req->link, &supp->reqs);
|
||||
req->in_queue = true;
|
||||
mutex_unlock(&supp->mutex);
|
||||
|
||||
/* Tell an eventual waiter there's a new request */
|
||||
|
|
@ -130,9 +131,10 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params,
|
|||
* will serve all requests in a timely manner and
|
||||
* interrupting then wouldn't make sense.
|
||||
*/
|
||||
interruptable = !req->busy;
|
||||
if (!req->busy)
|
||||
if (req->in_queue) {
|
||||
list_del(&req->link);
|
||||
req->in_queue = false;
|
||||
}
|
||||
}
|
||||
mutex_unlock(&supp->mutex);
|
||||
|
||||
|
|
@ -176,7 +178,7 @@ static struct optee_supp_req *supp_pop_entry(struct optee_supp *supp,
|
|||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
list_del(&req->link);
|
||||
req->busy = true;
|
||||
req->in_queue = false;
|
||||
|
||||
return req;
|
||||
}
|
||||
|
|
@ -318,7 +320,6 @@ static struct optee_supp_req *supp_pop_req(struct optee_supp *supp,
|
|||
if ((num_params - nm) != req->num_params)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
req->busy = false;
|
||||
idr_remove(&supp->idr, id);
|
||||
supp->req_id = -1;
|
||||
*num_meta = nm;
|
||||
|
|
|
|||
|
|
@ -1529,6 +1529,25 @@ config SERIAL_OWL_CONSOLE
|
|||
Say 'Y' here if you wish to use Actions Semiconductor S500/S900 UART
|
||||
as the system console.
|
||||
|
||||
config SERIAL_RDA
|
||||
bool "RDA Micro serial port support"
|
||||
depends on ARCH_RDA || COMPILE_TEST
|
||||
select SERIAL_CORE
|
||||
help
|
||||
This driver is for RDA8810PL SoC's UART.
|
||||
Say 'Y' here if you wish to use the on-board serial port.
|
||||
Otherwise, say 'N'.
|
||||
|
||||
config SERIAL_RDA_CONSOLE
|
||||
bool "Console on RDA Micro serial port"
|
||||
depends on SERIAL_RDA=y
|
||||
select SERIAL_CORE_CONSOLE
|
||||
select SERIAL_EARLYCON
|
||||
default y
|
||||
help
|
||||
Say 'Y' here if you wish to use the RDA8810PL UART as the system
|
||||
console. Only earlycon is implemented currently.
|
||||
|
||||
endmenu
|
||||
|
||||
config SERIAL_MCTRL_GPIO
|
||||
|
|
|
|||
|
|
@ -89,6 +89,7 @@ obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o
|
|||
obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o
|
||||
obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
|
||||
obj-$(CONFIG_SERIAL_OWL) += owl-uart.o
|
||||
obj-$(CONFIG_SERIAL_RDA) += rda-uart.o
|
||||
|
||||
# GPIOLIB helpers for modem control lines
|
||||
obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,831 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* RDA8810PL serial device driver
|
||||
*
|
||||
* Copyright RDA Microelectronics Company Limited
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
* Copyright (c) 2018 Manivannan Sadhasivam
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/tty_flip.h>
|
||||
|
||||
#define RDA_UART_PORT_NUM 3
|
||||
#define RDA_UART_DEV_NAME "ttyRDA"
|
||||
|
||||
#define RDA_UART_CTRL 0x00
|
||||
#define RDA_UART_STATUS 0x04
|
||||
#define RDA_UART_RXTX_BUFFER 0x08
|
||||
#define RDA_UART_IRQ_MASK 0x0c
|
||||
#define RDA_UART_IRQ_CAUSE 0x10
|
||||
#define RDA_UART_IRQ_TRIGGERS 0x14
|
||||
#define RDA_UART_CMD_SET 0x18
|
||||
#define RDA_UART_CMD_CLR 0x1c
|
||||
|
||||
/* UART_CTRL Bits */
|
||||
#define RDA_UART_ENABLE BIT(0)
|
||||
#define RDA_UART_DBITS_8 BIT(1)
|
||||
#define RDA_UART_TX_SBITS_2 BIT(2)
|
||||
#define RDA_UART_PARITY_EN BIT(3)
|
||||
#define RDA_UART_PARITY(x) (((x) & 0x3) << 4)
|
||||
#define RDA_UART_PARITY_ODD RDA_UART_PARITY(0)
|
||||
#define RDA_UART_PARITY_EVEN RDA_UART_PARITY(1)
|
||||
#define RDA_UART_PARITY_SPACE RDA_UART_PARITY(2)
|
||||
#define RDA_UART_PARITY_MARK RDA_UART_PARITY(3)
|
||||
#define RDA_UART_DIV_MODE BIT(20)
|
||||
#define RDA_UART_IRDA_EN BIT(21)
|
||||
#define RDA_UART_DMA_EN BIT(22)
|
||||
#define RDA_UART_FLOW_CNT_EN BIT(23)
|
||||
#define RDA_UART_LOOP_BACK_EN BIT(24)
|
||||
#define RDA_UART_RX_LOCK_ERR BIT(25)
|
||||
#define RDA_UART_RX_BREAK_LEN(x) (((x) & 0xf) << 28)
|
||||
|
||||
/* UART_STATUS Bits */
|
||||
#define RDA_UART_RX_FIFO(x) (((x) & 0x7f) << 0)
|
||||
#define RDA_UART_RX_FIFO_MASK (0x7f << 0)
|
||||
#define RDA_UART_TX_FIFO(x) (((x) & 0x1f) << 8)
|
||||
#define RDA_UART_TX_FIFO_MASK (0x1f << 8)
|
||||
#define RDA_UART_TX_ACTIVE BIT(14)
|
||||
#define RDA_UART_RX_ACTIVE BIT(15)
|
||||
#define RDA_UART_RX_OVERFLOW_ERR BIT(16)
|
||||
#define RDA_UART_TX_OVERFLOW_ERR BIT(17)
|
||||
#define RDA_UART_RX_PARITY_ERR BIT(18)
|
||||
#define RDA_UART_RX_FRAMING_ERR BIT(19)
|
||||
#define RDA_UART_RX_BREAK_INT BIT(20)
|
||||
#define RDA_UART_DCTS BIT(24)
|
||||
#define RDA_UART_CTS BIT(25)
|
||||
#define RDA_UART_DTR BIT(28)
|
||||
#define RDA_UART_CLK_ENABLED BIT(31)
|
||||
|
||||
/* UART_RXTX_BUFFER Bits */
|
||||
#define RDA_UART_RX_DATA(x) (((x) & 0xff) << 0)
|
||||
#define RDA_UART_TX_DATA(x) (((x) & 0xff) << 0)
|
||||
|
||||
/* UART_IRQ_MASK Bits */
|
||||
#define RDA_UART_TX_MODEM_STATUS BIT(0)
|
||||
#define RDA_UART_RX_DATA_AVAILABLE BIT(1)
|
||||
#define RDA_UART_TX_DATA_NEEDED BIT(2)
|
||||
#define RDA_UART_RX_TIMEOUT BIT(3)
|
||||
#define RDA_UART_RX_LINE_ERR BIT(4)
|
||||
#define RDA_UART_TX_DMA_DONE BIT(5)
|
||||
#define RDA_UART_RX_DMA_DONE BIT(6)
|
||||
#define RDA_UART_RX_DMA_TIMEOUT BIT(7)
|
||||
#define RDA_UART_DTR_RISE BIT(8)
|
||||
#define RDA_UART_DTR_FALL BIT(9)
|
||||
|
||||
/* UART_IRQ_CAUSE Bits */
|
||||
#define RDA_UART_TX_MODEM_STATUS_U BIT(16)
|
||||
#define RDA_UART_RX_DATA_AVAILABLE_U BIT(17)
|
||||
#define RDA_UART_TX_DATA_NEEDED_U BIT(18)
|
||||
#define RDA_UART_RX_TIMEOUT_U BIT(19)
|
||||
#define RDA_UART_RX_LINE_ERR_U BIT(20)
|
||||
#define RDA_UART_TX_DMA_DONE_U BIT(21)
|
||||
#define RDA_UART_RX_DMA_DONE_U BIT(22)
|
||||
#define RDA_UART_RX_DMA_TIMEOUT_U BIT(23)
|
||||
#define RDA_UART_DTR_RISE_U BIT(24)
|
||||
#define RDA_UART_DTR_FALL_U BIT(25)
|
||||
|
||||
/* UART_TRIGGERS Bits */
|
||||
#define RDA_UART_RX_TRIGGER(x) (((x) & 0x1f) << 0)
|
||||
#define RDA_UART_TX_TRIGGER(x) (((x) & 0xf) << 8)
|
||||
#define RDA_UART_AFC_LEVEL(x) (((x) & 0x1f) << 16)
|
||||
|
||||
/* UART_CMD_SET Bits */
|
||||
#define RDA_UART_RI BIT(0)
|
||||
#define RDA_UART_DCD BIT(1)
|
||||
#define RDA_UART_DSR BIT(2)
|
||||
#define RDA_UART_TX_BREAK_CONTROL BIT(3)
|
||||
#define RDA_UART_TX_FINISH_N_WAIT BIT(4)
|
||||
#define RDA_UART_RTS BIT(5)
|
||||
#define RDA_UART_RX_FIFO_RESET BIT(6)
|
||||
#define RDA_UART_TX_FIFO_RESET BIT(7)
|
||||
|
||||
#define RDA_UART_TX_FIFO_SIZE 16
|
||||
|
||||
static struct uart_driver rda_uart_driver;
|
||||
|
||||
struct rda_uart_port {
|
||||
struct uart_port port;
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
#define to_rda_uart_port(port) container_of(port, struct rda_uart_port, port)
|
||||
|
||||
static struct rda_uart_port *rda_uart_ports[RDA_UART_PORT_NUM];
|
||||
|
||||
static inline void rda_uart_write(struct uart_port *port, u32 val,
|
||||
unsigned int off)
|
||||
{
|
||||
writel(val, port->membase + off);
|
||||
}
|
||||
|
||||
static inline u32 rda_uart_read(struct uart_port *port, unsigned int off)
|
||||
{
|
||||
return readl(port->membase + off);
|
||||
}
|
||||
|
||||
static unsigned int rda_uart_tx_empty(struct uart_port *port)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned int ret;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_STATUS);
|
||||
ret = (val & RDA_UART_TX_FIFO_MASK) ? TIOCSER_TEMT : 0;
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned int rda_uart_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
unsigned int mctrl = 0;
|
||||
u32 cmd_set, status;
|
||||
|
||||
cmd_set = rda_uart_read(port, RDA_UART_CMD_SET);
|
||||
status = rda_uart_read(port, RDA_UART_STATUS);
|
||||
if (cmd_set & RDA_UART_RTS)
|
||||
mctrl |= TIOCM_RTS;
|
||||
if (!(status & RDA_UART_CTS))
|
||||
mctrl |= TIOCM_CTS;
|
||||
|
||||
return mctrl;
|
||||
}
|
||||
|
||||
static void rda_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (mctrl & TIOCM_RTS) {
|
||||
val = rda_uart_read(port, RDA_UART_CMD_SET);
|
||||
rda_uart_write(port, (val | RDA_UART_RTS), RDA_UART_CMD_SET);
|
||||
} else {
|
||||
/* Clear RTS to stop to receive. */
|
||||
val = rda_uart_read(port, RDA_UART_CMD_CLR);
|
||||
rda_uart_write(port, (val | RDA_UART_RTS), RDA_UART_CMD_CLR);
|
||||
}
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_CTRL);
|
||||
|
||||
if (mctrl & TIOCM_LOOP)
|
||||
val |= RDA_UART_LOOP_BACK_EN;
|
||||
else
|
||||
val &= ~RDA_UART_LOOP_BACK_EN;
|
||||
|
||||
rda_uart_write(port, val, RDA_UART_CTRL);
|
||||
}
|
||||
|
||||
static void rda_uart_stop_tx(struct uart_port *port)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_IRQ_MASK);
|
||||
val &= ~RDA_UART_TX_DATA_NEEDED;
|
||||
rda_uart_write(port, val, RDA_UART_IRQ_MASK);
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_CMD_SET);
|
||||
val |= RDA_UART_TX_FIFO_RESET;
|
||||
rda_uart_write(port, val, RDA_UART_CMD_SET);
|
||||
}
|
||||
|
||||
static void rda_uart_stop_rx(struct uart_port *port)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_IRQ_MASK);
|
||||
val &= ~(RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT);
|
||||
rda_uart_write(port, val, RDA_UART_IRQ_MASK);
|
||||
|
||||
/* Read Rx buffer before reset to avoid Rx timeout interrupt */
|
||||
val = rda_uart_read(port, RDA_UART_RXTX_BUFFER);
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_CMD_SET);
|
||||
val |= RDA_UART_RX_FIFO_RESET;
|
||||
rda_uart_write(port, val, RDA_UART_CMD_SET);
|
||||
}
|
||||
|
||||
static void rda_uart_start_tx(struct uart_port *port)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (uart_tx_stopped(port)) {
|
||||
rda_uart_stop_tx(port);
|
||||
return;
|
||||
}
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_IRQ_MASK);
|
||||
val |= RDA_UART_TX_DATA_NEEDED;
|
||||
rda_uart_write(port, val, RDA_UART_IRQ_MASK);
|
||||
}
|
||||
|
||||
static void rda_uart_change_baudrate(struct rda_uart_port *rda_port,
|
||||
unsigned long baud)
|
||||
{
|
||||
clk_set_rate(rda_port->clk, baud * 8);
|
||||
}
|
||||
|
||||
static void rda_uart_set_termios(struct uart_port *port,
|
||||
struct ktermios *termios,
|
||||
struct ktermios *old)
|
||||
{
|
||||
struct rda_uart_port *rda_port = to_rda_uart_port(port);
|
||||
unsigned long flags;
|
||||
unsigned int ctrl, cmd_set, cmd_clr, triggers;
|
||||
unsigned int baud;
|
||||
u32 irq_mask;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
baud = uart_get_baud_rate(port, termios, old, 9600, port->uartclk / 4);
|
||||
rda_uart_change_baudrate(rda_port, baud);
|
||||
|
||||
ctrl = rda_uart_read(port, RDA_UART_CTRL);
|
||||
cmd_set = rda_uart_read(port, RDA_UART_CMD_SET);
|
||||
cmd_clr = rda_uart_read(port, RDA_UART_CMD_CLR);
|
||||
|
||||
switch (termios->c_cflag & CSIZE) {
|
||||
case CS5:
|
||||
case CS6:
|
||||
dev_warn(port->dev, "bit size not supported, using 7 bits\n");
|
||||
/* Fall through */
|
||||
case CS7:
|
||||
ctrl &= ~RDA_UART_DBITS_8;
|
||||
break;
|
||||
default:
|
||||
ctrl |= RDA_UART_DBITS_8;
|
||||
break;
|
||||
}
|
||||
|
||||
/* stop bits */
|
||||
if (termios->c_cflag & CSTOPB)
|
||||
ctrl |= RDA_UART_TX_SBITS_2;
|
||||
else
|
||||
ctrl &= ~RDA_UART_TX_SBITS_2;
|
||||
|
||||
/* parity check */
|
||||
if (termios->c_cflag & PARENB) {
|
||||
ctrl |= RDA_UART_PARITY_EN;
|
||||
|
||||
/* Mark or Space parity */
|
||||
if (termios->c_cflag & CMSPAR) {
|
||||
if (termios->c_cflag & PARODD)
|
||||
ctrl |= RDA_UART_PARITY_MARK;
|
||||
else
|
||||
ctrl |= RDA_UART_PARITY_SPACE;
|
||||
} else if (termios->c_cflag & PARODD) {
|
||||
ctrl |= RDA_UART_PARITY_ODD;
|
||||
} else {
|
||||
ctrl |= RDA_UART_PARITY_EVEN;
|
||||
}
|
||||
} else {
|
||||
ctrl &= ~RDA_UART_PARITY_EN;
|
||||
}
|
||||
|
||||
/* Hardware handshake (RTS/CTS) */
|
||||
if (termios->c_cflag & CRTSCTS) {
|
||||
ctrl |= RDA_UART_FLOW_CNT_EN;
|
||||
cmd_set |= RDA_UART_RTS;
|
||||
} else {
|
||||
ctrl &= ~RDA_UART_FLOW_CNT_EN;
|
||||
cmd_clr |= RDA_UART_RTS;
|
||||
}
|
||||
|
||||
ctrl |= RDA_UART_ENABLE;
|
||||
ctrl &= ~RDA_UART_DMA_EN;
|
||||
|
||||
triggers = (RDA_UART_AFC_LEVEL(20) | RDA_UART_RX_TRIGGER(16));
|
||||
irq_mask = rda_uart_read(port, RDA_UART_IRQ_MASK);
|
||||
rda_uart_write(port, 0, RDA_UART_IRQ_MASK);
|
||||
|
||||
rda_uart_write(port, triggers, RDA_UART_IRQ_TRIGGERS);
|
||||
rda_uart_write(port, ctrl, RDA_UART_CTRL);
|
||||
rda_uart_write(port, cmd_set, RDA_UART_CMD_SET);
|
||||
rda_uart_write(port, cmd_clr, RDA_UART_CMD_CLR);
|
||||
|
||||
rda_uart_write(port, irq_mask, RDA_UART_IRQ_MASK);
|
||||
|
||||
/* Don't rewrite B0 */
|
||||
if (tty_termios_baud_rate(termios))
|
||||
tty_termios_encode_baud_rate(termios, baud, baud);
|
||||
|
||||
/* update the per-port timeout */
|
||||
uart_update_timeout(port, termios->c_cflag, baud);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
static void rda_uart_send_chars(struct uart_port *port)
|
||||
{
|
||||
struct circ_buf *xmit = &port->state->xmit;
|
||||
unsigned int ch;
|
||||
u32 val;
|
||||
|
||||
if (uart_tx_stopped(port))
|
||||
return;
|
||||
|
||||
if (port->x_char) {
|
||||
while (!(rda_uart_read(port, RDA_UART_STATUS) &
|
||||
RDA_UART_TX_FIFO_MASK))
|
||||
cpu_relax();
|
||||
|
||||
rda_uart_write(port, port->x_char, RDA_UART_RXTX_BUFFER);
|
||||
port->icount.tx++;
|
||||
port->x_char = 0;
|
||||
}
|
||||
|
||||
while (rda_uart_read(port, RDA_UART_STATUS) & RDA_UART_TX_FIFO_MASK) {
|
||||
if (uart_circ_empty(xmit))
|
||||
break;
|
||||
|
||||
ch = xmit->buf[xmit->tail];
|
||||
rda_uart_write(port, ch, RDA_UART_RXTX_BUFFER);
|
||||
xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
|
||||
port->icount.tx++;
|
||||
}
|
||||
|
||||
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
||||
uart_write_wakeup(port);
|
||||
|
||||
if (!uart_circ_empty(xmit)) {
|
||||
/* Re-enable Tx FIFO interrupt */
|
||||
val = rda_uart_read(port, RDA_UART_IRQ_MASK);
|
||||
val |= RDA_UART_TX_DATA_NEEDED;
|
||||
rda_uart_write(port, val, RDA_UART_IRQ_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
static void rda_uart_receive_chars(struct uart_port *port)
|
||||
{
|
||||
u32 status, val;
|
||||
|
||||
status = rda_uart_read(port, RDA_UART_STATUS);
|
||||
while ((status & RDA_UART_RX_FIFO_MASK)) {
|
||||
char flag = TTY_NORMAL;
|
||||
|
||||
if (status & RDA_UART_RX_PARITY_ERR) {
|
||||
port->icount.parity++;
|
||||
flag = TTY_PARITY;
|
||||
}
|
||||
|
||||
if (status & RDA_UART_RX_FRAMING_ERR) {
|
||||
port->icount.frame++;
|
||||
flag = TTY_FRAME;
|
||||
}
|
||||
|
||||
if (status & RDA_UART_RX_OVERFLOW_ERR) {
|
||||
port->icount.overrun++;
|
||||
flag = TTY_OVERRUN;
|
||||
}
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_RXTX_BUFFER);
|
||||
val &= 0xff;
|
||||
|
||||
port->icount.rx++;
|
||||
tty_insert_flip_char(&port->state->port, val, flag);
|
||||
|
||||
status = rda_uart_read(port, RDA_UART_STATUS);
|
||||
}
|
||||
|
||||
spin_unlock(&port->lock);
|
||||
tty_flip_buffer_push(&port->state->port);
|
||||
spin_lock(&port->lock);
|
||||
}
|
||||
|
||||
static irqreturn_t rda_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct uart_port *port = dev_id;
|
||||
unsigned long flags;
|
||||
u32 val, irq_mask;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* Clear IRQ cause */
|
||||
val = rda_uart_read(port, RDA_UART_IRQ_CAUSE);
|
||||
rda_uart_write(port, val, RDA_UART_IRQ_CAUSE);
|
||||
|
||||
if (val & (RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT))
|
||||
rda_uart_receive_chars(port);
|
||||
|
||||
if (val & (RDA_UART_TX_DATA_NEEDED)) {
|
||||
irq_mask = rda_uart_read(port, RDA_UART_IRQ_MASK);
|
||||
irq_mask &= ~RDA_UART_TX_DATA_NEEDED;
|
||||
rda_uart_write(port, irq_mask, RDA_UART_IRQ_MASK);
|
||||
|
||||
rda_uart_send_chars(port);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int rda_uart_startup(struct uart_port *port)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
rda_uart_write(port, 0, RDA_UART_IRQ_MASK);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
ret = request_irq(port->irq, rda_interrupt, IRQF_NO_SUSPEND,
|
||||
"rda-uart", port);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_CTRL);
|
||||
val |= RDA_UART_ENABLE;
|
||||
rda_uart_write(port, val, RDA_UART_CTRL);
|
||||
|
||||
/* enable rx interrupt */
|
||||
val = rda_uart_read(port, RDA_UART_IRQ_MASK);
|
||||
val |= (RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT);
|
||||
rda_uart_write(port, val, RDA_UART_IRQ_MASK);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rda_uart_shutdown(struct uart_port *port)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
rda_uart_stop_tx(port);
|
||||
rda_uart_stop_rx(port);
|
||||
|
||||
val = rda_uart_read(port, RDA_UART_CTRL);
|
||||
val &= ~RDA_UART_ENABLE;
|
||||
rda_uart_write(port, val, RDA_UART_CTRL);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
static const char *rda_uart_type(struct uart_port *port)
|
||||
{
|
||||
return (port->type == PORT_RDA) ? "rda-uart" : NULL;
|
||||
}
|
||||
|
||||
static int rda_uart_request_port(struct uart_port *port)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(port->dev);
|
||||
struct resource *res;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENXIO;
|
||||
|
||||
if (!devm_request_mem_region(port->dev, port->mapbase,
|
||||
resource_size(res), dev_name(port->dev)))
|
||||
return -EBUSY;
|
||||
|
||||
if (port->flags & UPF_IOREMAP) {
|
||||
port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
|
||||
resource_size(res));
|
||||
if (!port->membase)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rda_uart_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
unsigned long irq_flags;
|
||||
|
||||
if (flags & UART_CONFIG_TYPE) {
|
||||
port->type = PORT_RDA;
|
||||
rda_uart_request_port(port);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&port->lock, irq_flags);
|
||||
|
||||
/* Clear mask, so no surprise interrupts. */
|
||||
rda_uart_write(port, 0, RDA_UART_IRQ_MASK);
|
||||
|
||||
/* Clear status register */
|
||||
rda_uart_write(port, 0, RDA_UART_STATUS);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, irq_flags);
|
||||
}
|
||||
|
||||
static void rda_uart_release_port(struct uart_port *port)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(port->dev);
|
||||
struct resource *res;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return;
|
||||
|
||||
if (port->flags & UPF_IOREMAP) {
|
||||
devm_release_mem_region(port->dev, port->mapbase,
|
||||
resource_size(res));
|
||||
devm_iounmap(port->dev, port->membase);
|
||||
port->membase = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static int rda_uart_verify_port(struct uart_port *port,
|
||||
struct serial_struct *ser)
|
||||
{
|
||||
if (port->type != PORT_RDA)
|
||||
return -EINVAL;
|
||||
|
||||
if (port->irq != ser->irq)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct uart_ops rda_uart_ops = {
|
||||
.tx_empty = rda_uart_tx_empty,
|
||||
.get_mctrl = rda_uart_get_mctrl,
|
||||
.set_mctrl = rda_uart_set_mctrl,
|
||||
.start_tx = rda_uart_start_tx,
|
||||
.stop_tx = rda_uart_stop_tx,
|
||||
.stop_rx = rda_uart_stop_rx,
|
||||
.startup = rda_uart_startup,
|
||||
.shutdown = rda_uart_shutdown,
|
||||
.set_termios = rda_uart_set_termios,
|
||||
.type = rda_uart_type,
|
||||
.request_port = rda_uart_request_port,
|
||||
.release_port = rda_uart_release_port,
|
||||
.config_port = rda_uart_config_port,
|
||||
.verify_port = rda_uart_verify_port,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SERIAL_RDA_CONSOLE
|
||||
|
||||
static void rda_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
if (!port->membase)
|
||||
return;
|
||||
|
||||
while (!(rda_uart_read(port, RDA_UART_STATUS) & RDA_UART_TX_FIFO_MASK))
|
||||
cpu_relax();
|
||||
|
||||
rda_uart_write(port, ch, RDA_UART_RXTX_BUFFER);
|
||||
}
|
||||
|
||||
static void rda_uart_port_write(struct uart_port *port, const char *s,
|
||||
u_int count)
|
||||
{
|
||||
u32 old_irq_mask;
|
||||
unsigned long flags;
|
||||
int locked;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
if (port->sysrq) {
|
||||
locked = 0;
|
||||
} else if (oops_in_progress) {
|
||||
locked = spin_trylock(&port->lock);
|
||||
} else {
|
||||
spin_lock(&port->lock);
|
||||
locked = 1;
|
||||
}
|
||||
|
||||
old_irq_mask = rda_uart_read(port, RDA_UART_IRQ_MASK);
|
||||
rda_uart_write(port, 0, RDA_UART_IRQ_MASK);
|
||||
|
||||
uart_console_write(port, s, count, rda_console_putchar);
|
||||
|
||||
/* wait until all contents have been sent out */
|
||||
while (!(rda_uart_read(port, RDA_UART_STATUS) & RDA_UART_TX_FIFO_MASK))
|
||||
cpu_relax();
|
||||
|
||||
rda_uart_write(port, old_irq_mask, RDA_UART_IRQ_MASK);
|
||||
|
||||
if (locked)
|
||||
spin_unlock(&port->lock);
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void rda_uart_console_write(struct console *co, const char *s,
|
||||
u_int count)
|
||||
{
|
||||
struct rda_uart_port *rda_port;
|
||||
|
||||
rda_port = rda_uart_ports[co->index];
|
||||
if (!rda_port)
|
||||
return;
|
||||
|
||||
rda_uart_port_write(&rda_port->port, s, count);
|
||||
}
|
||||
|
||||
static int rda_uart_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct rda_uart_port *rda_port;
|
||||
int baud = 921600;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
|
||||
if (co->index < 0 || co->index >= RDA_UART_PORT_NUM)
|
||||
return -EINVAL;
|
||||
|
||||
rda_port = rda_uart_ports[co->index];
|
||||
if (!rda_port || !rda_port->port.membase)
|
||||
return -ENODEV;
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
||||
return uart_set_options(&rda_port->port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct console rda_uart_console = {
|
||||
.name = RDA_UART_DEV_NAME,
|
||||
.write = rda_uart_console_write,
|
||||
.device = uart_console_device,
|
||||
.setup = rda_uart_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &rda_uart_driver,
|
||||
};
|
||||
|
||||
static int __init rda_uart_console_init(void)
|
||||
{
|
||||
register_console(&rda_uart_console);
|
||||
|
||||
return 0;
|
||||
}
|
||||
console_initcall(rda_uart_console_init);
|
||||
|
||||
static void rda_uart_early_console_write(struct console *co,
|
||||
const char *s,
|
||||
u_int count)
|
||||
{
|
||||
struct earlycon_device *dev = co->data;
|
||||
|
||||
rda_uart_port_write(&dev->port, s, count);
|
||||
}
|
||||
|
||||
static int __init
|
||||
rda_uart_early_console_setup(struct earlycon_device *device, const char *opt)
|
||||
{
|
||||
if (!device->port.membase)
|
||||
return -ENODEV;
|
||||
|
||||
device->con->write = rda_uart_early_console_write;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
OF_EARLYCON_DECLARE(rda, "rda,8810pl-uart",
|
||||
rda_uart_early_console_setup);
|
||||
|
||||
#define RDA_UART_CONSOLE (&rda_uart_console)
|
||||
#else
|
||||
#define RDA_UART_CONSOLE NULL
|
||||
#endif /* CONFIG_SERIAL_RDA_CONSOLE */
|
||||
|
||||
static struct uart_driver rda_uart_driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = "rda-uart",
|
||||
.dev_name = RDA_UART_DEV_NAME,
|
||||
.nr = RDA_UART_PORT_NUM,
|
||||
.cons = RDA_UART_CONSOLE,
|
||||
};
|
||||
|
||||
static const struct of_device_id rda_uart_dt_matches[] = {
|
||||
{ .compatible = "rda,8810pl-uart" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rda_uart_dt_matches);
|
||||
|
||||
static int rda_uart_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res_mem;
|
||||
struct rda_uart_port *rda_port;
|
||||
int ret, irq;
|
||||
|
||||
if (pdev->dev.of_node)
|
||||
pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
|
||||
|
||||
if (pdev->id < 0 || pdev->id >= RDA_UART_PORT_NUM) {
|
||||
dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res_mem) {
|
||||
dev_err(&pdev->dev, "could not get mem\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "could not get irq\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
if (rda_uart_ports[pdev->id]) {
|
||||
dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
rda_port = devm_kzalloc(&pdev->dev, sizeof(*rda_port), GFP_KERNEL);
|
||||
if (!rda_port)
|
||||
return -ENOMEM;
|
||||
|
||||
rda_port->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(rda_port->clk)) {
|
||||
dev_err(&pdev->dev, "could not get clk\n");
|
||||
return PTR_ERR(rda_port->clk);
|
||||
}
|
||||
|
||||
rda_port->port.dev = &pdev->dev;
|
||||
rda_port->port.regshift = 0;
|
||||
rda_port->port.line = pdev->id;
|
||||
rda_port->port.type = PORT_RDA;
|
||||
rda_port->port.iotype = UPIO_MEM;
|
||||
rda_port->port.mapbase = res_mem->start;
|
||||
rda_port->port.irq = irq;
|
||||
rda_port->port.uartclk = clk_get_rate(rda_port->clk);
|
||||
if (rda_port->port.uartclk == 0) {
|
||||
dev_err(&pdev->dev, "clock rate is zero\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
rda_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP |
|
||||
UPF_LOW_LATENCY;
|
||||
rda_port->port.x_char = 0;
|
||||
rda_port->port.fifosize = RDA_UART_TX_FIFO_SIZE;
|
||||
rda_port->port.ops = &rda_uart_ops;
|
||||
|
||||
rda_uart_ports[pdev->id] = rda_port;
|
||||
platform_set_drvdata(pdev, rda_port);
|
||||
|
||||
ret = uart_add_one_port(&rda_uart_driver, &rda_port->port);
|
||||
if (ret)
|
||||
rda_uart_ports[pdev->id] = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rda_uart_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rda_uart_port *rda_port = platform_get_drvdata(pdev);
|
||||
|
||||
uart_remove_one_port(&rda_uart_driver, &rda_port->port);
|
||||
rda_uart_ports[pdev->id] = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rda_uart_platform_driver = {
|
||||
.probe = rda_uart_probe,
|
||||
.remove = rda_uart_remove,
|
||||
.driver = {
|
||||
.name = "rda-uart",
|
||||
.of_match_table = rda_uart_dt_matches,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rda_uart_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = uart_register_driver(&rda_uart_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_register(&rda_uart_platform_driver);
|
||||
if (ret)
|
||||
uart_unregister_driver(&rda_uart_driver);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __init rda_uart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&rda_uart_platform_driver);
|
||||
uart_unregister_driver(&rda_uart_driver);
|
||||
}
|
||||
|
||||
module_init(rda_uart_init);
|
||||
module_exit(rda_uart_exit);
|
||||
|
||||
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
|
||||
MODULE_DESCRIPTION("RDA8810PL serial device driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* ARM PL353 SMC Driver Header
|
||||
*
|
||||
* Copyright (C) 2012 - 2018 Xilinx, Inc
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_PL353_SMC_H
|
||||
#define __LINUX_PL353_SMC_H
|
||||
|
||||
enum pl353_smc_ecc_mode {
|
||||
PL353_SMC_ECCMODE_BYPASS = 0,
|
||||
PL353_SMC_ECCMODE_APB = 1,
|
||||
PL353_SMC_ECCMODE_MEM = 2
|
||||
};
|
||||
|
||||
enum pl353_smc_mem_width {
|
||||
PL353_SMC_MEM_WIDTH_8 = 0,
|
||||
PL353_SMC_MEM_WIDTH_16 = 1
|
||||
};
|
||||
|
||||
u32 pl353_smc_get_ecc_val(int ecc_reg);
|
||||
bool pl353_smc_ecc_is_busy(void);
|
||||
int pl353_smc_get_nand_int_status_raw(void);
|
||||
void pl353_smc_clr_nand_int(void);
|
||||
int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode);
|
||||
int pl353_smc_set_ecc_pg_size(unsigned int pg_sz);
|
||||
int pl353_smc_set_buswidth(unsigned int bw);
|
||||
void pl353_smc_set_cycles(u32 timings[]);
|
||||
#endif
|
||||
|
|
@ -67,6 +67,9 @@ extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
|
|||
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
|
||||
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
|
||||
#else
|
||||
|
||||
#include <linux/errno.h>
|
||||
|
||||
static inline
|
||||
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -281,4 +281,7 @@
|
|||
/* MediaTek BTIF */
|
||||
#define PORT_MTK_BTIF 117
|
||||
|
||||
/* RDA UART */
|
||||
#define PORT_RDA 118
|
||||
|
||||
#endif /* _UAPILINUX_SERIAL_CORE_H */
|
||||
|
|
|
|||
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