[TG3]: Add PHY workaround for 5784
The 5784 B step and newer chips require the PHY DSPs to be fine-tuned based on one-time programmable values stored in the chip. This is essential to achieve optimal PHY operations especially when using long cables. We also need to properly handle the 10Mbit RX bit in the CPMU_CTRL register during PHY reset. Update version to 3.89. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
Родитель
61407f80f7
Коммит
b2a5c19ca0
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@ -64,8 +64,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.88"
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#define DRV_MODULE_RELDATE "March 20, 2008"
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#define DRV_MODULE_VERSION "3.89"
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#define DRV_MODULE_RELDATE "April 03, 2008"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -804,6 +804,12 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
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return ret;
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}
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static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
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{
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
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}
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static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
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{
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u32 phy;
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@ -886,6 +892,49 @@ static int tg3_bmcr_reset(struct tg3 *tp)
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return 0;
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}
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static void tg3_phy_apply_otp(struct tg3 *tp)
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{
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u32 otp, phy;
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if (!tp->phy_otp)
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return;
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otp = tp->phy_otp;
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/* Enable SM_DSP clock and tx 6dB coding. */
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phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
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MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
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MII_TG3_AUXCTL_ACTL_TX_6DB;
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tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
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phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
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phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
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tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
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phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
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((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
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tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
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phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
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phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
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tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
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phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
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tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
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phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
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tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
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phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
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((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
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tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
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/* Turn off SM_DSP clock. */
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phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
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MII_TG3_AUXCTL_ACTL_TX_6DB;
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tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
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}
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static int tg3_wait_macro_done(struct tg3 *tp)
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{
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int limit = 100;
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@ -1073,6 +1122,7 @@ static void tg3_link_report(struct tg3 *);
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*/
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static int tg3_phy_reset(struct tg3 *tp)
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{
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u32 cpmuctrl;
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u32 phy_status;
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int err;
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@ -1102,10 +1152,28 @@ static int tg3_phy_reset(struct tg3 *tp)
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goto out;
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}
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cpmuctrl = 0;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
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GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
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cpmuctrl = tr32(TG3_CPMU_CTRL);
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if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
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tw32(TG3_CPMU_CTRL,
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cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
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}
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err = tg3_bmcr_reset(tp);
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if (err)
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return err;
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if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
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u32 phy;
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phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
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tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
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tw32(TG3_CPMU_CTRL, cpmuctrl);
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}
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if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
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u32 val;
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@ -1124,6 +1192,8 @@ static int tg3_phy_reset(struct tg3 *tp)
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MII_TG3_MISC_SHDW_APD_WKTM_84MS);
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}
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tg3_phy_apply_otp(tp);
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out:
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if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
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@ -9464,7 +9534,8 @@ static int tg3_test_loopback(struct tg3 *tp)
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if (err)
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return TG3_LOOPBACK_FAILED;
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if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
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int i;
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u32 status;
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@ -9481,17 +9552,23 @@ static int tg3_test_loopback(struct tg3 *tp)
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if (status != CPMU_MUTEX_GNT_DRIVER)
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return TG3_LOOPBACK_FAILED;
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/* Turn off power management based on link speed. */
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/* Turn off link-based power management. */
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cpmuctrl = tr32(TG3_CPMU_CTRL);
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tw32(TG3_CPMU_CTRL,
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cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
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CPMU_CTRL_LINK_AWARE_MODE));
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX)
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tw32(TG3_CPMU_CTRL,
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cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
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CPMU_CTRL_LINK_AWARE_MODE));
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else
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tw32(TG3_CPMU_CTRL,
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cpmuctrl & ~CPMU_CTRL_LINK_AWARE_MODE);
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}
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if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
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err |= TG3_MAC_LOOPBACK_FAILED;
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if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
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tw32(TG3_CPMU_CTRL, cpmuctrl);
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/* Release the mutex */
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@ -10724,9 +10801,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
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tp->led_ctrl = LED_CTRL_MODE_PHY_2;
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if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
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tp->pci_chip_rev_id == CHIPREV_ID_5784_A1)
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tp->led_ctrl = LED_CTRL_MODE_MAC;
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
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tp->led_ctrl = LED_CTRL_MODE_PHY_1;
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if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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@ -10773,6 +10849,55 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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}
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}
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static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
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{
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int i;
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u32 val;
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tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
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tw32(OTP_CTRL, cmd);
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/* Wait for up to 1 ms for command to execute. */
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for (i = 0; i < 100; i++) {
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val = tr32(OTP_STATUS);
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if (val & OTP_STATUS_CMD_DONE)
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break;
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udelay(10);
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}
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return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
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}
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/* Read the gphy configuration from the OTP region of the chip. The gphy
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* configuration is a 32-bit value that straddles the alignment boundary.
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* We do two 32-bit reads and then shift and merge the results.
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*/
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static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
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{
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u32 bhalf_otp, thalf_otp;
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tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
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if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
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return 0;
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tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
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if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
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return 0;
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thalf_otp = tr32(OTP_READ_DATA);
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tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
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if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
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return 0;
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bhalf_otp = tr32(OTP_READ_DATA);
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return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
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}
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static int __devinit tg3_phy_probe(struct tg3 *tp)
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{
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u32 hw_phy_id_1, hw_phy_id_2;
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@ -11586,6 +11711,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
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GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
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tp->phy_otp = tg3_read_otp_phycfg(tp);
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if (tp->phy_otp == 0)
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tp->phy_otp = TG3_OTP_DEFAULT;
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}
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tp->coalesce_mode = 0;
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if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
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GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
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@ -138,6 +138,8 @@
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#define CHIPREV_5704_BX 0x21
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#define CHIPREV_5750_AX 0x40
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#define CHIPREV_5750_BX 0x41
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#define CHIPREV_5784_AX 0x57840
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#define CHIPREV_5761_AX 0x57610
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#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
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#define METAL_REV_A0 0x00
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#define METAL_REV_A1 0x01
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@ -866,6 +868,7 @@
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#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
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#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
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#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
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#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
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#define TG3_CPMU_LSPD_10MB_CLK 0x00003604
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#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
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#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
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@ -1559,7 +1562,24 @@
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/* 0x702c unused */
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#define NVRAM_ADDR_LOCKOUT 0x00007030
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/* 0x7034 --> 0x7c00 unused */
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/* 0x7034 --> 0x7500 unused */
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#define OTP_MODE 0x00007500
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#define OTP_MODE_OTP_THRU_GRC 0x00000001
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#define OTP_CTRL 0x00007504
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#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
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#define OTP_CTRL_OTP_CMD_READ 0x00000000
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#define OTP_CTRL_OTP_CMD_INIT 0x00000008
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#define OTP_CTRL_OTP_CMD_START 0x00000001
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#define OTP_STATUS 0x00007508
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#define OTP_STATUS_CMD_DONE 0x00000001
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#define OTP_ADDRESS 0x0000750c
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#define OTP_ADDRESS_MAGIC1 0x000000a0
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#define OTP_ADDRESS_MAGIC2 0x00000080
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/* 0x7510 unused */
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#define OTP_READ_DATA 0x00007514
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/* 0x7518 --> 0x7c04 unused */
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#define PCIE_TRANSACTION_CFG 0x00007c04
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#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
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@ -1568,6 +1588,28 @@
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#define PCIE_PWR_MGMT_THRESH 0x00007d28
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#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
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/* OTP bit definitions */
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#define TG3_OTP_AGCTGT_MASK 0x000000e0
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#define TG3_OTP_AGCTGT_SHIFT 1
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#define TG3_OTP_HPFFLTR_MASK 0x00000300
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#define TG3_OTP_HPFFLTR_SHIFT 1
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#define TG3_OTP_HPFOVER_MASK 0x00000400
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#define TG3_OTP_HPFOVER_SHIFT 1
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#define TG3_OTP_LPFDIS_MASK 0x00000800
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#define TG3_OTP_LPFDIS_SHIFT 11
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#define TG3_OTP_VDAC_MASK 0xff000000
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#define TG3_OTP_VDAC_SHIFT 24
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#define TG3_OTP_10BTAMP_MASK 0x0000f000
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#define TG3_OTP_10BTAMP_SHIFT 8
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#define TG3_OTP_ROFF_MASK 0x00e00000
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#define TG3_OTP_ROFF_SHIFT 11
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#define TG3_OTP_RCOFF_MASK 0x001c0000
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#define TG3_OTP_RCOFF_SHIFT 16
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#define TG3_OTP_DEFAULT 0x286c1640
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#define TG3_EEPROM_MAGIC 0x669955aa
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#define TG3_EEPROM_MAGIC_FW 0xa5000000
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#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
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@ -1705,15 +1747,31 @@
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#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
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#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
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#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */
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#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
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#define MII_TG3_DSP_TAP1 0x0001
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#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
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#define MII_TG3_DSP_AADJ1CH0 0x001f
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#define MII_TG3_DSP_AADJ1CH3 0x601f
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#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
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#define MII_TG3_DSP_EXP8 0x0708
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#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
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#define MII_TG3_DSP_EXP8_AEDW 0x0200
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#define MII_TG3_DSP_EXP75 0x0f75
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#define MII_TG3_DSP_EXP96 0x0f96
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#define MII_TG3_DSP_EXP97 0x0f97
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#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
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#define MII_TG3_AUXCTL_MISC_WREN 0x8000
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#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
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#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
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#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
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#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
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#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
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#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
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#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
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#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
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#define MII_TG3_AUX_STAT_LPASS 0x0004
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@ -1743,6 +1801,20 @@
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#define MII_TG3_INT_DUPLEXCHG 0x0008
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#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
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#define MII_TG3_MISC_SHDW 0x1c
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#define MII_TG3_MISC_SHDW_WREN 0x8000
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#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
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#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
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#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
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#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
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#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
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#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
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#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
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#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
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#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
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||||
#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
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#define MII_TG3_EPHY_SHADOW_EN 0x80
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@ -2473,6 +2545,7 @@ struct tg3 {
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#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
|
||||
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||||
u32 led_ctrl;
|
||||
u32 phy_otp;
|
||||
u16 pci_cmd;
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char board_part_number[24];
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||||
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