cxgb4: Add register definations for T5
Signed-off-by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Santosh Rastapur
David S. Miller
Родитель
f7de0b9368
Коммит
b2decadd83
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@ -68,9 +68,14 @@
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#define QID_SHIFT 15
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#define QID(x) ((x) << QID_SHIFT)
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#define DBPRIO(x) ((x) << 14)
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#define DBTYPE(x) ((x) << 13)
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#define PIDX_MASK 0x00003fffU
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#define PIDX_SHIFT 0
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#define PIDX(x) ((x) << PIDX_SHIFT)
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#define S_PIDX_T5 0
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#define M_PIDX_T5 0x1fffU
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#define PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
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#define SGE_PF_GTS 0x4
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#define INGRESSQID_MASK 0xffff0000U
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@ -152,6 +157,8 @@
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#define QUEUESPERPAGEPF0_MASK 0x0000000fU
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#define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
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#define QUEUESPERPAGEPF1 4
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#define SGE_INT_CAUSE1 0x1024
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#define SGE_INT_CAUSE2 0x1030
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#define SGE_INT_CAUSE3 0x103c
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@ -272,17 +279,36 @@
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#define S_HP_INT_THRESH 28
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#define M_HP_INT_THRESH 0xfU
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#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
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#define S_LP_INT_THRESH_T5 18
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#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
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#define M_LP_COUNT_T5 0x3ffffU
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#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
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#define M_HP_COUNT 0x7ffU
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#define S_HP_COUNT 16
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#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
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#define S_LP_INT_THRESH 12
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#define M_LP_INT_THRESH 0xfU
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#define M_LP_INT_THRESH_T5 0xfffU
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#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
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#define M_LP_COUNT 0x7ffU
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#define S_LP_COUNT 0
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#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
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#define A_SGE_DBFIFO_STATUS 0x10a4
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#define SGE_STAT_TOTAL 0x10e4
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#define SGE_STAT_MATCH 0x10e8
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#define SGE_STAT_CFG 0x10ec
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#define S_STATSOURCE_T5 9
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#define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
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#define SGE_DBFIFO_STATUS2 0x1118
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#define M_HP_COUNT_T5 0x3ffU
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#define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5)
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#define S_HP_INT_THRESH_T5 10
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#define M_HP_INT_THRESH_T5 0xfU
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#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
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#define S_ENABLE_DROP 13
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#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
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#define F_ENABLE_DROP V_ENABLE_DROP(1U)
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@ -331,8 +357,27 @@
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#define MSIADDRHPERR 0x00000002U
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#define MSIADDRLPERR 0x00000001U
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#define READRSPERR 0x20000000U
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#define TRGT1GRPPERR 0x10000000U
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#define IPSOTPERR 0x08000000U
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#define IPRXDATAGRPPERR 0x02000000U
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#define IPRXHDRGRPPERR 0x01000000U
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#define MAGRPPERR 0x00400000U
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#define VFIDPERR 0x00200000U
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#define HREQWRPERR 0x00010000U
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#define DREQWRPERR 0x00002000U
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#define MSTTAGQPERR 0x00000400U
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#define PIOREQGRPPERR 0x00000100U
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#define PIOCPLGRPPERR 0x00000080U
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#define MSIXSTIPERR 0x00000004U
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#define MSTTIMEOUTPERR 0x00000002U
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#define MSTGRPPERR 0x00000001U
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#define PCIE_NONFAT_ERR 0x3010
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#define PCIE_MEM_ACCESS_BASE_WIN 0x3068
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#define S_PCIEOFST 10
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#define M_PCIEOFST 0x3fffffU
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#define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
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#define PCIEOFST_MASK 0xfffffc00U
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#define BIR_MASK 0x00000300U
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#define BIR_SHIFT 8
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@ -342,6 +387,9 @@
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#define WINDOW(x) ((x) << WINDOW_SHIFT)
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#define PCIE_MEM_ACCESS_OFFSET 0x306c
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#define S_PFNUM 0
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#define V_PFNUM(x) ((x) << S_PFNUM)
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#define PCIE_FW 0x30b8
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#define PCIE_FW_ERR 0x80000000U
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#define PCIE_FW_INIT 0x40000000U
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@ -407,12 +455,18 @@
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#define MC_BIST_STATUS_RDATA 0x7688
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#define MA_EDRAM0_BAR 0x77c0
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#define MA_EDRAM1_BAR 0x77c4
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#define EDRAM_SIZE_MASK 0xfffU
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#define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK)
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#define MA_EXT_MEMORY_BAR 0x77c8
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#define EXT_MEM_SIZE_MASK 0x00000fffU
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#define EXT_MEM_SIZE_SHIFT 0
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#define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT)
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#define MA_TARGET_MEM_ENABLE 0x77d8
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#define EXT_MEM1_ENABLE 0x00000010U
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#define EXT_MEM_ENABLE 0x00000004U
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#define EDRAM1_ENABLE 0x00000002U
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#define EDRAM0_ENABLE 0x00000001U
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@ -431,6 +485,7 @@
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#define MA_PCIE_FW 0x30b8
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#define MA_PARITY_ERROR_STATUS 0x77f4
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#define MA_EXT_MEMORY1_BAR 0x7808
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#define EDC_0_BASE_ADDR 0x7900
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#define EDC_BIST_CMD 0x7904
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@ -801,6 +856,15 @@
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#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
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#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
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#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
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#define MAC_PORT_CFG2 0x818
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#define MAC_PORT_MAGIC_MACID_LO 0x824
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#define MAC_PORT_MAGIC_MACID_HI 0x828
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#define MAC_PORT_EPIO_DATA0 0x8c0
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#define MAC_PORT_EPIO_DATA1 0x8c4
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#define MAC_PORT_EPIO_DATA2 0x8c8
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#define MAC_PORT_EPIO_DATA3 0x8cc
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#define MAC_PORT_EPIO_OP 0x8d0
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#define MPS_CMN_CTL 0x9000
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#define NUMPORTS_MASK 0x00000003U
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#define NUMPORTS_SHIFT 0
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@ -1063,6 +1127,7 @@
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#define ADDRESS_SHIFT 0
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#define ADDRESS(x) ((x) << ADDRESS_SHIFT)
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#define MAC_PORT_INT_CAUSE 0x8dc
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#define XGMAC_PORT_INT_CAUSE 0x10dc
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#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
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@ -1101,4 +1166,33 @@
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#define V_PORT(x) ((x) << S_PORT)
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#define F_PORT V_PORT(1U)
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#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
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#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
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#define T5_PORT0_BASE 0x30000
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#define T5_PORT_STRIDE 0x4000
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#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
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#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
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#define MC_0_BASE_ADDR 0x40000
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#define MC_1_BASE_ADDR 0x48000
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#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
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#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
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#define MC_P_BIST_CMD 0x41400
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#define MC_P_BIST_CMD_ADDR 0x41404
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#define MC_P_BIST_CMD_LEN 0x41408
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#define MC_P_BIST_DATA_PATTERN 0x4140c
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#define MC_P_BIST_STATUS_RDATA 0x41488
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#define EDC_T50_BASE_ADDR 0x50000
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#define EDC_H_BIST_CMD 0x50004
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#define EDC_H_BIST_CMD_ADDR 0x50008
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#define EDC_H_BIST_CMD_LEN 0x5000c
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#define EDC_H_BIST_DATA_PATTERN 0x50010
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#define EDC_H_BIST_STATUS_RDATA 0x50028
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#define EDC_T51_BASE_ADDR 0x50800
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#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
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#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
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#endif /* __T4_REGS_H */
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