x86/amd_nb, EDAC/amd64: Move DF Indirect Read to AMD64 EDAC
df_indirect_read() is used only for address translation. Move it to EDAC along with the translation code. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211028175728.121452-3-yazen.ghannam@amd.com
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b3218ae477
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@ -24,7 +24,6 @@ extern int amd_set_subcaches(int, unsigned long);
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extern int amd_smn_read(u16 node, u32 address, u32 *value);
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extern int amd_smn_read(u16 node, u32 address, u32 *value);
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extern int amd_smn_write(u16 node, u32 address, u32 value);
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extern int amd_smn_write(u16 node, u32 address, u32 value);
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extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo);
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struct amd_l3_cache {
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struct amd_l3_cache {
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unsigned indices;
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unsigned indices;
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@ -29,7 +29,7 @@
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#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
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#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
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#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
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#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
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/* Protect the PCI config register pairs used for SMN and DF indirect access. */
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/* Protect the PCI config register pairs used for SMN. */
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static DEFINE_MUTEX(smn_mutex);
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static DEFINE_MUTEX(smn_mutex);
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static u32 *flush_words;
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static u32 *flush_words;
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@ -182,53 +182,6 @@ int amd_smn_write(u16 node, u32 address, u32 value)
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}
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}
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EXPORT_SYMBOL_GPL(amd_smn_write);
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EXPORT_SYMBOL_GPL(amd_smn_write);
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/*
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* Data Fabric Indirect Access uses FICAA/FICAD.
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*
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* Fabric Indirect Configuration Access Address (FICAA): Constructed based
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* on the device's Instance Id and the PCI function and register offset of
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* the desired register.
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*
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* Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
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* and FICAD HI registers but so far we only need the LO register.
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*/
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int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
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{
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struct pci_dev *F4;
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u32 ficaa;
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int err = -ENODEV;
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if (node >= amd_northbridges.num)
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goto out;
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F4 = node_to_amd_nb(node)->link;
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if (!F4)
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goto out;
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ficaa = 1;
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ficaa |= reg & 0x3FC;
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ficaa |= (func & 0x7) << 11;
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ficaa |= instance_id << 16;
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mutex_lock(&smn_mutex);
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err = pci_write_config_dword(F4, 0x5C, ficaa);
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if (err) {
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pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
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goto out_unlock;
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}
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err = pci_read_config_dword(F4, 0x98, lo);
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if (err)
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pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
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out_unlock:
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mutex_unlock(&smn_mutex);
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out:
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return err;
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}
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EXPORT_SYMBOL_GPL(amd_df_indirect_read);
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int amd_cache_northbridges(void)
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int amd_cache_northbridges(void)
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{
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{
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@ -988,6 +988,56 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
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return csrow;
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return csrow;
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}
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}
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/* Protect the PCI config register pairs used for DF indirect access. */
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static DEFINE_MUTEX(df_indirect_mutex);
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/*
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* Data Fabric Indirect Access uses FICAA/FICAD.
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*
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* Fabric Indirect Configuration Access Address (FICAA): Constructed based
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* on the device's Instance Id and the PCI function and register offset of
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* the desired register.
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*
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* Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
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* and FICAD HI registers but so far we only need the LO register.
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*/
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static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
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{
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struct pci_dev *F4;
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u32 ficaa;
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int err = -ENODEV;
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if (node >= amd_nb_num())
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goto out;
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F4 = node_to_amd_nb(node)->link;
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if (!F4)
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goto out;
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ficaa = 1;
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ficaa |= reg & 0x3FC;
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ficaa |= (func & 0x7) << 11;
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ficaa |= instance_id << 16;
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mutex_lock(&df_indirect_mutex);
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err = pci_write_config_dword(F4, 0x5C, ficaa);
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if (err) {
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pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
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goto out_unlock;
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}
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err = pci_read_config_dword(F4, 0x98, lo);
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if (err)
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pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
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out_unlock:
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mutex_unlock(&df_indirect_mutex);
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out:
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return err;
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}
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static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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{
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{
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u64 dram_base_addr, dram_limit_addr, dram_hole_base;
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u64 dram_base_addr, dram_limit_addr, dram_hole_base;
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