i40e: Drop packet split receive routine
As part of preparation for the rx-refactor, remove the packet split receive routine and ancillary code. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Родитель
f8a952cb40
Коммит
b32bfa1724
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@ -101,7 +101,6 @@
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#define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1)
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#define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1)
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#define I40E_PRIV_FLAGS_FD_ATR BIT(2)
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#define I40E_PRIV_FLAGS_FD_ATR BIT(2)
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#define I40E_PRIV_FLAGS_VEB_STATS BIT(3)
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#define I40E_PRIV_FLAGS_VEB_STATS BIT(3)
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#define I40E_PRIV_FLAGS_PS BIT(4)
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#define I40E_PRIV_FLAGS_HW_ATR_EVICT BIT(5)
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#define I40E_PRIV_FLAGS_HW_ATR_EVICT BIT(5)
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#define I40E_NVM_VERSION_LO_SHIFT 0
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#define I40E_NVM_VERSION_LO_SHIFT 0
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@ -320,8 +319,6 @@ struct i40e_pf {
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#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
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#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
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#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
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#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
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#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
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#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
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#define I40E_FLAG_RX_1BUF_ENABLED BIT_ULL(4)
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#define I40E_FLAG_RX_PS_ENABLED BIT_ULL(5)
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#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
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#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
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#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
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#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
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#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
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#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
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@ -273,8 +273,8 @@ static void i40e_dbg_dump_vsi_seid(struct i40e_pf *pf, int seid)
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rx_ring->rx_buf_len,
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rx_ring->rx_buf_len,
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rx_ring->dtype);
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rx_ring->dtype);
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dev_info(&pf->pdev->dev,
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dev_info(&pf->pdev->dev,
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" rx_rings[%i]: hsplit = %d, next_to_use = %d, next_to_clean = %d, ring_active = %i\n",
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" rx_rings[%i]: next_to_use = %d, next_to_clean = %d, ring_active = %i\n",
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i, ring_is_ps_enabled(rx_ring),
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i,
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rx_ring->next_to_use,
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rx_ring->next_to_use,
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rx_ring->next_to_clean,
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rx_ring->next_to_clean,
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rx_ring->ring_active);
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rx_ring->ring_active);
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@ -2829,8 +2829,6 @@ static u32 i40e_get_priv_flags(struct net_device *dev)
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I40E_PRIV_FLAGS_FD_ATR : 0;
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I40E_PRIV_FLAGS_FD_ATR : 0;
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ret_flags |= pf->flags & I40E_FLAG_VEB_STATS_ENABLED ?
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ret_flags |= pf->flags & I40E_FLAG_VEB_STATS_ENABLED ?
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I40E_PRIV_FLAGS_VEB_STATS : 0;
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I40E_PRIV_FLAGS_VEB_STATS : 0;
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ret_flags |= pf->flags & I40E_FLAG_RX_PS_ENABLED ?
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I40E_PRIV_FLAGS_PS : 0;
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ret_flags |= pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE ?
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ret_flags |= pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE ?
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0 : I40E_PRIV_FLAGS_HW_ATR_EVICT;
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0 : I40E_PRIV_FLAGS_HW_ATR_EVICT;
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@ -2851,23 +2849,6 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
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/* NOTE: MFP is not settable */
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/* NOTE: MFP is not settable */
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/* allow the user to control the method of receive
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* buffer DMA, whether the packet is split at header
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* boundaries into two separate buffers. In some cases
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* one routine or the other will perform better.
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*/
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if ((flags & I40E_PRIV_FLAGS_PS) &&
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!(pf->flags & I40E_FLAG_RX_PS_ENABLED)) {
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pf->flags |= I40E_FLAG_RX_PS_ENABLED;
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pf->flags &= ~I40E_FLAG_RX_1BUF_ENABLED;
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reset_required = true;
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} else if (!(flags & I40E_PRIV_FLAGS_PS) &&
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(pf->flags & I40E_FLAG_RX_PS_ENABLED)) {
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pf->flags &= ~I40E_FLAG_RX_PS_ENABLED;
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pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
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reset_required = true;
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}
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if (flags & I40E_PRIV_FLAGS_LINKPOLL_FLAG)
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if (flags & I40E_PRIV_FLAGS_LINKPOLL_FLAG)
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pf->flags |= I40E_FLAG_LINK_POLLING_ENABLED;
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pf->flags |= I40E_FLAG_LINK_POLLING_ENABLED;
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else
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else
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@ -2871,18 +2871,9 @@ static int i40e_configure_rx_ring(struct i40e_ring *ring)
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}
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}
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rx_ctx.dtype = vsi->dtype;
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rx_ctx.dtype = vsi->dtype;
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if (vsi->dtype) {
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set_ring_ps_enabled(ring);
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rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
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I40E_RX_SPLIT_IP |
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I40E_RX_SPLIT_TCP_UDP |
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I40E_RX_SPLIT_SCTP;
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} else {
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rx_ctx.hsplit_0 = 0;
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rx_ctx.hsplit_0 = 0;
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}
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rx_ctx.rxmax = min_t(u16, vsi->max_frame,
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rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len);
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(chain_len * ring->rx_buf_len));
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if (hw->revision_id == 0)
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if (hw->revision_id == 0)
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rx_ctx.lrxqthresh = 0;
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rx_ctx.lrxqthresh = 0;
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else
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else
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@ -2919,12 +2910,7 @@ static int i40e_configure_rx_ring(struct i40e_ring *ring)
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ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
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ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
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writel(0, ring->tail);
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writel(0, ring->tail);
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if (ring_is_ps_enabled(ring)) {
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i40e_alloc_rx_headers(ring);
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i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
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} else {
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i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
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i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
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}
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return 0;
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return 0;
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}
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}
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@ -2963,25 +2949,9 @@ static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
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else
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else
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vsi->max_frame = I40E_RXBUFFER_2048;
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vsi->max_frame = I40E_RXBUFFER_2048;
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/* figure out correct receive buffer length */
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switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
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I40E_FLAG_RX_PS_ENABLED)) {
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case I40E_FLAG_RX_1BUF_ENABLED:
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vsi->rx_hdr_len = 0;
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vsi->rx_hdr_len = 0;
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vsi->rx_buf_len = vsi->max_frame;
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vsi->rx_buf_len = vsi->max_frame;
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vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
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vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
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break;
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case I40E_FLAG_RX_PS_ENABLED:
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vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
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vsi->rx_buf_len = I40E_RXBUFFER_2048;
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vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
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break;
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default:
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vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
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vsi->rx_buf_len = I40E_RXBUFFER_2048;
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vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
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break;
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}
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#ifdef I40E_FCOE
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#ifdef I40E_FCOE
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/* setup rx buffer for FCoE */
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/* setup rx buffer for FCoE */
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@ -8460,11 +8430,6 @@ static int i40e_sw_init(struct i40e_pf *pf)
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I40E_FLAG_MSI_ENABLED |
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I40E_FLAG_MSI_ENABLED |
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I40E_FLAG_MSIX_ENABLED;
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I40E_FLAG_MSIX_ENABLED;
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if (iommu_present(&pci_bus_type))
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pf->flags |= I40E_FLAG_RX_PS_ENABLED;
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else
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pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
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/* Set default ITR */
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/* Set default ITR */
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pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
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pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
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pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
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pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
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@ -10699,7 +10664,7 @@ static void i40e_print_features(struct i40e_pf *pf)
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i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
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i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
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pf->hw.func_caps.num_vsis,
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pf->hw.func_caps.num_vsis,
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pf->vsi[pf->lan_vsi]->num_queue_pairs,
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pf->vsi[pf->lan_vsi]->num_queue_pairs,
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pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
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"1BUF");
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if (pf->flags & I40E_FLAG_RSS_ENABLED)
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if (pf->flags & I40E_FLAG_RSS_ENABLED)
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i += snprintf(&buf[i], REMAIN(i), " RSS");
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i += snprintf(&buf[i], REMAIN(i), " RSS");
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@ -1032,22 +1032,6 @@ void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
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if (!rx_ring->rx_bi)
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if (!rx_ring->rx_bi)
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return;
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return;
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if (ring_is_ps_enabled(rx_ring)) {
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int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
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rx_bi = &rx_ring->rx_bi[0];
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if (rx_bi->hdr_buf) {
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dma_free_coherent(dev,
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bufsz,
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rx_bi->hdr_buf,
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rx_bi->dma);
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for (i = 0; i < rx_ring->count; i++) {
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rx_bi = &rx_ring->rx_bi[i];
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rx_bi->dma = 0;
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rx_bi->hdr_buf = NULL;
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}
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}
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}
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/* Free all the Rx ring sk_buffs */
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/* Free all the Rx ring sk_buffs */
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for (i = 0; i < rx_ring->count; i++) {
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for (i = 0; i < rx_ring->count; i++) {
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rx_bi = &rx_ring->rx_bi[i];
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rx_bi = &rx_ring->rx_bi[i];
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@ -1502,230 +1486,6 @@ static inline void i40e_rx_hash(struct i40e_ring *ring,
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}
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}
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}
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}
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/**
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* i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
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* @rx_ring: rx ring to clean
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* @budget: how many cleans we're allowed
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*
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* Returns true if there's any budget left (e.g. the clean is finished)
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**/
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static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, const int budget)
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{
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unsigned int total_rx_bytes = 0, total_rx_packets = 0;
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u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
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u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
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struct i40e_vsi *vsi = rx_ring->vsi;
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u16 i = rx_ring->next_to_clean;
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union i40e_rx_desc *rx_desc;
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u32 rx_error, rx_status;
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bool failure = false;
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u8 rx_ptype;
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u64 qword;
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u32 copysize;
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if (budget <= 0)
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return 0;
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do {
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struct i40e_rx_buffer *rx_bi;
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struct sk_buff *skb;
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u16 vlan_tag;
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/* return some buffers to hardware, one at a time is too slow */
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if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
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failure = failure ||
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i40e_alloc_rx_buffers_ps(rx_ring,
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cleaned_count);
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cleaned_count = 0;
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}
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i = rx_ring->next_to_clean;
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rx_desc = I40E_RX_DESC(rx_ring, i);
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qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
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rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
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I40E_RXD_QW1_STATUS_SHIFT;
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if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
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break;
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/* This memory barrier is needed to keep us from reading
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* any other fields out of the rx_desc until we know the
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* DD bit is set.
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*/
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dma_rmb();
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/* sync header buffer for reading */
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dma_sync_single_range_for_cpu(rx_ring->dev,
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rx_ring->rx_bi[0].dma,
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i * rx_ring->rx_hdr_len,
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rx_ring->rx_hdr_len,
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DMA_FROM_DEVICE);
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if (i40e_rx_is_programming_status(qword)) {
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i40e_clean_programming_status(rx_ring, rx_desc);
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I40E_RX_INCREMENT(rx_ring, i);
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continue;
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}
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rx_bi = &rx_ring->rx_bi[i];
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skb = rx_bi->skb;
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if (likely(!skb)) {
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skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
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rx_ring->rx_hdr_len,
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GFP_ATOMIC |
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__GFP_NOWARN);
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if (!skb) {
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rx_ring->rx_stats.alloc_buff_failed++;
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failure = true;
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break;
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}
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/* initialize queue mapping */
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skb_record_rx_queue(skb, rx_ring->queue_index);
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/* we are reusing so sync this buffer for CPU use */
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dma_sync_single_range_for_cpu(rx_ring->dev,
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rx_ring->rx_bi[0].dma,
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i * rx_ring->rx_hdr_len,
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rx_ring->rx_hdr_len,
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DMA_FROM_DEVICE);
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}
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rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
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I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
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rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
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I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
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rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
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I40E_RXD_QW1_LENGTH_SPH_SHIFT;
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rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
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I40E_RXD_QW1_ERROR_SHIFT;
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rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
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rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
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rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
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I40E_RXD_QW1_PTYPE_SHIFT;
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/* sync half-page for reading */
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dma_sync_single_range_for_cpu(rx_ring->dev,
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rx_bi->page_dma,
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rx_bi->page_offset,
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PAGE_SIZE / 2,
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DMA_FROM_DEVICE);
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prefetch(page_address(rx_bi->page) + rx_bi->page_offset);
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rx_bi->skb = NULL;
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cleaned_count++;
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copysize = 0;
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if (rx_hbo || rx_sph) {
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int len;
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if (rx_hbo)
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len = I40E_RX_HDR_SIZE;
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|
||||||
else
|
|
||||||
len = rx_header_len;
|
|
||||||
memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
|
|
||||||
} else if (skb->len == 0) {
|
|
||||||
int len;
|
|
||||||
unsigned char *va = page_address(rx_bi->page) +
|
|
||||||
rx_bi->page_offset;
|
|
||||||
|
|
||||||
len = min(rx_packet_len, rx_ring->rx_hdr_len);
|
|
||||||
memcpy(__skb_put(skb, len), va, len);
|
|
||||||
copysize = len;
|
|
||||||
rx_packet_len -= len;
|
|
||||||
}
|
|
||||||
/* Get the rest of the data if this was a header split */
|
|
||||||
if (rx_packet_len) {
|
|
||||||
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
|
|
||||||
rx_bi->page,
|
|
||||||
rx_bi->page_offset + copysize,
|
|
||||||
rx_packet_len, I40E_RXBUFFER_2048);
|
|
||||||
|
|
||||||
/* If the page count is more than 2, then both halves
|
|
||||||
* of the page are used and we need to free it. Do it
|
|
||||||
* here instead of in the alloc code. Otherwise one
|
|
||||||
* of the half-pages might be released between now and
|
|
||||||
* then, and we wouldn't know which one to use.
|
|
||||||
* Don't call get_page and free_page since those are
|
|
||||||
* both expensive atomic operations that just change
|
|
||||||
* the refcount in opposite directions. Just give the
|
|
||||||
* page to the stack; he can have our refcount.
|
|
||||||
*/
|
|
||||||
if (page_count(rx_bi->page) > 2) {
|
|
||||||
dma_unmap_page(rx_ring->dev,
|
|
||||||
rx_bi->page_dma,
|
|
||||||
PAGE_SIZE,
|
|
||||||
DMA_FROM_DEVICE);
|
|
||||||
rx_bi->page = NULL;
|
|
||||||
rx_bi->page_dma = 0;
|
|
||||||
rx_ring->rx_stats.realloc_count++;
|
|
||||||
} else {
|
|
||||||
get_page(rx_bi->page);
|
|
||||||
/* switch to the other half-page here; the
|
|
||||||
* allocation code programs the right addr
|
|
||||||
* into HW. If we haven't used this half-page,
|
|
||||||
* the address won't be changed, and HW can
|
|
||||||
* just use it next time through.
|
|
||||||
*/
|
|
||||||
rx_bi->page_offset ^= PAGE_SIZE / 2;
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
I40E_RX_INCREMENT(rx_ring, i);
|
|
||||||
|
|
||||||
if (unlikely(
|
|
||||||
!(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
|
|
||||||
struct i40e_rx_buffer *next_buffer;
|
|
||||||
|
|
||||||
next_buffer = &rx_ring->rx_bi[i];
|
|
||||||
next_buffer->skb = skb;
|
|
||||||
rx_ring->rx_stats.non_eop_descs++;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ERR_MASK will only have valid bits if EOP set */
|
|
||||||
if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
|
|
||||||
dev_kfree_skb_any(skb);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
|
|
||||||
|
|
||||||
if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
|
|
||||||
i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
|
|
||||||
I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
|
|
||||||
I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
|
|
||||||
rx_ring->last_rx_timestamp = jiffies;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* probably a little skewed due to removing CRC */
|
|
||||||
total_rx_bytes += skb->len;
|
|
||||||
total_rx_packets++;
|
|
||||||
|
|
||||||
skb->protocol = eth_type_trans(skb, rx_ring->netdev);
|
|
||||||
|
|
||||||
i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
|
|
||||||
|
|
||||||
vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
|
|
||||||
? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
|
|
||||||
: 0;
|
|
||||||
#ifdef I40E_FCOE
|
|
||||||
if (unlikely(
|
|
||||||
i40e_rx_is_fcoe(rx_ptype) &&
|
|
||||||
!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb))) {
|
|
||||||
dev_kfree_skb_any(skb);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
i40e_receive_skb(rx_ring, skb, vlan_tag);
|
|
||||||
|
|
||||||
rx_desc->wb.qword1.status_error_len = 0;
|
|
||||||
|
|
||||||
} while (likely(total_rx_packets < budget));
|
|
||||||
|
|
||||||
u64_stats_update_begin(&rx_ring->syncp);
|
|
||||||
rx_ring->stats.packets += total_rx_packets;
|
|
||||||
rx_ring->stats.bytes += total_rx_bytes;
|
|
||||||
u64_stats_update_end(&rx_ring->syncp);
|
|
||||||
rx_ring->q_vector->rx.total_packets += total_rx_packets;
|
|
||||||
rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
|
|
||||||
|
|
||||||
return failure ? budget : total_rx_packets;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
|
* i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
|
||||||
* @rx_ring: rx ring to clean
|
* @rx_ring: rx ring to clean
|
||||||
|
@ -2001,9 +1761,6 @@ int i40e_napi_poll(struct napi_struct *napi, int budget)
|
||||||
i40e_for_each_ring(ring, q_vector->rx) {
|
i40e_for_each_ring(ring, q_vector->rx) {
|
||||||
int cleaned;
|
int cleaned;
|
||||||
|
|
||||||
if (ring_is_ps_enabled(ring))
|
|
||||||
cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
|
|
||||||
else
|
|
||||||
cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
|
cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
|
||||||
|
|
||||||
work_done += cleaned;
|
work_done += cleaned;
|
||||||
|
|
|
@ -245,16 +245,9 @@ struct i40e_rx_queue_stats {
|
||||||
enum i40e_ring_state_t {
|
enum i40e_ring_state_t {
|
||||||
__I40E_TX_FDIR_INIT_DONE,
|
__I40E_TX_FDIR_INIT_DONE,
|
||||||
__I40E_TX_XPS_INIT_DONE,
|
__I40E_TX_XPS_INIT_DONE,
|
||||||
__I40E_RX_PS_ENABLED,
|
|
||||||
__I40E_RX_16BYTE_DESC_ENABLED,
|
__I40E_RX_16BYTE_DESC_ENABLED,
|
||||||
};
|
};
|
||||||
|
|
||||||
#define ring_is_ps_enabled(ring) \
|
|
||||||
test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
|
|
||||||
#define set_ring_ps_enabled(ring) \
|
|
||||||
set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
|
|
||||||
#define clear_ring_ps_enabled(ring) \
|
|
||||||
clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
|
|
||||||
#define ring_is_16byte_desc_enabled(ring) \
|
#define ring_is_16byte_desc_enabled(ring) \
|
||||||
test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
|
test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
|
||||||
#define set_ring_16byte_desc_enabled(ring) \
|
#define set_ring_16byte_desc_enabled(ring) \
|
||||||
|
|
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