drm/radeon/mst: fix regression in lane/link handling.
The function this used changed in
092c96a8ab
drm/radeon: fix dp link rate selection (v2)
However for MST we should just always train to the
max link/rate. Though we probably need to limit this
for future hw, in theory radeon won't support it.
This fixes my 30" monitor with MST enabled.
Cc: stable@vger.kernel.org # v4.4
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Родитель
ae20f12d2d
Коммит
b36f7d26a7
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@ -525,17 +525,9 @@ static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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{
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{
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struct radeon_connector_atom_dig *dig_connector;
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struct radeon_connector_atom_dig *dig_connector;
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int ret;
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dig_connector = mst_enc->connector->con_priv;
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dig_connector = mst_enc->connector->con_priv;
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ret = radeon_dp_get_dp_link_config(&mst_enc->connector->base,
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dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
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dig_connector->dpcd, adjusted_mode->clock,
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dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
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&dig_connector->dp_lane_count,
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&dig_connector->dp_clock);
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if (ret) {
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dig_connector->dp_lane_count = 0;
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dig_connector->dp_clock = 0;
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}
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DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
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DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
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dig_connector->dp_lane_count, dig_connector->dp_clock);
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dig_connector->dp_lane_count, dig_connector->dp_clock);
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}
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}
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