drm/nv50-/disp: add support for completion events
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
Родитель
996f5a0823
Коммит
b38a2322df
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@ -68,6 +68,10 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
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if (ret)
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return ret;
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nv_engine(priv)->sclass = gm107_disp_base_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nvd0_disp_intr;
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@ -29,6 +29,7 @@
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#include <core/enum.h>
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#include <nvif/unpack.h>
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#include <nvif/class.h>
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#include <nvif/event.h>
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#include <subdev/bios.h>
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#include <subdev/bios/dcb.h>
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@ -82,6 +83,71 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
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nouveau_namedb_destroy(&chan->base);
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}
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static void
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nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
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{
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struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
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nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index);
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}
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static void
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nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
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{
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struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
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nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index);
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}
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void
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nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid)
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{
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struct nvif_notify_uevent_rep {
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} rep;
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nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep));
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}
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int
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nv50_disp_chan_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
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struct nvkm_notify *notify)
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{
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struct nv50_disp_dmac *dmac = (void *)object;
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union {
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struct nvif_notify_uevent_req none;
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} *args = data;
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int ret;
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if (nvif_unvers(args->none)) {
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notify->size = sizeof(struct nvif_notify_uevent_rep);
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notify->types = 1;
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notify->index = dmac->base.chid;
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return 0;
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}
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return ret;
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}
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const struct nvkm_event_func
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nv50_disp_chan_uevent = {
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.ctor = nv50_disp_chan_uevent_ctor,
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.init = nv50_disp_chan_uevent_init,
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.fini = nv50_disp_chan_uevent_fini,
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};
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int
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nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type,
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struct nvkm_event **pevent)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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switch (type) {
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case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT:
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*pevent = &priv->uevent;
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return 0;
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default:
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break;
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}
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return -EINVAL;
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}
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int
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nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
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{
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@ -195,7 +261,7 @@ nv50_disp_dmac_init(struct nouveau_object *object)
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return ret;
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/* enable error reporting */
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nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
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nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid);
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/* initialise channel for dma command submission */
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nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
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@ -232,7 +298,7 @@ nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
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return -EBUSY;
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}
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/* disable error reporting */
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/* disable error reporting and completion notifications */
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nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
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return nv50_disp_chan_fini(&dmac->base, suspend);
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@ -454,7 +520,7 @@ nv50_disp_mast_init(struct nouveau_object *object)
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return ret;
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/* enable error reporting */
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nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
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nv_mask(priv, 0x610028, 0x00010000, 0x00010000);
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/* attempt to unstick channel from some unknown state */
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if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
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@ -494,7 +560,7 @@ nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
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return -EBUSY;
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}
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/* disable error reporting */
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/* disable error reporting and completion notifications */
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nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
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return nv50_disp_chan_fini(&mast->base, suspend);
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@ -507,6 +573,7 @@ nv50_disp_mast_ofuncs = {
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.base.init = nv50_disp_mast_init,
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.base.fini = nv50_disp_mast_fini,
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.base.map = nv50_disp_chan_map,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 0,
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@ -607,6 +674,7 @@ nv50_disp_sync_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nv50_disp_dmac_init,
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.base.fini = nv50_disp_dmac_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -696,6 +764,7 @@ nv50_disp_ovly_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nv50_disp_dmac_init,
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.base.fini = nv50_disp_dmac_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -813,6 +882,7 @@ nv50_disp_oimm_ofuncs = {
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.base.dtor = nv50_disp_pioc_dtor,
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.base.init = nv50_disp_pioc_init,
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.base.fini = nv50_disp_pioc_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -860,6 +930,7 @@ nv50_disp_curs_ofuncs = {
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.base.dtor = nv50_disp_pioc_dtor,
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.base.init = nv50_disp_pioc_init,
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.base.fini = nv50_disp_pioc_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -1846,6 +1917,12 @@ nv50_disp_intr(struct nouveau_subdev *subdev)
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intr0 &= ~(0x00010000 << chid);
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}
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while (intr0 & 0x0000001f) {
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u32 chid = __ffs(intr0 & 0x0000001f);
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nv50_disp_chan_uevent_send(priv, chid);
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intr0 &= ~(0x00000001 << chid);
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}
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if (intr1 & 0x00000004) {
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nouveau_disp_vblank(&priv->base, 0);
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nv_wr32(priv, 0x610024, 0x00000004);
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@ -1880,6 +1957,10 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
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if (ret)
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return ret;
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nv_engine(priv)->sclass = nv50_disp_base_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nv50_disp_intr;
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@ -26,6 +26,8 @@ struct nv50_disp_priv {
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struct work_struct supervisor;
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u32 super;
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struct nvkm_event uevent;
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struct {
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int nr;
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} head;
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@ -116,9 +118,16 @@ struct nv50_disp_chan {
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int chid;
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};
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int nv50_disp_chan_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
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int nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *);
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u32 nv50_disp_chan_rd32(struct nouveau_object *, u64);
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void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
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extern const struct nvkm_event_func nv50_disp_chan_uevent;
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int nv50_disp_chan_uevent_ctor(struct nouveau_object *, void *, u32,
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struct nvkm_notify *);
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void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int);
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extern const struct nvkm_event_func nvd0_disp_chan_uevent;
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#define nv50_disp_chan_init(a) \
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nouveau_namedb_init(&(a)->base)
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@ -236,6 +236,10 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
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if (ret)
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return ret;
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nv_engine(priv)->sclass = nv84_disp_base_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nv50_disp_intr;
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@ -95,6 +95,10 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
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if (ret)
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return ret;
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nv_engine(priv)->sclass = nv94_disp_base_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nv50_disp_intr;
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@ -112,6 +112,10 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
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if (ret)
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return ret;
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nv_engine(priv)->sclass = nva0_disp_base_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nv50_disp_intr;
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@ -67,6 +67,10 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
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if (ret)
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return ret;
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nv_engine(priv)->sclass = nva3_disp_base_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nv50_disp_intr;
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@ -42,6 +42,31 @@
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#include "nv50.h"
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/*******************************************************************************
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* EVO channel base class
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******************************************************************************/
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static void
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nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
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{
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struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
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nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index);
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}
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static void
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nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
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{
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struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
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nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index);
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}
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const struct nvkm_event_func
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nvd0_disp_chan_uevent = {
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.ctor = nv50_disp_chan_uevent_ctor,
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.init = nvd0_disp_chan_uevent_init,
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.fini = nvd0_disp_chan_uevent_fini,
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};
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/*******************************************************************************
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* EVO DMA channel base class
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******************************************************************************/
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@ -77,7 +102,6 @@ nvd0_disp_dmac_init(struct nouveau_object *object)
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return ret;
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/* enable error reporting */
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nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
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nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
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/* initialise channel for dma command submission */
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@ -115,7 +139,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
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return -EBUSY;
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}
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/* disable error reporting */
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/* disable error reporting and completion notification */
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nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
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nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
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@ -278,7 +302,6 @@ nvd0_disp_mast_init(struct nouveau_object *object)
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return ret;
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/* enable error reporting */
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nv_mask(priv, 0x610090, 0x00000001, 0x00000001);
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nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001);
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/* initialise channel for dma command submission */
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@ -313,7 +336,7 @@ nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
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return -EBUSY;
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}
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/* disable error reporting */
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/* disable error reporting and completion notification */
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nv_mask(priv, 0x610090, 0x00000001, 0x00000000);
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nv_mask(priv, 0x6100a0, 0x00000001, 0x00000000);
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@ -326,6 +349,7 @@ nvd0_disp_mast_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nvd0_disp_mast_init,
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.base.fini = nvd0_disp_mast_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -419,6 +443,7 @@ nvd0_disp_sync_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nvd0_disp_dmac_init,
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.base.fini = nvd0_disp_dmac_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -499,6 +524,7 @@ nvd0_disp_ovly_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nvd0_disp_dmac_init,
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.base.fini = nvd0_disp_dmac_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -524,7 +550,6 @@ nvd0_disp_pioc_init(struct nouveau_object *object)
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return ret;
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/* enable error reporting */
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nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
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nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
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/* activate channel */
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@ -553,7 +578,7 @@ nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
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return -EBUSY;
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}
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/* disable error reporting */
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/* disable error reporting and completion notification */
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nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
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nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
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@ -570,6 +595,7 @@ nvd0_disp_oimm_ofuncs = {
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.base.dtor = nv50_disp_pioc_dtor,
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.base.init = nvd0_disp_pioc_init,
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.base.fini = nvd0_disp_pioc_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -586,6 +612,7 @@ nvd0_disp_curs_ofuncs = {
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.base.dtor = nv50_disp_pioc_dtor,
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.base.init = nvd0_disp_pioc_init,
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.base.fini = nvd0_disp_pioc_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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@ -1153,7 +1180,11 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
|
|||
|
||||
if (intr & 0x00000001) {
|
||||
u32 stat = nv_rd32(priv, 0x61008c);
|
||||
nv_wr32(priv, 0x61008c, stat);
|
||||
while (stat) {
|
||||
int chid = __ffs(stat); stat &= ~(1 << chid);
|
||||
nv50_disp_chan_uevent_send(priv, chid);
|
||||
nv_wr32(priv, 0x61008c, 1 << chid);
|
||||
}
|
||||
intr &= ~0x00000001;
|
||||
}
|
||||
|
||||
|
|
@ -1209,6 +1240,10 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nvd0_disp_base_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nvd0_disp_intr;
|
||||
|
|
|
|||
|
|
@ -233,6 +233,10 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nve0_disp_base_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nvd0_disp_intr;
|
||||
|
|
|
|||
|
|
@ -68,6 +68,10 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nvf0_disp_base_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nvd0_disp_intr;
|
||||
|
|
|
|||
|
|
@ -479,6 +479,8 @@ struct nv50_disp_core_channel_dma_v0 {
|
|||
__u32 pushbuf;
|
||||
};
|
||||
|
||||
#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
|
||||
|
||||
/* cursor immediate */
|
||||
struct nv50_disp_cursor_v0 {
|
||||
__u8 version;
|
||||
|
|
@ -486,6 +488,8 @@ struct nv50_disp_cursor_v0 {
|
|||
__u8 pad02[6];
|
||||
};
|
||||
|
||||
#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
|
||||
|
||||
/* base */
|
||||
struct nv50_disp_base_channel_dma_v0 {
|
||||
__u8 version;
|
||||
|
|
@ -494,6 +498,8 @@ struct nv50_disp_base_channel_dma_v0 {
|
|||
__u32 pushbuf;
|
||||
};
|
||||
|
||||
#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
|
||||
|
||||
/* overlay */
|
||||
struct nv50_disp_overlay_channel_dma_v0 {
|
||||
__u8 version;
|
||||
|
|
@ -502,6 +508,8 @@ struct nv50_disp_overlay_channel_dma_v0 {
|
|||
__u32 pushbuf;
|
||||
};
|
||||
|
||||
#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
|
||||
|
||||
/* overlay immediate */
|
||||
struct nv50_disp_overlay_v0 {
|
||||
__u8 version;
|
||||
|
|
@ -509,6 +517,7 @@ struct nv50_disp_overlay_v0 {
|
|||
__u8 pad02[6];
|
||||
};
|
||||
|
||||
#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
|
||||
|
||||
/*******************************************************************************
|
||||
* fermi
|
||||
|
|
|
|||
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