iio: adc: Add ad7124 support
The ad7124-4 and ad7124-8 are a family of 4 and 8 channel sigma-delta ADCs with 24-bit precision and reference. Three power modes are available which in turn affect the output data rate: * Full power: 9.38 SPS to 19,200 SPS * Mid power: 2.34 SPS to 4800 SPS * Low power: 1.17 SPS to 2400 SPS The ad7124-4 can be configured to have four differential inputs, while ad7124-8 can have 8. Moreover, ad7124 also supports per channel configuration. Each configuration consists of gain, reference source, output data rate and bipolar/unipolar configuration. Datasheets: Link: http://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-4.pdf Link: http://www.analog.com/media/en/technical-documentation/data-sheets/ad7124-8.pdf Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Stefan Popa
Jonathan Cameron
Родитель
90c430d32c
Коммит
b3af341bbd
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@ -839,6 +839,13 @@ S: Supported
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F: drivers/iio/dac/ad5758.c
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F: Documentation/devicetree/bindings/iio/dac/ad5758.txt
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ANALOG DEVICES INC AD7124 DRIVER
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M: Stefan Popa <stefan.popa@analog.com>
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L: linux-iio@vger.kernel.org
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W: http://ez.analog.com/community/linux-device-drivers
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S: Supported
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F: drivers/iio/adc/ad7124.c
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ANALOG DEVICES INC AD9389B DRIVER
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M: Hans Verkuil <hans.verkuil@cisco.com>
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L: linux-media@vger.kernel.org
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@ -10,6 +10,17 @@ config AD_SIGMA_DELTA
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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config AD7124
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tristate "Analog Devices AD7124 and similar sigma-delta ADCs driver"
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depends on SPI_MASTER
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select AD_SIGMA_DELTA
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help
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Say yes here to build support for Analog Devices AD7124-4 and AD7124-8
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SPI analog to digital converters (ADC).
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To compile this driver as a module, choose M here: the module will be
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called ad7124.
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config AD7266
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tristate "Analog Devices AD7265/AD7266 ADC driver"
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depends on SPI_MASTER
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@ -5,6 +5,7 @@
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# When adding new entries keep the list in alphabetical order
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obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o
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obj-$(CONFIG_AD7124) += ad7124.o
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obj-$(CONFIG_AD7266) += ad7266.o
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obj-$(CONFIG_AD7291) += ad7291.o
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obj-$(CONFIG_AD7298) += ad7298.o
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@ -0,0 +1,684 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* AD7124 SPI ADC driver
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*
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* Copyright 2018 Analog Devices Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spi/spi.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/adc/ad_sigma_delta.h>
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#include <linux/iio/sysfs.h>
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/* AD7124 registers */
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#define AD7124_COMMS 0x00
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#define AD7124_STATUS 0x00
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#define AD7124_ADC_CONTROL 0x01
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#define AD7124_DATA 0x02
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#define AD7124_IO_CONTROL_1 0x03
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#define AD7124_IO_CONTROL_2 0x04
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#define AD7124_ID 0x05
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#define AD7124_ERROR 0x06
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#define AD7124_ERROR_EN 0x07
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#define AD7124_MCLK_COUNT 0x08
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#define AD7124_CHANNEL(x) (0x09 + (x))
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#define AD7124_CONFIG(x) (0x19 + (x))
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#define AD7124_FILTER(x) (0x21 + (x))
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#define AD7124_OFFSET(x) (0x29 + (x))
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#define AD7124_GAIN(x) (0x31 + (x))
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/* AD7124_STATUS */
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#define AD7124_STATUS_POR_FLAG_MSK BIT(4)
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/* AD7124_ADC_CONTROL */
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#define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
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#define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
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#define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
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#define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
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/* AD7124_CHANNEL_X */
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#define AD7124_CHANNEL_EN_MSK BIT(15)
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#define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
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#define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
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#define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
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#define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
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#define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
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#define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
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#define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
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/* AD7124_CONFIG_X */
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#define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
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#define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
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#define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
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#define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
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#define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
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#define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
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/* AD7124_FILTER_X */
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#define AD7124_FILTER_FS_MSK GENMASK(10, 0)
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#define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
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enum ad7124_ids {
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ID_AD7124_4,
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ID_AD7124_8,
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};
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enum ad7124_ref_sel {
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AD7124_REFIN1,
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AD7124_REFIN2,
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AD7124_INT_REF,
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AD7124_AVDD_REF,
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};
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enum ad7124_power_mode {
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AD7124_LOW_POWER,
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AD7124_MID_POWER,
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AD7124_FULL_POWER,
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};
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static const unsigned int ad7124_gain[8] = {
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1, 2, 4, 8, 16, 32, 64, 128
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};
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static const int ad7124_master_clk_freq_hz[3] = {
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[AD7124_LOW_POWER] = 76800,
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[AD7124_MID_POWER] = 153600,
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[AD7124_FULL_POWER] = 614400,
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};
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static const char * const ad7124_ref_names[] = {
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[AD7124_REFIN1] = "refin1",
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[AD7124_REFIN2] = "refin2",
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[AD7124_INT_REF] = "int",
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[AD7124_AVDD_REF] = "avdd",
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};
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struct ad7124_chip_info {
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unsigned int num_inputs;
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};
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struct ad7124_channel_config {
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enum ad7124_ref_sel refsel;
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bool bipolar;
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unsigned int ain;
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unsigned int vref_mv;
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unsigned int pga_bits;
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unsigned int odr;
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};
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struct ad7124_state {
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const struct ad7124_chip_info *chip_info;
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struct ad_sigma_delta sd;
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struct ad7124_channel_config channel_config[4];
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struct regulator *vref[4];
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struct clk *mclk;
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unsigned int adc_control;
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unsigned int num_channels;
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};
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static const struct iio_chan_spec ad7124_channel_template = {
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.type = IIO_VOLTAGE,
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.indexed = 1,
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.differential = 1,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE) |
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BIT(IIO_CHAN_INFO_OFFSET) |
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BIT(IIO_CHAN_INFO_SAMP_FREQ),
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.scan_type = {
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.sign = 'u',
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.realbits = 24,
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.storagebits = 32,
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.shift = 8,
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.endianness = IIO_BE,
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},
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};
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static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
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[ID_AD7124_4] = {
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.num_inputs = 8,
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},
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[ID_AD7124_8] = {
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.num_inputs = 16,
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},
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};
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static int ad7124_find_closest_match(const int *array,
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unsigned int size, int val)
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{
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int i, idx;
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unsigned int diff_new, diff_old;
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diff_old = U32_MAX;
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idx = 0;
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for (i = 0; i < size; i++) {
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diff_new = abs(val - array[i]);
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if (diff_new < diff_old) {
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diff_old = diff_new;
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idx = i;
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}
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}
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return idx;
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}
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static int ad7124_spi_write_mask(struct ad7124_state *st,
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unsigned int addr,
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unsigned long mask,
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unsigned int val,
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unsigned int bytes)
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{
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unsigned int readval;
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int ret;
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ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
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if (ret < 0)
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return ret;
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readval &= ~mask;
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readval |= val;
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return ad_sd_write_reg(&st->sd, addr, bytes, readval);
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}
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static int ad7124_set_mode(struct ad_sigma_delta *sd,
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enum ad_sigma_delta_mode mode)
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{
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struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
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st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
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st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
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return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
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}
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static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
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{
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struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
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unsigned int val;
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val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
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AD7124_CHANNEL_SETUP(channel);
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return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
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}
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static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
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.set_channel = ad7124_set_channel,
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.set_mode = ad7124_set_mode,
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.has_registers = true,
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.addr_shift = 0,
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.read_mask = BIT(6),
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.data_reg = AD7124_DATA,
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};
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static int ad7124_set_channel_odr(struct ad7124_state *st,
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unsigned int channel,
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unsigned int odr)
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{
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unsigned int fclk, odr_sel_bits;
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int ret;
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fclk = clk_get_rate(st->mclk);
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/*
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* FS[10:0] = fCLK / (fADC x 32) where:
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* fADC is the output data rate
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* fCLK is the master clock frequency
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* FS[10:0] are the bits in the filter register
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* FS[10:0] can have a value from 1 to 2047
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*/
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odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
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if (odr_sel_bits < 1)
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odr_sel_bits = 1;
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else if (odr_sel_bits > 2047)
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odr_sel_bits = 2047;
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ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
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AD7124_FILTER_FS_MSK,
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AD7124_FILTER_FS(odr_sel_bits), 3);
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if (ret < 0)
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return ret;
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/* fADC = fCLK / (FS[10:0] x 32) */
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st->channel_config[channel].odr =
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DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
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return 0;
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}
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static int ad7124_set_channel_gain(struct ad7124_state *st,
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unsigned int channel,
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unsigned int gain)
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{
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unsigned int res;
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int ret;
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res = ad7124_find_closest_match(ad7124_gain,
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ARRAY_SIZE(ad7124_gain), gain);
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ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
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AD7124_CONFIG_PGA_MSK,
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AD7124_CONFIG_PGA(res), 2);
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if (ret < 0)
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return ret;
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st->channel_config[channel].pga_bits = res;
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return 0;
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}
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static int ad7124_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long info)
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{
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struct ad7124_state *st = iio_priv(indio_dev);
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int idx, ret;
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switch (info) {
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case IIO_CHAN_INFO_RAW:
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ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
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if (ret < 0)
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return ret;
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/* After the conversion is performed, disable the channel */
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ret = ad_sd_write_reg(&st->sd,
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AD7124_CHANNEL(chan->address), 2,
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st->channel_config[chan->address].ain |
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AD7124_CHANNEL_EN(0));
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if (ret < 0)
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return ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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idx = st->channel_config[chan->address].pga_bits;
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*val = st->channel_config[chan->address].vref_mv;
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if (st->channel_config[chan->address].bipolar)
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*val2 = chan->scan_type.realbits - 1 + idx;
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else
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*val2 = chan->scan_type.realbits + idx;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_OFFSET:
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if (st->channel_config[chan->address].bipolar)
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*val = -(1 << (chan->scan_type.realbits - 1));
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else
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*val = 0;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = st->channel_config[chan->address].odr;
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static int ad7124_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long info)
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{
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struct ad7124_state *st = iio_priv(indio_dev);
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unsigned int res, gain, full_scale, vref;
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switch (info) {
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case IIO_CHAN_INFO_SAMP_FREQ:
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if (val2 != 0)
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return -EINVAL;
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return ad7124_set_channel_odr(st, chan->address, val);
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case IIO_CHAN_INFO_SCALE:
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if (val != 0)
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return -EINVAL;
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if (st->channel_config[chan->address].bipolar)
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full_scale = 1 << (chan->scan_type.realbits - 1);
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else
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full_scale = 1 << chan->scan_type.realbits;
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vref = st->channel_config[chan->address].vref_mv * 1000000LL;
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res = DIV_ROUND_CLOSEST(vref, full_scale);
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gain = DIV_ROUND_CLOSEST(res, val2);
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return ad7124_set_channel_gain(st, chan->address, gain);
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default:
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return -EINVAL;
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}
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}
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static IIO_CONST_ATTR(in_voltage_scale_available,
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"0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
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static struct attribute *ad7124_attributes[] = {
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&iio_const_attr_in_voltage_scale_available.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group ad7124_attrs_group = {
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.attrs = ad7124_attributes,
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};
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static const struct iio_info ad7124_info = {
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.read_raw = ad7124_read_raw,
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.write_raw = ad7124_write_raw,
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.validate_trigger = ad_sd_validate_trigger,
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.attrs = &ad7124_attrs_group,
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};
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static int ad7124_soft_reset(struct ad7124_state *st)
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{
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unsigned int readval, timeout;
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int ret;
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ret = ad_sd_reset(&st->sd, 64);
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if (ret < 0)
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return ret;
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timeout = 100;
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do {
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ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
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if (ret < 0)
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return ret;
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if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
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return 0;
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/* The AD7124 requires typically 2ms to power up and settle */
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usleep_range(100, 2000);
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} while (--timeout);
|
||||
|
||||
dev_err(&st->sd.spi->dev, "Soft reset failed\n");
|
||||
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static int ad7124_init_channel_vref(struct ad7124_state *st,
|
||||
unsigned int channel_number)
|
||||
{
|
||||
unsigned int refsel = st->channel_config[channel_number].refsel;
|
||||
|
||||
switch (refsel) {
|
||||
case AD7124_REFIN1:
|
||||
case AD7124_REFIN2:
|
||||
case AD7124_AVDD_REF:
|
||||
if (IS_ERR(st->vref[refsel])) {
|
||||
dev_err(&st->sd.spi->dev,
|
||||
"Error, trying to use external voltage reference without a %s regulator.\n",
|
||||
ad7124_ref_names[refsel]);
|
||||
return PTR_ERR(st->vref[refsel]);
|
||||
}
|
||||
st->channel_config[channel_number].vref_mv =
|
||||
regulator_get_voltage(st->vref[refsel]);
|
||||
/* Conversion from uV to mV */
|
||||
st->channel_config[channel_number].vref_mv /= 1000;
|
||||
break;
|
||||
case AD7124_INT_REF:
|
||||
st->channel_config[channel_number].vref_mv = 2500;
|
||||
break;
|
||||
default:
|
||||
dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct ad7124_state *st = iio_priv(indio_dev);
|
||||
struct device_node *child;
|
||||
struct iio_chan_spec *chan;
|
||||
unsigned int ain[2], channel = 0, tmp;
|
||||
int ret;
|
||||
|
||||
st->num_channels = of_get_available_child_count(np);
|
||||
if (!st->num_channels) {
|
||||
dev_err(indio_dev->dev.parent, "no channel children\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
|
||||
sizeof(*chan), GFP_KERNEL);
|
||||
if (!chan)
|
||||
return -ENOMEM;
|
||||
|
||||
indio_dev->channels = chan;
|
||||
indio_dev->num_channels = st->num_channels;
|
||||
|
||||
for_each_available_child_of_node(np, child) {
|
||||
ret = of_property_read_u32(child, "reg", &channel);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = of_property_read_u32_array(child, "diff-channels",
|
||||
ain, 2);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
if (ain[0] >= st->chip_info->num_inputs ||
|
||||
ain[1] >= st->chip_info->num_inputs) {
|
||||
dev_err(indio_dev->dev.parent,
|
||||
"Input pin number out of range.\n");
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
|
||||
AD7124_CHANNEL_AINM(ain[1]);
|
||||
st->channel_config[channel].bipolar =
|
||||
of_property_read_bool(child, "bipolar");
|
||||
|
||||
ret = of_property_read_u32(child, "adi,reference-select", &tmp);
|
||||
if (ret)
|
||||
st->channel_config[channel].refsel = AD7124_INT_REF;
|
||||
else
|
||||
st->channel_config[channel].refsel = tmp;
|
||||
|
||||
*chan = ad7124_channel_template;
|
||||
chan->address = channel;
|
||||
chan->scan_index = channel;
|
||||
chan->channel = ain[0];
|
||||
chan->channel2 = ain[1];
|
||||
|
||||
chan++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
err:
|
||||
of_node_put(child);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ad7124_setup(struct ad7124_state *st)
|
||||
{
|
||||
unsigned int val, fclk, power_mode;
|
||||
int i, ret;
|
||||
|
||||
fclk = clk_get_rate(st->mclk);
|
||||
if (!fclk)
|
||||
return -EINVAL;
|
||||
|
||||
/* The power mode changes the master clock frequency */
|
||||
power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
|
||||
ARRAY_SIZE(ad7124_master_clk_freq_hz),
|
||||
fclk);
|
||||
if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
|
||||
ret = clk_set_rate(st->mclk, fclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Set the power mode */
|
||||
st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
|
||||
st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
|
||||
ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < st->num_channels; i++) {
|
||||
val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
|
||||
ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = ad7124_init_channel_vref(st, i);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
|
||||
AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel);
|
||||
ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
/*
|
||||
* 9.38 SPS is the minimum output data rate supported
|
||||
* regardless of the selected power mode. Round it up to 10 and
|
||||
* set all the enabled channels to this default value.
|
||||
*/
|
||||
ret = ad7124_set_channel_odr(st, i, 10);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ad7124_probe(struct spi_device *spi)
|
||||
{
|
||||
const struct spi_device_id *id;
|
||||
struct ad7124_state *st;
|
||||
struct iio_dev *indio_dev;
|
||||
int i, ret;
|
||||
|
||||
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
||||
if (!indio_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
st = iio_priv(indio_dev);
|
||||
|
||||
id = spi_get_device_id(spi);
|
||||
st->chip_info = &ad7124_chip_info_tbl[id->driver_data];
|
||||
|
||||
ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
|
||||
|
||||
spi_set_drvdata(spi, indio_dev);
|
||||
|
||||
indio_dev->dev.parent = &spi->dev;
|
||||
indio_dev->name = spi_get_device_id(spi)->name;
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
indio_dev->info = &ad7124_info;
|
||||
|
||||
ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
|
||||
if (i == AD7124_INT_REF)
|
||||
continue;
|
||||
|
||||
st->vref[i] = devm_regulator_get_optional(&spi->dev,
|
||||
ad7124_ref_names[i]);
|
||||
if (PTR_ERR(st->vref[i]) == -ENODEV)
|
||||
continue;
|
||||
else if (IS_ERR(st->vref[i]))
|
||||
return PTR_ERR(st->vref[i]);
|
||||
|
||||
ret = regulator_enable(st->vref[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
st->mclk = devm_clk_get(&spi->dev, "mclk");
|
||||
if (IS_ERR(st->mclk)) {
|
||||
ret = PTR_ERR(st->mclk);
|
||||
goto error_regulator_disable;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(st->mclk);
|
||||
if (ret < 0)
|
||||
goto error_regulator_disable;
|
||||
|
||||
ret = ad7124_soft_reset(st);
|
||||
if (ret < 0)
|
||||
goto error_clk_disable_unprepare;
|
||||
|
||||
ret = ad7124_setup(st);
|
||||
if (ret < 0)
|
||||
goto error_clk_disable_unprepare;
|
||||
|
||||
ret = ad_sd_setup_buffer_and_trigger(indio_dev);
|
||||
if (ret < 0)
|
||||
goto error_clk_disable_unprepare;
|
||||
|
||||
ret = iio_device_register(indio_dev);
|
||||
if (ret < 0) {
|
||||
dev_err(&spi->dev, "Failed to register iio device\n");
|
||||
goto error_remove_trigger;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
error_remove_trigger:
|
||||
ad_sd_cleanup_buffer_and_trigger(indio_dev);
|
||||
error_clk_disable_unprepare:
|
||||
clk_disable_unprepare(st->mclk);
|
||||
error_regulator_disable:
|
||||
for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
|
||||
if (!IS_ERR_OR_NULL(st->vref[i]))
|
||||
regulator_disable(st->vref[i]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ad7124_remove(struct spi_device *spi)
|
||||
{
|
||||
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
||||
struct ad7124_state *st = iio_priv(indio_dev);
|
||||
int i;
|
||||
|
||||
iio_device_unregister(indio_dev);
|
||||
ad_sd_cleanup_buffer_and_trigger(indio_dev);
|
||||
clk_disable_unprepare(st->mclk);
|
||||
|
||||
for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
|
||||
if (!IS_ERR_OR_NULL(st->vref[i]))
|
||||
regulator_disable(st->vref[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct spi_device_id ad7124_id_table[] = {
|
||||
{ "ad7124-4", ID_AD7124_4 },
|
||||
{ "ad7124-8", ID_AD7124_8 },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(spi, ad7124_id_table);
|
||||
|
||||
static const struct of_device_id ad7124_of_match[] = {
|
||||
{ .compatible = "adi,ad7124-4" },
|
||||
{ .compatible = "adi,ad7124-8" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ad7124_of_match);
|
||||
|
||||
static struct spi_driver ad71124_driver = {
|
||||
.driver = {
|
||||
.name = "ad7124",
|
||||
.of_match_table = ad7124_of_match,
|
||||
},
|
||||
.probe = ad7124_probe,
|
||||
.remove = ad7124_remove,
|
||||
.id_table = ad7124_id_table,
|
||||
};
|
||||
module_spi_driver(ad71124_driver);
|
||||
|
||||
MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
|
||||
MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
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