Add initial support for I3C along with 2 I3C master controller drivers.
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This commit is contained in:
Linus Torvalds
Коммит
b3cc2bfe72
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What: /sys/bus/i3c/devices/i3c-<bus-id>
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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An I3C bus. This directory will contain one sub-directory per
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I3C device present on the bus.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/current_master
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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Expose the master that owns the bus (<bus-id>-<master-pid>) at
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the time this file is read. Note that bus ownership can change
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overtime, so there's no guarantee that when the read() call
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returns, the value returned is still valid.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/mode
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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I3C bus mode. Can be "pure", "mixed-fast" or "mixed-slow". See
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the I3C specification for a detailed description of what each
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of these modes implies.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/i3c_scl_frequency
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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The frequency (expressed in Hz) of the SCL signal when
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operating in I3C SDR mode.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/i2c_scl_frequency
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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The frequency (expressed in Hz) of the SCL signal when
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operating in I2C mode.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/dynamic_address
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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Dynamic address assigned to the master controller. This
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address may change if the bus is re-initialized.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/bcr
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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BCR stands for Bus Characteristics Register and express the
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device capabilities in term of speed, maximum read/write
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length, etc. See the I3C specification for more details.
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This entry describes the BCR of the master controller driving
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the bus.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/dcr
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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DCR stands for Device Characteristics Register and express the
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device capabilities in term of exposed features. See the I3C
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specification for more details.
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This entry describes the DCR of the master controller driving
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the bus.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/pid
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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PID stands for Provisional ID and is used to uniquely identify
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a device on a bus. This PID contains information about the
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vendor, the part and an instance ID so that several devices of
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the same type can be connected on the same bus.
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See the I3C specification for more details.
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This entry describes the PID of the master controller driving
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the bus.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/hdrcap
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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Expose the HDR (High Data Rate) capabilities of a device.
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Returns a list of supported HDR mode, each element is separated
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by space. Modes can be "hdr-ddr", "hdr-tsp" and "hdr-tsl".
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See the I3C specification for more details about these HDR
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modes.
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This entry describes the HDRCAP of the master controller
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driving the bus.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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An I3C device present on I3C bus identified by <bus-id>. Note
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that all devices are represented including the master driving
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the bus.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>/dynamic_address
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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Dynamic address assigned to device <bus-id>-<device-pid>. This
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address may change if the bus is re-initialized.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>/bcr
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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BCR stands for Bus Characteristics Register and express the
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device capabilities in term of speed, maximum read/write
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length, etc. See the I3C specification for more details.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>/dcr
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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DCR stands for Device Characteristics Register and express the
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device capabilities in term of exposed features. See the I3C
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specification for more details.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>/pid
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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PID stands for Provisional ID and is used to uniquely identify
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a device on a bus. This PID contains information about the
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vendor, the part and an instance ID so that several devices of
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the same type can be connected on the same bus.
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See the I3C specification for more details.
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What: /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>/hdrcap
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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Expose the HDR (High Data Rate) capabilities of a device.
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Returns a list of supported HDR mode, each element is separated
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by space. Modes can be "hdr-ddr", "hdr-tsp" and "hdr-tsl".
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See the I3C specification for more details about these HDR
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modes.
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What: /sys/bus/i3c/devices/<bus-id>-<device-pid>
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KernelVersion: 5.0
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Contact: linux-i3c@vger.kernel.org
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Description:
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These directories are just symbolic links to
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/sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>.
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Bindings for cadence I3C master block
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=====================================
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Required properties:
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--------------------
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- compatible: shall be "cdns,i3c-master"
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- clocks: shall reference the pclk and sysclk
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- clock-names: shall contain "pclk" and "sysclk"
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- interrupts: the interrupt line connected to this I3C master
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- reg: I3C master registers
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Mandatory properties defined by the generic binding (see
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Documentation/devicetree/bindings/i3c/i3c.txt for more details):
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- #address-cells: shall be set to 1
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- #size-cells: shall be set to 0
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Optional properties defined by the generic binding (see
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Documentation/devicetree/bindings/i3c/i3c.txt for more details):
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- i2c-scl-hz
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- i3c-scl-hz
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I3C device connected on the bus follow the generic description (see
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Documentation/devicetree/bindings/i3c/i3c.txt for more details).
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Example:
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i3c-master@0d040000 {
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compatible = "cdns,i3c-master";
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clocks = <&coreclock>, <&i3csysclock>;
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clock-names = "pclk", "sysclk";
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interrupts = <3 0>;
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reg = <0x0d040000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-scl-hz = <100000>;
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nunchuk: nunchuk@52 {
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compatible = "nintendo,nunchuk";
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reg = <0x52 0x80000010 0>;
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};
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};
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Generic device tree bindings for I3C busses
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===========================================
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This document describes generic bindings that should be used to describe I3C
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busses in a device tree.
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Required properties
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-------------------
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- #address-cells - should be <3>. Read more about addresses below.
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- #size-cells - should be <0>.
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- compatible - name of the I3C master controller driving the I3C bus
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For other required properties e.g. to describe register sets,
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clocks, etc. check the binding documentation of the specific driver.
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The node describing an I3C bus should be named i3c-master.
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Optional properties
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-------------------
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These properties may not be supported by all I3C master drivers. Each I3C
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master bindings should specify which of them are supported.
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- i3c-scl-hz: frequency of the SCL signal used for I3C transfers.
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When undefined the core sets it to 12.5MHz.
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- i2c-scl-hz: frequency of the SCL signal used for I2C transfers.
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When undefined, the core looks at LVR (Legacy Virtual Register)
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values of I2C devices described in the device tree to determine
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the maximum I2C frequency.
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I2C devices
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===========
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Each I2C device connected to the bus should be described in a subnode. All
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properties described in Documentation/devicetree/bindings/i2c/i2c.txt are
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valid here, but several new properties have been added.
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New constraint on existing properties:
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--------------------------------------
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- reg: contains 3 cells
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+ first cell : still encoding the I2C address
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+ second cell: shall be 0
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+ third cell: shall encode the I3C LVR (Legacy Virtual Register)
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bit[31:8]: unused/ignored
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bit[7:5]: I2C device index. Possible values
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* 0: I2C device has a 50 ns spike filter
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* 1: I2C device does not have a 50 ns spike filter but supports high
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frequency on SCL
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* 2: I2C device does not have a 50 ns spike filter and is not tolerant
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to high frequencies
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* 3-7: reserved
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bit[4]: tell whether the device operates in FM (Fast Mode) or FM+ mode
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* 0: FM+ mode
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* 1: FM mode
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bit[3:0]: device type
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* 0-15: reserved
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The I2C node unit-address should always match the first cell of the reg
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property: <device-type>@<i2c-address>.
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I3C devices
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===========
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All I3C devices are supposed to support DAA (Dynamic Address Assignment), and
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are thus discoverable. So, by default, I3C devices do not have to be described
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in the device tree.
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This being said, one might want to attach extra resources to these devices,
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and those resources may have to be described in the device tree, which in turn
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means we have to describe I3C devices.
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Another use case for describing an I3C device in the device tree is when this
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I3C device has a static I2C address and we want to assign it a specific I3C
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dynamic address before the DAA takes place (so that other devices on the bus
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can't take this dynamic address).
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The I3C device should be names <device-type>@<static-i2c-address>,<i3c-pid>,
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where device-type is describing the type of device connected on the bus
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(gpio-controller, sensor, ...).
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Required properties
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-------------------
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- reg: contains 3 cells
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+ first cell : encodes the static I2C address. Should be 0 if the device does
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not have one (0 is not a valid I2C address).
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+ second and third cells: should encode the ProvisionalID. The second cell
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contains the manufacturer ID left-shifted by 1.
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The third cell contains ORing of the part ID
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left-shifted by 16, the instance ID left-shifted
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by 12 and the extra information. This encoding is
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following the PID definition provided by the I3C
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specification.
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Optional properties
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-------------------
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- assigned-address: dynamic address to be assigned to this device. This
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property is only valid if the I3C device has a static
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address (first cell of the reg property != 0).
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Example:
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i3c-master@d040000 {
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compatible = "cdns,i3c-master";
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clocks = <&coreclock>, <&i3csysclock>;
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clock-names = "pclk", "sysclk";
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interrupts = <3 0>;
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reg = <0x0d040000 0x1000>;
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#address-cells = <3>;
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#size-cells = <0>;
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i2c-scl-hz = <100000>;
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/* I2C device. */
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nunchuk: nunchuk@52 {
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compatible = "nintendo,nunchuk";
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reg = <0x52 0x0 0x10>;
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};
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/* I3C device with a static I2C address. */
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thermal_sensor: sensor@68,39200144004 {
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reg = <0x68 0x392 0x144004>;
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assigned-address = <0xa>;
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};
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/*
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* I3C device without a static I2C address but requiring
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* resources described in the DT.
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*/
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sensor@0,39200154004 {
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reg = <0x0 0x392 0x154004>;
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clocks = <&clock_provider 0>;
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};
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};
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@ -0,0 +1,41 @@
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Bindings for Synopsys DesignWare I3C master block
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=================================================
|
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Required properties:
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--------------------
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- compatible: shall be "snps,dw-i3c-master-1.00a"
|
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- clocks: shall reference the core_clk
|
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- interrupts: the interrupt line connected to this I3C master
|
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- reg: Offset and length of I3C master registers
|
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|
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Mandatory properties defined by the generic binding (see
|
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Documentation/devicetree/bindings/i3c/i3c.txt for more details):
|
||||
|
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- #address-cells: shall be set to 3
|
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- #size-cells: shall be set to 0
|
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|
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Optional properties defined by the generic binding (see
|
||||
Documentation/devicetree/bindings/i3c/i3c.txt for more details):
|
||||
|
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- i2c-scl-hz
|
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- i3c-scl-hz
|
||||
|
||||
I3C device connected on the bus follow the generic description (see
|
||||
Documentation/devicetree/bindings/i3c/i3c.txt for more details).
|
||||
|
||||
Example:
|
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|
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i3c-master@2000 {
|
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compatible = "snps,dw-i3c-master-1.00a";
|
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#address-cells = <3>;
|
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#size-cells = <0>;
|
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reg = <0x02000 0x1000>;
|
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interrupts = <0>;
|
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clocks = <&i3cclk>;
|
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|
||||
eeprom@57{
|
||||
compatible = "atmel,24c01";
|
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reg = <0x57 0x0 0x10>;
|
||||
pagesize = <0x8>;
|
||||
};
|
||||
};
|
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|
|
@ -0,0 +1,9 @@
|
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.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
=====================
|
||||
I3C device driver API
|
||||
=====================
|
||||
|
||||
.. kernel-doc:: include/linux/i3c/device.h
|
||||
|
||||
.. kernel-doc:: drivers/i3c/device.c
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
=============
|
||||
I3C subsystem
|
||||
=============
|
||||
|
||||
.. toctree::
|
||||
|
||||
protocol
|
||||
device-driver-api
|
||||
master-driver-api
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
================================
|
||||
I3C master controller driver API
|
||||
================================
|
||||
|
||||
.. kernel-doc:: drivers/i3c/master.c
|
||||
|
||||
.. kernel-doc:: include/linux/i3c/master.h
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
============
|
||||
I3C protocol
|
||||
============
|
||||
|
||||
Disclaimer
|
||||
==========
|
||||
|
||||
This chapter will focus on aspects that matter to software developers. For
|
||||
everything hardware related (like how things are transmitted on the bus, how
|
||||
collisions are prevented, ...) please have a look at the I3C specification.
|
||||
|
||||
This document is just a brief introduction to the I3C protocol and the concepts
|
||||
it brings to the table. If you need more information, please refer to the MIPI
|
||||
I3C specification (can be downloaded here
|
||||
http://resources.mipi.org/mipi-i3c-v1-download).
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
||||
The I3C (pronounced 'eye-three-see') is a MIPI standardized protocol designed
|
||||
to overcome I2C limitations (limited speed, external signals needed for
|
||||
interrupts, no automatic detection of the devices connected to the bus, ...)
|
||||
while remaining power-efficient.
|
||||
|
||||
I3C Bus
|
||||
=======
|
||||
|
||||
An I3C bus is made of several I3C devices and possibly some I2C devices as
|
||||
well, but let's focus on I3C devices for now.
|
||||
|
||||
An I3C device on the I3C bus can have one of the following roles:
|
||||
|
||||
* Master: the device is driving the bus. It's the one in charge of initiating
|
||||
transactions or deciding who is allowed to talk on the bus (slave generated
|
||||
events are possible in I3C, see below).
|
||||
* Slave: the device acts as a slave, and is not able to send frames to another
|
||||
slave on the bus. The device can still send events to the master on
|
||||
its own initiative if the master allowed it.
|
||||
|
||||
I3C is a multi-master protocol, so there might be several masters on a bus,
|
||||
though only one device can act as a master at a given time. In order to gain
|
||||
bus ownership, a master has to follow a specific procedure.
|
||||
|
||||
Each device on the I3C bus has to be assigned a dynamic address to be able to
|
||||
communicate. Until this is done, the device should only respond to a limited
|
||||
set of commands. If it has a static address (also called legacy I2C address),
|
||||
the device can reply to I2C transfers.
|
||||
|
||||
In addition to these per-device addresses, the protocol defines a broadcast
|
||||
address in order to address all devices on the bus.
|
||||
|
||||
Once a dynamic address has been assigned to a device, this address will be used
|
||||
for any direct communication with the device. Note that even after being
|
||||
assigned a dynamic address, the device should still process broadcast messages.
|
||||
|
||||
I3C Device discovery
|
||||
====================
|
||||
|
||||
The I3C protocol defines a mechanism to automatically discover devices present
|
||||
on the bus, their capabilities and the functionalities they provide. In this
|
||||
regard I3C is closer to a discoverable bus like USB than it is to I2C or SPI.
|
||||
|
||||
The discovery mechanism is called DAA (Dynamic Address Assignment), because it
|
||||
not only discovers devices but also assigns them a dynamic address.
|
||||
|
||||
During DAA, each I3C device reports 3 important things:
|
||||
|
||||
* BCR: Bus Characteristic Register. This 8-bit register describes the device bus
|
||||
related capabilities
|
||||
* DCR: Device Characteristic Register. This 8-bit register describes the
|
||||
functionalities provided by the device
|
||||
* Provisional ID: A 48-bit unique identifier. On a given bus there should be no
|
||||
Provisional ID collision, otherwise the discovery mechanism may fail.
|
||||
|
||||
I3C slave events
|
||||
================
|
||||
|
||||
The I3C protocol allows slaves to generate events on their own, and thus allows
|
||||
them to take temporary control of the bus.
|
||||
|
||||
This mechanism is called IBI for In Band Interrupts, and as stated in the name,
|
||||
it allows devices to generate interrupts without requiring an external signal.
|
||||
|
||||
During DAA, each device on the bus has been assigned an address, and this
|
||||
address will serve as a priority identifier to determine who wins if 2 different
|
||||
devices are generating an interrupt at the same moment on the bus (the lower the
|
||||
dynamic address the higher the priority).
|
||||
|
||||
Masters are allowed to inhibit interrupts if they want to. This inhibition
|
||||
request can be broadcast (applies to all devices) or sent to a specific
|
||||
device.
|
||||
|
||||
I3C Hot-Join
|
||||
============
|
||||
|
||||
The Hot-Join mechanism is similar to USB hotplug. This mechanism allows
|
||||
slaves to join the bus after it has been initialized by the master.
|
||||
|
||||
This covers the following use cases:
|
||||
|
||||
* the device is not powered when the bus is probed
|
||||
* the device is hotplugged on the bus through an extension board
|
||||
|
||||
This mechanism is relying on slave events to inform the master that a new
|
||||
device joined the bus and is waiting for a dynamic address.
|
||||
|
||||
The master is then free to address the request as it wishes: ignore it or
|
||||
assign a dynamic address to the slave.
|
||||
|
||||
I3C transfer types
|
||||
==================
|
||||
|
||||
If you omit SMBus (which is just a standardization on how to access registers
|
||||
exposed by I2C devices), I2C has only one transfer type.
|
||||
|
||||
I3C defines 3 different classes of transfer in addition to I2C transfers which
|
||||
are here for backward compatibility with I2C devices.
|
||||
|
||||
I3C CCC commands
|
||||
----------------
|
||||
|
||||
CCC (Common Command Code) commands are meant to be used for anything that is
|
||||
related to bus management and all features that are common to a set of devices.
|
||||
|
||||
CCC commands contain an 8-bit CCC ID describing the command that is executed.
|
||||
The MSB of this ID specifies whether this is a broadcast command (bit7 = 0) or a
|
||||
unicast one (bit7 = 1).
|
||||
|
||||
The command ID can be followed by a payload. Depending on the command, this
|
||||
payload is either sent by the master sending the command (write CCC command),
|
||||
or sent by the slave receiving the command (read CCC command). Of course, read
|
||||
accesses only apply to unicast commands.
|
||||
Note that, when sending a CCC command to a specific device, the device address
|
||||
is passed in the first byte of the payload.
|
||||
|
||||
The payload length is not explicitly passed on the bus, and should be extracted
|
||||
from the CCC ID.
|
||||
|
||||
Note that vendors can use a dedicated range of CCC IDs for their own commands
|
||||
(0x61-0x7f and 0xe0-0xef).
|
||||
|
||||
I3C Private SDR transfers
|
||||
-------------------------
|
||||
|
||||
Private SDR (Single Data Rate) transfers should be used for anything that is
|
||||
device specific and does not require high transfer speed.
|
||||
|
||||
It is the equivalent of I2C transfers but in the I3C world. Each transfer is
|
||||
passed the device address (dynamic address assigned during DAA), a payload
|
||||
and a direction.
|
||||
|
||||
The only difference with I2C is that the transfer is much faster (typical clock
|
||||
frequency is 12.5MHz).
|
||||
|
||||
I3C HDR commands
|
||||
----------------
|
||||
|
||||
HDR commands should be used for anything that is device specific and requires
|
||||
high transfer speed.
|
||||
|
||||
The first thing attached to an HDR command is the HDR mode. There are currently
|
||||
3 different modes defined by the I3C specification (refer to the specification
|
||||
for more details):
|
||||
|
||||
* HDR-DDR: Double Data Rate mode
|
||||
* HDR-TSP: Ternary Symbol Pure. Only usable on busses with no I2C devices
|
||||
* HDR-TSL: Ternary Symbol Legacy. Usable on busses with I2C devices
|
||||
|
||||
When sending an HDR command, the whole bus has to enter HDR mode, which is done
|
||||
using a broadcast CCC command.
|
||||
Once the bus has entered a specific HDR mode, the master sends the HDR command.
|
||||
An HDR command is made of:
|
||||
|
||||
* one 16-bits command word in big endian
|
||||
* N 16-bits data words in big endian
|
||||
|
||||
Those words may be wrapped with specific preambles/post-ambles which depend on
|
||||
the chosen HDR mode and are detailed here (see the specification for more
|
||||
details).
|
||||
|
||||
The 16-bits command word is made of:
|
||||
|
||||
* bit[15]: direction bit, read is 1, write is 0
|
||||
* bit[14:8]: command code. Identifies the command being executed, the amount of
|
||||
data words and their meaning
|
||||
* bit[7:1]: I3C address of the device this command is addressed to
|
||||
* bit[0]: reserved/parity-bit
|
||||
|
||||
Backward compatibility with I2C devices
|
||||
=======================================
|
||||
|
||||
The I3C protocol has been designed to be backward compatible with I2C devices.
|
||||
This backward compatibility allows one to connect a mix of I2C and I3C devices
|
||||
on the same bus, though, in order to be really efficient, I2C devices should
|
||||
be equipped with 50 ns spike filters.
|
||||
|
||||
I2C devices can't be discovered like I3C ones and have to be statically
|
||||
declared. In order to let the master know what these devices are capable of
|
||||
(both in terms of bus related limitations and functionalities), the software
|
||||
has to provide some information, which is done through the LVR (Legacy I2C
|
||||
Virtual Register).
|
||||
|
|
@ -33,6 +33,7 @@ available subsections can be seen below.
|
|||
pci/index
|
||||
spi
|
||||
i2c
|
||||
i3c/index
|
||||
hsi
|
||||
edac
|
||||
scsi
|
||||
|
|
|
|||
18
MAINTAINERS
18
MAINTAINERS
|
|
@ -7088,6 +7088,24 @@ L: linux-i2c@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/i2c/i2c-stub.c
|
||||
|
||||
I3C SUBSYSTEM
|
||||
M: Boris Brezillon <bbrezillon@kernel.org>
|
||||
L: linux-i3c@lists.infradead.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git
|
||||
S: Maintained
|
||||
F: Documentation/ABI/testing/sysfs-bus-i3c
|
||||
F: Documentation/devicetree/bindings/i3c/
|
||||
F: Documentation/driver-api/i3c
|
||||
F: drivers/i3c/
|
||||
F: include/linux/i3c/
|
||||
F: include/dt-bindings/i3c/
|
||||
|
||||
I3C DRIVER FOR SYNOPSYS DESIGNWARE
|
||||
M: Vitor Soares <vitor.soares@synopsys.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt
|
||||
F: drivers/i3c/master/dw*
|
||||
|
||||
IA64 (Itanium) PLATFORM
|
||||
M: Tony Luck <tony.luck@intel.com>
|
||||
M: Fenghua Yu <fenghua.yu@intel.com>
|
||||
|
|
|
|||
|
|
@ -57,6 +57,8 @@ source "drivers/char/Kconfig"
|
|||
|
||||
source "drivers/i2c/Kconfig"
|
||||
|
||||
source "drivers/i3c/Kconfig"
|
||||
|
||||
source "drivers/spi/Kconfig"
|
||||
|
||||
source "drivers/spmi/Kconfig"
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ obj-$(CONFIG_SERIO) += input/serio/
|
|||
obj-$(CONFIG_GAMEPORT) += input/gameport/
|
||||
obj-$(CONFIG_INPUT) += input/
|
||||
obj-$(CONFIG_RTC_LIB) += rtc/
|
||||
obj-y += i2c/ media/
|
||||
obj-y += i2c/ i3c/ media/
|
||||
obj-$(CONFIG_PPS) += pps/
|
||||
obj-y += ptp/
|
||||
obj-$(CONFIG_W1) += w1/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
menuconfig I3C
|
||||
tristate "I3C support"
|
||||
select I2C
|
||||
help
|
||||
I3C is a serial protocol standardized by the MIPI alliance.
|
||||
|
||||
It's supposed to be backward compatible with I2C while providing
|
||||
support for high speed transfers and native interrupt support
|
||||
without the need for extra pins.
|
||||
|
||||
The I3C protocol also standardizes the slave device types and is
|
||||
mainly designed to communicate with sensors.
|
||||
|
||||
If you want I3C support, you should say Y here and also to the
|
||||
specific driver for your bus adapter(s) below.
|
||||
|
||||
This I3C support can also be built as a module. If so, the module
|
||||
will be called i3c.
|
||||
|
||||
if I3C
|
||||
source "drivers/i3c/master/Kconfig"
|
||||
endif # I3C
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
i3c-y := device.o master.o
|
||||
obj-$(CONFIG_I3C) += i3c.o
|
||||
obj-$(CONFIG_I3C) += master/
|
||||
|
|
@ -0,0 +1,233 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2018 Cadence Design Systems Inc.
|
||||
*
|
||||
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
|
||||
*/
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/completion.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "internals.h"
|
||||
|
||||
/**
|
||||
* i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
|
||||
* specific device
|
||||
*
|
||||
* @dev: device with which the transfers should be done
|
||||
* @xfers: array of transfers
|
||||
* @nxfers: number of transfers
|
||||
*
|
||||
* Initiate one or several private SDR transfers with @dev.
|
||||
*
|
||||
* This function can sleep and thus cannot be called in atomic context.
|
||||
*
|
||||
* Return: 0 in case of success, a negative error core otherwise.
|
||||
*/
|
||||
int i3c_device_do_priv_xfers(struct i3c_device *dev,
|
||||
struct i3c_priv_xfer *xfers,
|
||||
int nxfers)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
if (nxfers < 1)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < nxfers; i++) {
|
||||
if (!xfers[i].len || !xfers[i].data.in)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
i3c_bus_normaluse_lock(dev->bus);
|
||||
ret = i3c_dev_do_priv_xfers_locked(dev->desc, xfers, nxfers);
|
||||
i3c_bus_normaluse_unlock(dev->bus);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);
|
||||
|
||||
/**
|
||||
* i3c_device_get_info() - get I3C device information
|
||||
*
|
||||
* @dev: device we want information on
|
||||
* @info: the information object to fill in
|
||||
*
|
||||
* Retrieve I3C dev info.
|
||||
*/
|
||||
void i3c_device_get_info(struct i3c_device *dev,
|
||||
struct i3c_device_info *info)
|
||||
{
|
||||
if (!info)
|
||||
return;
|
||||
|
||||
i3c_bus_normaluse_lock(dev->bus);
|
||||
if (dev->desc)
|
||||
*info = dev->desc->info;
|
||||
i3c_bus_normaluse_unlock(dev->bus);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3c_device_get_info);
|
||||
|
||||
/**
|
||||
* i3c_device_disable_ibi() - Disable IBIs coming from a specific device
|
||||
* @dev: device on which IBIs should be disabled
|
||||
*
|
||||
* This function disable IBIs coming from a specific device and wait for
|
||||
* all pending IBIs to be processed.
|
||||
*
|
||||
* Return: 0 in case of success, a negative error core otherwise.
|
||||
*/
|
||||
int i3c_device_disable_ibi(struct i3c_device *dev)
|
||||
{
|
||||
int ret = -ENOENT;
|
||||
|
||||
i3c_bus_normaluse_lock(dev->bus);
|
||||
if (dev->desc) {
|
||||
mutex_lock(&dev->desc->ibi_lock);
|
||||
ret = i3c_dev_disable_ibi_locked(dev->desc);
|
||||
mutex_unlock(&dev->desc->ibi_lock);
|
||||
}
|
||||
i3c_bus_normaluse_unlock(dev->bus);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3c_device_disable_ibi);
|
||||
|
||||
/**
|
||||
* i3c_device_enable_ibi() - Enable IBIs coming from a specific device
|
||||
* @dev: device on which IBIs should be enabled
|
||||
*
|
||||
* This function enable IBIs coming from a specific device and wait for
|
||||
* all pending IBIs to be processed. This should be called on a device
|
||||
* where i3c_device_request_ibi() has succeeded.
|
||||
*
|
||||
* Note that IBIs from this device might be received before this function
|
||||
* returns to its caller.
|
||||
*
|
||||
* Return: 0 in case of success, a negative error core otherwise.
|
||||
*/
|
||||
int i3c_device_enable_ibi(struct i3c_device *dev)
|
||||
{
|
||||
int ret = -ENOENT;
|
||||
|
||||
i3c_bus_normaluse_lock(dev->bus);
|
||||
if (dev->desc) {
|
||||
mutex_lock(&dev->desc->ibi_lock);
|
||||
ret = i3c_dev_enable_ibi_locked(dev->desc);
|
||||
mutex_unlock(&dev->desc->ibi_lock);
|
||||
}
|
||||
i3c_bus_normaluse_unlock(dev->bus);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3c_device_enable_ibi);
|
||||
|
||||
/**
|
||||
* i3c_device_request_ibi() - Request an IBI
|
||||
* @dev: device for which we should enable IBIs
|
||||
* @req: setup requested for this IBI
|
||||
*
|
||||
* This function is responsible for pre-allocating all resources needed to
|
||||
* process IBIs coming from @dev. When this function returns, the IBI is not
|
||||
* enabled until i3c_device_enable_ibi() is called.
|
||||
*
|
||||
* Return: 0 in case of success, a negative error core otherwise.
|
||||
*/
|
||||
int i3c_device_request_ibi(struct i3c_device *dev,
|
||||
const struct i3c_ibi_setup *req)
|
||||
{
|
||||
int ret = -ENOENT;
|
||||
|
||||
if (!req->handler || !req->num_slots)
|
||||
return -EINVAL;
|
||||
|
||||
i3c_bus_normaluse_lock(dev->bus);
|
||||
if (dev->desc) {
|
||||
mutex_lock(&dev->desc->ibi_lock);
|
||||
ret = i3c_dev_request_ibi_locked(dev->desc, req);
|
||||
mutex_unlock(&dev->desc->ibi_lock);
|
||||
}
|
||||
i3c_bus_normaluse_unlock(dev->bus);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3c_device_request_ibi);
|
||||
|
||||
/**
|
||||
* i3c_device_free_ibi() - Free all resources needed for IBI handling
|
||||
* @dev: device on which you want to release IBI resources
|
||||
*
|
||||
* This function is responsible for de-allocating resources previously
|
||||
* allocated by i3c_device_request_ibi(). It should be called after disabling
|
||||
* IBIs with i3c_device_disable_ibi().
|
||||
*/
|
||||
void i3c_device_free_ibi(struct i3c_device *dev)
|
||||
{
|
||||
i3c_bus_normaluse_lock(dev->bus);
|
||||
if (dev->desc) {
|
||||
mutex_lock(&dev->desc->ibi_lock);
|
||||
i3c_dev_free_ibi_locked(dev->desc);
|
||||
mutex_unlock(&dev->desc->ibi_lock);
|
||||
}
|
||||
i3c_bus_normaluse_unlock(dev->bus);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3c_device_free_ibi);
|
||||
|
||||
/**
|
||||
* i3cdev_to_dev() - Returns the device embedded in @i3cdev
|
||||
* @i3cdev: I3C device
|
||||
*
|
||||
* Return: a pointer to a device object.
|
||||
*/
|
||||
struct device *i3cdev_to_dev(struct i3c_device *i3cdev)
|
||||
{
|
||||
return &i3cdev->dev;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3cdev_to_dev);
|
||||
|
||||
/**
|
||||
* dev_to_i3cdev() - Returns the I3C device containing @dev
|
||||
* @dev: device object
|
||||
*
|
||||
* Return: a pointer to an I3C device object.
|
||||
*/
|
||||
struct i3c_device *dev_to_i3cdev(struct device *dev)
|
||||
{
|
||||
return container_of(dev, struct i3c_device, dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dev_to_i3cdev);
|
||||
|
||||
/**
|
||||
* i3c_driver_register_with_owner() - register an I3C device driver
|
||||
*
|
||||
* @drv: driver to register
|
||||
* @owner: module that owns this driver
|
||||
*
|
||||
* Register @drv to the core.
|
||||
*
|
||||
* Return: 0 in case of success, a negative error core otherwise.
|
||||
*/
|
||||
int i3c_driver_register_with_owner(struct i3c_driver *drv, struct module *owner)
|
||||
{
|
||||
drv->driver.owner = owner;
|
||||
drv->driver.bus = &i3c_bus_type;
|
||||
|
||||
return driver_register(&drv->driver);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3c_driver_register_with_owner);
|
||||
|
||||
/**
|
||||
* i3c_driver_unregister() - unregister an I3C device driver
|
||||
*
|
||||
* @drv: driver to unregister
|
||||
*
|
||||
* Unregister @drv.
|
||||
*/
|
||||
void i3c_driver_unregister(struct i3c_driver *drv)
|
||||
{
|
||||
driver_unregister(&drv->driver);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(i3c_driver_unregister);
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Cadence Design Systems Inc.
|
||||
*
|
||||
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
|
||||
*/
|
||||
|
||||
#ifndef I3C_INTERNALS_H
|
||||
#define I3C_INTERNALS_H
|
||||
|
||||
#include <linux/i3c/master.h>
|
||||
|
||||
extern struct bus_type i3c_bus_type;
|
||||
|
||||
void i3c_bus_normaluse_lock(struct i3c_bus *bus);
|
||||
void i3c_bus_normaluse_unlock(struct i3c_bus *bus);
|
||||
|
||||
int i3c_dev_do_priv_xfers_locked(struct i3c_dev_desc *dev,
|
||||
struct i3c_priv_xfer *xfers,
|
||||
int nxfers);
|
||||
int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev);
|
||||
int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev);
|
||||
int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
|
||||
const struct i3c_ibi_setup *req);
|
||||
void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev);
|
||||
#endif /* I3C_INTERNAL_H */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,22 @@
|
|||
config CDNS_I3C_MASTER
|
||||
tristate "Cadence I3C master driver"
|
||||
depends on I3C
|
||||
depends on HAS_IOMEM
|
||||
depends on !(ALPHA || PARISC)
|
||||
help
|
||||
Enable this driver if you want to support Cadence I3C master block.
|
||||
|
||||
config DW_I3C_MASTER
|
||||
tristate "Synospsys DesignWare I3C master driver"
|
||||
depends on I3C
|
||||
depends on HAS_IOMEM
|
||||
depends on !(ALPHA || PARISC)
|
||||
# ALPHA and PARISC needs {read,write}sl()
|
||||
help
|
||||
Support for Synopsys DesignWare MIPI I3C Controller.
|
||||
|
||||
For details please see
|
||||
https://www.synopsys.com/dw/ipdir.php?ds=mipi_i3c
|
||||
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called dw-i3c-master.
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
obj-$(CONFIG_CDNS_I3C_MASTER) += i3c-master-cdns.o
|
||||
obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,385 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Cadence Design Systems Inc.
|
||||
*
|
||||
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
|
||||
*/
|
||||
|
||||
#ifndef I3C_CCC_H
|
||||
#define I3C_CCC_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/i3c/device.h>
|
||||
|
||||
/* I3C CCC (Common Command Codes) related definitions */
|
||||
#define I3C_CCC_DIRECT BIT(7)
|
||||
|
||||
#define I3C_CCC_ID(id, broadcast) \
|
||||
((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT))
|
||||
|
||||
/* Commands valid in both broadcast and unicast modes */
|
||||
#define I3C_CCC_ENEC(broadcast) I3C_CCC_ID(0x0, broadcast)
|
||||
#define I3C_CCC_DISEC(broadcast) I3C_CCC_ID(0x1, broadcast)
|
||||
#define I3C_CCC_ENTAS(as, broadcast) I3C_CCC_ID(0x2 + (as), broadcast)
|
||||
#define I3C_CCC_RSTDAA(broadcast) I3C_CCC_ID(0x6, broadcast)
|
||||
#define I3C_CCC_SETMWL(broadcast) I3C_CCC_ID(0x9, broadcast)
|
||||
#define I3C_CCC_SETMRL(broadcast) I3C_CCC_ID(0xa, broadcast)
|
||||
#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28 : 0x98)
|
||||
#define I3C_CCC_VENDOR(id, broadcast) ((id) + ((broadcast) ? 0x61 : 0xe0))
|
||||
|
||||
/* Broadcast-only commands */
|
||||
#define I3C_CCC_ENTDAA I3C_CCC_ID(0x7, true)
|
||||
#define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true)
|
||||
#define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true)
|
||||
#define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true)
|
||||
|
||||
/* Unicast-only commands */
|
||||
#define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false)
|
||||
#define I3C_CCC_SETNEWDA I3C_CCC_ID(0x8, false)
|
||||
#define I3C_CCC_GETMWL I3C_CCC_ID(0xb, false)
|
||||
#define I3C_CCC_GETMRL I3C_CCC_ID(0xc, false)
|
||||
#define I3C_CCC_GETPID I3C_CCC_ID(0xd, false)
|
||||
#define I3C_CCC_GETBCR I3C_CCC_ID(0xe, false)
|
||||
#define I3C_CCC_GETDCR I3C_CCC_ID(0xf, false)
|
||||
#define I3C_CCC_GETSTATUS I3C_CCC_ID(0x10, false)
|
||||
#define I3C_CCC_GETACCMST I3C_CCC_ID(0x11, false)
|
||||
#define I3C_CCC_SETBRGTGT I3C_CCC_ID(0x13, false)
|
||||
#define I3C_CCC_GETMXDS I3C_CCC_ID(0x14, false)
|
||||
#define I3C_CCC_GETHDRCAP I3C_CCC_ID(0x15, false)
|
||||
#define I3C_CCC_GETXTIME I3C_CCC_ID(0x19, false)
|
||||
|
||||
#define I3C_CCC_EVENT_SIR BIT(0)
|
||||
#define I3C_CCC_EVENT_MR BIT(1)
|
||||
#define I3C_CCC_EVENT_HJ BIT(3)
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_events - payload passed to ENEC/DISEC CCC
|
||||
*
|
||||
* @events: bitmask of I3C_CCC_EVENT_xxx events.
|
||||
*
|
||||
* Depending on the CCC command, the specific events coming from all devices
|
||||
* (broadcast version) or a specific device (unicast version) will be
|
||||
* enabled (ENEC) or disabled (DISEC).
|
||||
*/
|
||||
struct i3c_ccc_events {
|
||||
u8 events;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_mwl - payload passed to SETMWL/GETMWL CCC
|
||||
*
|
||||
* @len: maximum write length in bytes
|
||||
*
|
||||
* The maximum write length is only applicable to SDR private messages or
|
||||
* extended Write CCCs (like SETXTIME).
|
||||
*/
|
||||
struct i3c_ccc_mwl {
|
||||
__be16 len;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_mrl - payload passed to SETMRL/GETMRL CCC
|
||||
*
|
||||
* @len: maximum read length in bytes
|
||||
* @ibi_len: maximum IBI payload length
|
||||
*
|
||||
* The maximum read length is only applicable to SDR private messages or
|
||||
* extended Read CCCs (like GETXTIME).
|
||||
* The IBI length is only valid if the I3C slave is IBI capable
|
||||
* (%I3C_BCR_IBI_REQ_CAP is set).
|
||||
*/
|
||||
struct i3c_ccc_mrl {
|
||||
__be16 read_len;
|
||||
u8 ibi_len;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_dev_desc - I3C/I2C device descriptor used for DEFSLVS
|
||||
*
|
||||
* @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is
|
||||
* describing an I2C slave.
|
||||
* @dcr: DCR value (not applicable to entries describing I2C devices)
|
||||
* @lvr: LVR value (not applicable to entries describing I3C devices)
|
||||
* @bcr: BCR value or 0 if this entry is describing an I2C slave
|
||||
* @static_addr: static address or 0 if the device does not have a static
|
||||
* address
|
||||
*
|
||||
* The DEFSLVS command should be passed an array of i3c_ccc_dev_desc
|
||||
* descriptors (one entry per I3C/I2C dev controlled by the master).
|
||||
*/
|
||||
struct i3c_ccc_dev_desc {
|
||||
u8 dyn_addr;
|
||||
union {
|
||||
u8 dcr;
|
||||
u8 lvr;
|
||||
};
|
||||
u8 bcr;
|
||||
u8 static_addr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_defslvs - payload passed to DEFSLVS CCC
|
||||
*
|
||||
* @count: number of dev descriptors
|
||||
* @master: descriptor describing the current master
|
||||
* @slaves: array of descriptors describing slaves controlled by the
|
||||
* current master
|
||||
*
|
||||
* Information passed to the broadcast DEFSLVS to propagate device
|
||||
* information to all masters currently acting as slaves on the bus.
|
||||
* This is only meaningful if you have more than one master.
|
||||
*/
|
||||
struct i3c_ccc_defslvs {
|
||||
u8 count;
|
||||
struct i3c_ccc_dev_desc master;
|
||||
struct i3c_ccc_dev_desc slaves[0];
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* enum i3c_ccc_test_mode - enum listing all available test modes
|
||||
*
|
||||
* @I3C_CCC_EXIT_TEST_MODE: exit test mode
|
||||
* @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
|
||||
*/
|
||||
enum i3c_ccc_test_mode {
|
||||
I3C_CCC_EXIT_TEST_MODE,
|
||||
I3C_CCC_VENDOR_TEST_MODE,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_enttm - payload passed to ENTTM CCC
|
||||
*
|
||||
* @mode: one of the &enum i3c_ccc_test_mode modes
|
||||
*
|
||||
* Information passed to the ENTTM CCC to instruct an I3C device to enter a
|
||||
* specific test mode.
|
||||
*/
|
||||
struct i3c_ccc_enttm {
|
||||
u8 mode;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_setda - payload passed to SETNEWDA and SETDASA CCCs
|
||||
*
|
||||
* @addr: dynamic address to assign to an I3C device
|
||||
*
|
||||
* Information passed to the SETNEWDA and SETDASA CCCs to assign/change the
|
||||
* dynamic address of an I3C device.
|
||||
*/
|
||||
struct i3c_ccc_setda {
|
||||
u8 addr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_getpid - payload passed to GETPID CCC
|
||||
*
|
||||
* @pid: 48 bits PID in big endian
|
||||
*/
|
||||
struct i3c_ccc_getpid {
|
||||
u8 pid[6];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_getbcr - payload passed to GETBCR CCC
|
||||
*
|
||||
* @bcr: BCR (Bus Characteristic Register) value
|
||||
*/
|
||||
struct i3c_ccc_getbcr {
|
||||
u8 bcr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_getdcr - payload passed to GETDCR CCC
|
||||
*
|
||||
* @dcr: DCR (Device Characteristic Register) value
|
||||
*/
|
||||
struct i3c_ccc_getdcr {
|
||||
u8 dcr;
|
||||
};
|
||||
|
||||
#define I3C_CCC_STATUS_PENDING_INT(status) ((status) & GENMASK(3, 0))
|
||||
#define I3C_CCC_STATUS_PROTOCOL_ERROR BIT(5)
|
||||
#define I3C_CCC_STATUS_ACTIVITY_MODE(status) \
|
||||
(((status) & GENMASK(7, 6)) >> 6)
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_getstatus - payload passed to GETSTATUS CCC
|
||||
*
|
||||
* @status: status of the I3C slave (see I3C_CCC_STATUS_xxx macros for more
|
||||
* information).
|
||||
*/
|
||||
struct i3c_ccc_getstatus {
|
||||
__be16 status;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_getaccmst - payload passed to GETACCMST CCC
|
||||
*
|
||||
* @newmaster: address of the master taking bus ownership
|
||||
*/
|
||||
struct i3c_ccc_getaccmst {
|
||||
u8 newmaster;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_bridged_slave_desc - bridged slave descriptor
|
||||
*
|
||||
* @addr: dynamic address of the bridged device
|
||||
* @id: ID of the slave device behind the bridge
|
||||
*/
|
||||
struct i3c_ccc_bridged_slave_desc {
|
||||
u8 addr;
|
||||
__be16 id;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_setbrgtgt - payload passed to SETBRGTGT CCC
|
||||
*
|
||||
* @count: number of bridged slaves
|
||||
* @bslaves: bridged slave descriptors
|
||||
*/
|
||||
struct i3c_ccc_setbrgtgt {
|
||||
u8 count;
|
||||
struct i3c_ccc_bridged_slave_desc bslaves[0];
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
|
||||
*/
|
||||
enum i3c_sdr_max_data_rate {
|
||||
I3C_SDR0_FSCL_MAX,
|
||||
I3C_SDR1_FSCL_8MHZ,
|
||||
I3C_SDR2_FSCL_6MHZ,
|
||||
I3C_SDR3_FSCL_4MHZ,
|
||||
I3C_SDR4_FSCL_2MHZ,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum i3c_tsco - clock to data turn-around
|
||||
*/
|
||||
enum i3c_tsco {
|
||||
I3C_TSCO_8NS,
|
||||
I3C_TSCO_9NS,
|
||||
I3C_TSCO_10NS,
|
||||
I3C_TSCO_11NS,
|
||||
I3C_TSCO_12NS,
|
||||
};
|
||||
|
||||
#define I3C_CCC_MAX_SDR_FSCL_MASK GENMASK(2, 0)
|
||||
#define I3C_CCC_MAX_SDR_FSCL(x) ((x) & I3C_CCC_MAX_SDR_FSCL_MASK)
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_getmxds - payload passed to GETMXDS CCC
|
||||
*
|
||||
* @maxwr: write limitations
|
||||
* @maxrd: read limitations
|
||||
* @maxrdturn: maximum read turn-around expressed micro-seconds and
|
||||
* little-endian formatted
|
||||
*/
|
||||
struct i3c_ccc_getmxds {
|
||||
u8 maxwr;
|
||||
u8 maxrd;
|
||||
u8 maxrdturn[3];
|
||||
} __packed;
|
||||
|
||||
#define I3C_CCC_HDR_MODE(mode) BIT(mode)
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_gethdrcap - payload passed to GETHDRCAP CCC
|
||||
*
|
||||
* @modes: bitmap of supported HDR modes
|
||||
*/
|
||||
struct i3c_ccc_gethdrcap {
|
||||
u8 modes;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* enum i3c_ccc_setxtime_subcmd - SETXTIME sub-commands
|
||||
*/
|
||||
enum i3c_ccc_setxtime_subcmd {
|
||||
I3C_CCC_SETXTIME_ST = 0x7f,
|
||||
I3C_CCC_SETXTIME_DT = 0xbf,
|
||||
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE0 = 0xdf,
|
||||
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE1 = 0xef,
|
||||
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE2 = 0xf7,
|
||||
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE3 = 0xfb,
|
||||
I3C_CCC_SETXTIME_ASYNC_TRIGGER = 0xfd,
|
||||
I3C_CCC_SETXTIME_TPH = 0x3f,
|
||||
I3C_CCC_SETXTIME_TU = 0x9f,
|
||||
I3C_CCC_SETXTIME_ODR = 0x8f,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_setxtime - payload passed to SETXTIME CCC
|
||||
*
|
||||
* @subcmd: one of the sub-commands ddefined in &enum i3c_ccc_setxtime_subcmd
|
||||
* @data: sub-command payload. Amount of data is determined by
|
||||
* &i3c_ccc_setxtime->subcmd
|
||||
*/
|
||||
struct i3c_ccc_setxtime {
|
||||
u8 subcmd;
|
||||
u8 data[0];
|
||||
} __packed;
|
||||
|
||||
#define I3C_CCC_GETXTIME_SYNC_MODE BIT(0)
|
||||
#define I3C_CCC_GETXTIME_ASYNC_MODE(x) BIT((x) + 1)
|
||||
#define I3C_CCC_GETXTIME_OVERFLOW BIT(7)
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_getxtime - payload retrieved from GETXTIME CCC
|
||||
*
|
||||
* @supported_modes: bitmap describing supported XTIME modes
|
||||
* @state: current status (enabled mode and overflow status)
|
||||
* @frequency: slave's internal oscillator frequency in 500KHz steps
|
||||
* @inaccuracy: slave's internal oscillator inaccuracy in 0.1% steps
|
||||
*/
|
||||
struct i3c_ccc_getxtime {
|
||||
u8 supported_modes;
|
||||
u8 state;
|
||||
u8 frequency;
|
||||
u8 inaccuracy;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_cmd_payload - CCC payload
|
||||
*
|
||||
* @len: payload length
|
||||
* @data: payload data. This buffer must be DMA-able
|
||||
*/
|
||||
struct i3c_ccc_cmd_payload {
|
||||
u16 len;
|
||||
void *data;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_cmd_dest - CCC command destination
|
||||
*
|
||||
* @addr: can be an I3C device address or the broadcast address if this is a
|
||||
* broadcast CCC
|
||||
* @payload: payload to be sent to this device or broadcasted
|
||||
*/
|
||||
struct i3c_ccc_cmd_dest {
|
||||
u8 addr;
|
||||
struct i3c_ccc_cmd_payload payload;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ccc_cmd - CCC command
|
||||
*
|
||||
* @rnw: true if the CCC should retrieve data from the device. Only valid for
|
||||
* unicast commands
|
||||
* @id: CCC command id
|
||||
* @ndests: number of destinations. Should always be one for broadcast commands
|
||||
* @dests: array of destinations and associated payload for this CCC. Most of
|
||||
* the time, only one destination is provided
|
||||
* @err: I3C error code
|
||||
*/
|
||||
struct i3c_ccc_cmd {
|
||||
u8 rnw;
|
||||
u8 id;
|
||||
unsigned int ndests;
|
||||
struct i3c_ccc_cmd_dest *dests;
|
||||
enum i3c_error_code err;
|
||||
};
|
||||
|
||||
#endif /* I3C_CCC_H */
|
||||
|
|
@ -0,0 +1,331 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Cadence Design Systems Inc.
|
||||
*
|
||||
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
|
||||
*/
|
||||
|
||||
#ifndef I3C_DEV_H
|
||||
#define I3C_DEV_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/kconfig.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
/**
|
||||
* enum i3c_error_code - I3C error codes
|
||||
*
|
||||
* These are the standard error codes as defined by the I3C specification.
|
||||
* When -EIO is returned by the i3c_device_do_priv_xfers() or
|
||||
* i3c_device_send_hdr_cmds() one can check the error code in
|
||||
* &struct_i3c_priv_xfer.err or &struct i3c_hdr_cmd.err to get a better idea of
|
||||
* what went wrong.
|
||||
*
|
||||
* @I3C_ERROR_UNKNOWN: unknown error, usually means the error is not I3C
|
||||
* related
|
||||
* @I3C_ERROR_M0: M0 error
|
||||
* @I3C_ERROR_M1: M1 error
|
||||
* @I3C_ERROR_M2: M2 error
|
||||
*/
|
||||
enum i3c_error_code {
|
||||
I3C_ERROR_UNKNOWN = 0,
|
||||
I3C_ERROR_M0 = 1,
|
||||
I3C_ERROR_M1,
|
||||
I3C_ERROR_M2,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum i3c_hdr_mode - HDR mode ids
|
||||
* @I3C_HDR_DDR: DDR mode
|
||||
* @I3C_HDR_TSP: TSP mode
|
||||
* @I3C_HDR_TSL: TSL mode
|
||||
*/
|
||||
enum i3c_hdr_mode {
|
||||
I3C_HDR_DDR,
|
||||
I3C_HDR_TSP,
|
||||
I3C_HDR_TSL,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_priv_xfer - I3C SDR private transfer
|
||||
* @rnw: encodes the transfer direction. true for a read, false for a write
|
||||
* @len: transfer length in bytes of the transfer
|
||||
* @data: input/output buffer
|
||||
* @data.in: input buffer. Must point to a DMA-able buffer
|
||||
* @data.out: output buffer. Must point to a DMA-able buffer
|
||||
* @err: I3C error code
|
||||
*/
|
||||
struct i3c_priv_xfer {
|
||||
u8 rnw;
|
||||
u16 len;
|
||||
union {
|
||||
void *in;
|
||||
const void *out;
|
||||
} data;
|
||||
enum i3c_error_code err;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum i3c_dcr - I3C DCR values
|
||||
* @I3C_DCR_GENERIC_DEVICE: generic I3C device
|
||||
*/
|
||||
enum i3c_dcr {
|
||||
I3C_DCR_GENERIC_DEVICE = 0,
|
||||
};
|
||||
|
||||
#define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33)
|
||||
#define I3C_PID_RND_LOWER_32BITS(pid) (!!((pid) & BIT_ULL(32)))
|
||||
#define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0))
|
||||
#define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16)
|
||||
#define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12)
|
||||
#define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))
|
||||
|
||||
#define I3C_BCR_DEVICE_ROLE(bcr) ((bcr) & GENMASK(7, 6))
|
||||
#define I3C_BCR_I3C_SLAVE (0 << 6)
|
||||
#define I3C_BCR_I3C_MASTER (1 << 6)
|
||||
#define I3C_BCR_HDR_CAP BIT(5)
|
||||
#define I3C_BCR_BRIDGE BIT(4)
|
||||
#define I3C_BCR_OFFLINE_CAP BIT(3)
|
||||
#define I3C_BCR_IBI_PAYLOAD BIT(2)
|
||||
#define I3C_BCR_IBI_REQ_CAP BIT(1)
|
||||
#define I3C_BCR_MAX_DATA_SPEED_LIM BIT(0)
|
||||
|
||||
/**
|
||||
* struct i3c_device_info - I3C device information
|
||||
* @pid: Provisional ID
|
||||
* @bcr: Bus Characteristic Register
|
||||
* @dcr: Device Characteristic Register
|
||||
* @static_addr: static/I2C address
|
||||
* @dyn_addr: dynamic address
|
||||
* @hdr_cap: supported HDR modes
|
||||
* @max_read_ds: max read speed information
|
||||
* @max_write_ds: max write speed information
|
||||
* @max_ibi_len: max IBI payload length
|
||||
* @max_read_turnaround: max read turn-around time in micro-seconds
|
||||
* @max_read_len: max private SDR read length in bytes
|
||||
* @max_write_len: max private SDR write length in bytes
|
||||
*
|
||||
* These are all basic information that should be advertised by an I3C device.
|
||||
* Some of them are optional depending on the device type and device
|
||||
* capabilities.
|
||||
* For each I3C slave attached to a master with
|
||||
* i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
|
||||
* to retrieve these data.
|
||||
*/
|
||||
struct i3c_device_info {
|
||||
u64 pid;
|
||||
u8 bcr;
|
||||
u8 dcr;
|
||||
u8 static_addr;
|
||||
u8 dyn_addr;
|
||||
u8 hdr_cap;
|
||||
u8 max_read_ds;
|
||||
u8 max_write_ds;
|
||||
u8 max_ibi_len;
|
||||
u32 max_read_turnaround;
|
||||
u16 max_read_len;
|
||||
u16 max_write_len;
|
||||
};
|
||||
|
||||
/*
|
||||
* I3C device internals are kept hidden from I3C device users. It's just
|
||||
* simpler to refactor things when everything goes through getter/setters, and
|
||||
* I3C device drivers should not have to worry about internal representation
|
||||
* anyway.
|
||||
*/
|
||||
struct i3c_device;
|
||||
|
||||
/* These macros should be used to i3c_device_id entries. */
|
||||
#define I3C_MATCH_MANUF_AND_PART (I3C_MATCH_MANUF | I3C_MATCH_PART)
|
||||
|
||||
#define I3C_DEVICE(_manufid, _partid, _drvdata) \
|
||||
{ \
|
||||
.match_flags = I3C_MATCH_MANUF_AND_PART, \
|
||||
.manuf_id = _manufid, \
|
||||
.part_id = _partid, \
|
||||
.data = _drvdata, \
|
||||
}
|
||||
|
||||
#define I3C_DEVICE_EXTRA_INFO(_manufid, _partid, _info, _drvdata) \
|
||||
{ \
|
||||
.match_flags = I3C_MATCH_MANUF_AND_PART | \
|
||||
I3C_MATCH_EXTRA_INFO, \
|
||||
.manuf_id = _manufid, \
|
||||
.part_id = _partid, \
|
||||
.extra_info = _info, \
|
||||
.data = _drvdata, \
|
||||
}
|
||||
|
||||
#define I3C_CLASS(_dcr, _drvdata) \
|
||||
{ \
|
||||
.match_flags = I3C_MATCH_DCR, \
|
||||
.dcr = _dcr, \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct i3c_driver - I3C device driver
|
||||
* @driver: inherit from device_driver
|
||||
* @probe: I3C device probe method
|
||||
* @remove: I3C device remove method
|
||||
* @id_table: I3C device match table. Will be used by the framework to decide
|
||||
* which device to bind to this driver
|
||||
*/
|
||||
struct i3c_driver {
|
||||
struct device_driver driver;
|
||||
int (*probe)(struct i3c_device *dev);
|
||||
int (*remove)(struct i3c_device *dev);
|
||||
const struct i3c_device_id *id_table;
|
||||
};
|
||||
|
||||
static inline struct i3c_driver *drv_to_i3cdrv(struct device_driver *drv)
|
||||
{
|
||||
return container_of(drv, struct i3c_driver, driver);
|
||||
}
|
||||
|
||||
struct device *i3cdev_to_dev(struct i3c_device *i3cdev);
|
||||
struct i3c_device *dev_to_i3cdev(struct device *dev);
|
||||
|
||||
static inline void i3cdev_set_drvdata(struct i3c_device *i3cdev,
|
||||
void *data)
|
||||
{
|
||||
struct device *dev = i3cdev_to_dev(i3cdev);
|
||||
|
||||
dev_set_drvdata(dev, data);
|
||||
}
|
||||
|
||||
static inline void *i3cdev_get_drvdata(struct i3c_device *i3cdev)
|
||||
{
|
||||
struct device *dev = i3cdev_to_dev(i3cdev);
|
||||
|
||||
return dev_get_drvdata(dev);
|
||||
}
|
||||
|
||||
int i3c_driver_register_with_owner(struct i3c_driver *drv,
|
||||
struct module *owner);
|
||||
void i3c_driver_unregister(struct i3c_driver *drv);
|
||||
|
||||
#define i3c_driver_register(__drv) \
|
||||
i3c_driver_register_with_owner(__drv, THIS_MODULE)
|
||||
|
||||
/**
|
||||
* module_i3c_driver() - Register a module providing an I3C driver
|
||||
* @__drv: the I3C driver to register
|
||||
*
|
||||
* Provide generic init/exit functions that simply register/unregister an I3C
|
||||
* driver.
|
||||
* Should be used by any driver that does not require extra init/cleanup steps.
|
||||
*/
|
||||
#define module_i3c_driver(__drv) \
|
||||
module_driver(__drv, i3c_driver_register, i3c_driver_unregister)
|
||||
|
||||
/**
|
||||
* i3c_i2c_driver_register() - Register an i2c and an i3c driver
|
||||
* @i3cdrv: the I3C driver to register
|
||||
* @i2cdrv: the I2C driver to register
|
||||
*
|
||||
* This function registers both @i2cdev and @i3cdev, and fails if one of these
|
||||
* registrations fails. This is mainly useful for devices that support both I2C
|
||||
* and I3C modes.
|
||||
* Note that when CONFIG_I3C is not enabled, this function only registers the
|
||||
* I2C driver.
|
||||
*
|
||||
* Return: 0 if both registrations succeeds, a negative error code otherwise.
|
||||
*/
|
||||
static inline int i3c_i2c_driver_register(struct i3c_driver *i3cdrv,
|
||||
struct i2c_driver *i2cdrv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = i2c_add_driver(i2cdrv);
|
||||
if (ret || !IS_ENABLED(CONFIG_I3C))
|
||||
return ret;
|
||||
|
||||
ret = i3c_driver_register(i3cdrv);
|
||||
if (ret)
|
||||
i2c_del_driver(i2cdrv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* i3c_i2c_driver_unregister() - Unregister an i2c and an i3c driver
|
||||
* @i3cdrv: the I3C driver to register
|
||||
* @i2cdrv: the I2C driver to register
|
||||
*
|
||||
* This function unregisters both @i3cdrv and @i2cdrv.
|
||||
* Note that when CONFIG_I3C is not enabled, this function only unregisters the
|
||||
* @i2cdrv.
|
||||
*/
|
||||
static inline void i3c_i2c_driver_unregister(struct i3c_driver *i3cdrv,
|
||||
struct i2c_driver *i2cdrv)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_I3C))
|
||||
i3c_driver_unregister(i3cdrv);
|
||||
|
||||
i2c_del_driver(i2cdrv);
|
||||
}
|
||||
|
||||
/**
|
||||
* module_i3c_i2c_driver() - Register a module providing an I3C and an I2C
|
||||
* driver
|
||||
* @__i3cdrv: the I3C driver to register
|
||||
* @__i2cdrv: the I3C driver to register
|
||||
*
|
||||
* Provide generic init/exit functions that simply register/unregister an I3C
|
||||
* and an I2C driver.
|
||||
* This macro can be used even if CONFIG_I3C is disabled, in this case, only
|
||||
* the I2C driver will be registered.
|
||||
* Should be used by any driver that does not require extra init/cleanup steps.
|
||||
*/
|
||||
#define module_i3c_i2c_driver(__i3cdrv, __i2cdrv) \
|
||||
module_driver(__i3cdrv, \
|
||||
i3c_i2c_driver_register, \
|
||||
i3c_i2c_driver_unregister)
|
||||
|
||||
int i3c_device_do_priv_xfers(struct i3c_device *dev,
|
||||
struct i3c_priv_xfer *xfers,
|
||||
int nxfers);
|
||||
|
||||
void i3c_device_get_info(struct i3c_device *dev, struct i3c_device_info *info);
|
||||
|
||||
struct i3c_ibi_payload {
|
||||
unsigned int len;
|
||||
const void *data;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ibi_setup - IBI setup object
|
||||
* @max_payload_len: maximum length of the payload associated to an IBI. If one
|
||||
* IBI appears to have a payload that is bigger than this
|
||||
* number, the IBI will be rejected.
|
||||
* @num_slots: number of pre-allocated IBI slots. This should be chosen so that
|
||||
* the system never runs out of IBI slots, otherwise you'll lose
|
||||
* IBIs.
|
||||
* @handler: IBI handler, every time an IBI is received. This handler is called
|
||||
* in a workqueue context. It is allowed to sleep and send new
|
||||
* messages on the bus, though it's recommended to keep the
|
||||
* processing done there as fast as possible to avoid delaying
|
||||
* processing of other queued on the same workqueue.
|
||||
*
|
||||
* Temporary structure used to pass information to i3c_device_request_ibi().
|
||||
* This object can be allocated on the stack since i3c_device_request_ibi()
|
||||
* copies every bit of information and do not use it after
|
||||
* i3c_device_request_ibi() has returned.
|
||||
*/
|
||||
struct i3c_ibi_setup {
|
||||
unsigned int max_payload_len;
|
||||
unsigned int num_slots;
|
||||
void (*handler)(struct i3c_device *dev,
|
||||
const struct i3c_ibi_payload *payload);
|
||||
};
|
||||
|
||||
int i3c_device_request_ibi(struct i3c_device *dev,
|
||||
const struct i3c_ibi_setup *setup);
|
||||
void i3c_device_free_ibi(struct i3c_device *dev);
|
||||
int i3c_device_enable_ibi(struct i3c_device *dev);
|
||||
int i3c_device_disable_ibi(struct i3c_device *dev);
|
||||
|
||||
#endif /* I3C_DEV_H */
|
||||
|
|
@ -0,0 +1,648 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Cadence Design Systems Inc.
|
||||
*
|
||||
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
|
||||
*/
|
||||
|
||||
#ifndef I3C_MASTER_H
|
||||
#define I3C_MASTER_H
|
||||
|
||||
#include <asm/bitsperlong.h>
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i3c/ccc.h>
|
||||
#include <linux/i3c/device.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#define I3C_HOT_JOIN_ADDR 0x2
|
||||
#define I3C_BROADCAST_ADDR 0x7e
|
||||
#define I3C_MAX_ADDR GENMASK(6, 0)
|
||||
|
||||
struct i3c_master_controller;
|
||||
struct i3c_bus;
|
||||
struct i2c_device;
|
||||
struct i3c_device;
|
||||
|
||||
/**
|
||||
* struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor
|
||||
* @node: node element used to insert the slot into the I2C or I3C device
|
||||
* list
|
||||
* @master: I3C master that instantiated this device. Will be used to do
|
||||
* I2C/I3C transfers
|
||||
* @master_priv: master private data assigned to the device. Can be used to
|
||||
* add master specific information
|
||||
*
|
||||
* This structure is describing common I3C/I2C dev information.
|
||||
*/
|
||||
struct i3c_i2c_dev_desc {
|
||||
struct list_head node;
|
||||
struct i3c_master_controller *master;
|
||||
void *master_priv;
|
||||
};
|
||||
|
||||
#define I3C_LVR_I2C_INDEX_MASK GENMASK(7, 5)
|
||||
#define I3C_LVR_I2C_INDEX(x) ((x) << 5)
|
||||
#define I3C_LVR_I2C_FM_MODE BIT(4)
|
||||
|
||||
#define I2C_MAX_ADDR GENMASK(9, 0)
|
||||
|
||||
/**
|
||||
* struct i2c_dev_boardinfo - I2C device board information
|
||||
* @node: used to insert the boardinfo object in the I2C boardinfo list
|
||||
* @base: regular I2C board information
|
||||
* @lvr: LVR (Legacy Virtual Register) needed by the I3C core to know about
|
||||
* the I2C device limitations
|
||||
*
|
||||
* This structure is used to attach board-level information to an I2C device.
|
||||
* Each I2C device connected on the I3C bus should have one.
|
||||
*/
|
||||
struct i2c_dev_boardinfo {
|
||||
struct list_head node;
|
||||
struct i2c_board_info base;
|
||||
u8 lvr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i2c_dev_desc - I2C device descriptor
|
||||
* @common: common part of the I2C device descriptor
|
||||
* @boardinfo: pointer to the boardinfo attached to this I2C device
|
||||
* @dev: I2C device object registered to the I2C framework
|
||||
*
|
||||
* Each I2C device connected on the bus will have an i2c_dev_desc.
|
||||
* This object is created by the core and later attached to the controller
|
||||
* using &struct_i3c_master_controller->ops->attach_i2c_dev().
|
||||
*
|
||||
* &struct_i2c_dev_desc is the internal representation of an I2C device
|
||||
* connected on an I3C bus. This object is also passed to all
|
||||
* &struct_i3c_master_controller_ops hooks.
|
||||
*/
|
||||
struct i2c_dev_desc {
|
||||
struct i3c_i2c_dev_desc common;
|
||||
const struct i2c_dev_boardinfo *boardinfo;
|
||||
struct i2c_client *dev;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_ibi_slot - I3C IBI (In-Band Interrupt) slot
|
||||
* @work: work associated to this slot. The IBI handler will be called from
|
||||
* there
|
||||
* @dev: the I3C device that has generated this IBI
|
||||
* @len: length of the payload associated to this IBI
|
||||
* @data: payload buffer
|
||||
*
|
||||
* An IBI slot is an object pre-allocated by the controller and used when an
|
||||
* IBI comes in.
|
||||
* Every time an IBI comes in, the I3C master driver should find a free IBI
|
||||
* slot in its IBI slot pool, retrieve the IBI payload and queue the IBI using
|
||||
* i3c_master_queue_ibi().
|
||||
*
|
||||
* How IBI slots are allocated is left to the I3C master driver, though, for
|
||||
* simple kmalloc-based allocation, the generic IBI slot pool can be used.
|
||||
*/
|
||||
struct i3c_ibi_slot {
|
||||
struct work_struct work;
|
||||
struct i3c_dev_desc *dev;
|
||||
unsigned int len;
|
||||
void *data;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_device_ibi_info - IBI information attached to a specific device
|
||||
* @all_ibis_handled: used to be informed when no more IBIs are waiting to be
|
||||
* processed. Used by i3c_device_disable_ibi() to wait for
|
||||
* all IBIs to be dequeued
|
||||
* @pending_ibis: count the number of pending IBIs. Each pending IBI has its
|
||||
* work element queued to the controller workqueue
|
||||
* @max_payload_len: maximum payload length for an IBI coming from this device.
|
||||
* this value is specified when calling
|
||||
* i3c_device_request_ibi() and should not change at run
|
||||
* time. All messages IBIs exceeding this limit should be
|
||||
* rejected by the master
|
||||
* @num_slots: number of IBI slots reserved for this device
|
||||
* @enabled: reflect the IBI status
|
||||
* @handler: IBI handler specified at i3c_device_request_ibi() call time. This
|
||||
* handler will be called from the controller workqueue, and as such
|
||||
* is allowed to sleep (though it is recommended to process the IBI
|
||||
* as fast as possible to not stall processing of other IBIs queued
|
||||
* on the same workqueue).
|
||||
* New I3C messages can be sent from the IBI handler
|
||||
*
|
||||
* The &struct_i3c_device_ibi_info object is allocated when
|
||||
* i3c_device_request_ibi() is called and attached to a specific device. This
|
||||
* object is here to manage IBIs coming from a specific I3C device.
|
||||
*
|
||||
* Note that this structure is the generic view of the IBI management
|
||||
* infrastructure. I3C master drivers may have their own internal
|
||||
* representation which they can associate to the device using
|
||||
* controller-private data.
|
||||
*/
|
||||
struct i3c_device_ibi_info {
|
||||
struct completion all_ibis_handled;
|
||||
atomic_t pending_ibis;
|
||||
unsigned int max_payload_len;
|
||||
unsigned int num_slots;
|
||||
unsigned int enabled;
|
||||
void (*handler)(struct i3c_device *dev,
|
||||
const struct i3c_ibi_payload *payload);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_dev_boardinfo - I3C device board information
|
||||
* @node: used to insert the boardinfo object in the I3C boardinfo list
|
||||
* @init_dyn_addr: initial dynamic address requested by the FW. We provide no
|
||||
* guarantee that the device will end up using this address,
|
||||
* but try our best to assign this specific address to the
|
||||
* device
|
||||
* @static_addr: static address the I3C device listen on before it's been
|
||||
* assigned a dynamic address by the master. Will be used during
|
||||
* bus initialization to assign it a specific dynamic address
|
||||
* before starting DAA (Dynamic Address Assignment)
|
||||
* @pid: I3C Provisional ID exposed by the device. This is a unique identifier
|
||||
* that may be used to attach boardinfo to i3c_dev_desc when the device
|
||||
* does not have a static address
|
||||
* @of_node: optional DT node in case the device has been described in the DT
|
||||
*
|
||||
* This structure is used to attach board-level information to an I3C device.
|
||||
* Not all I3C devices connected on the bus will have a boardinfo. It's only
|
||||
* needed if you want to attach extra resources to a device or assign it a
|
||||
* specific dynamic address.
|
||||
*/
|
||||
struct i3c_dev_boardinfo {
|
||||
struct list_head node;
|
||||
u8 init_dyn_addr;
|
||||
u8 static_addr;
|
||||
u64 pid;
|
||||
struct device_node *of_node;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_dev_desc - I3C device descriptor
|
||||
* @common: common part of the I3C device descriptor
|
||||
* @info: I3C device information. Will be automatically filled when you create
|
||||
* your device with i3c_master_add_i3c_dev_locked()
|
||||
* @ibi_lock: lock used to protect the &struct_i3c_device->ibi
|
||||
* @ibi: IBI info attached to a device. Should be NULL until
|
||||
* i3c_device_request_ibi() is called
|
||||
* @dev: pointer to the I3C device object exposed to I3C device drivers. This
|
||||
* should never be accessed from I3C master controller drivers. Only core
|
||||
* code should manipulate it in when updating the dev <-> desc link or
|
||||
* when propagating IBI events to the driver
|
||||
* @boardinfo: pointer to the boardinfo attached to this I3C device
|
||||
*
|
||||
* Internal representation of an I3C device. This object is only used by the
|
||||
* core and passed to I3C master controller drivers when they're requested to
|
||||
* do some operations on the device.
|
||||
* The core maintains the link between the internal I3C dev descriptor and the
|
||||
* object exposed to the I3C device drivers (&struct_i3c_device).
|
||||
*/
|
||||
struct i3c_dev_desc {
|
||||
struct i3c_i2c_dev_desc common;
|
||||
struct i3c_device_info info;
|
||||
struct mutex ibi_lock;
|
||||
struct i3c_device_ibi_info *ibi;
|
||||
struct i3c_device *dev;
|
||||
const struct i3c_dev_boardinfo *boardinfo;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_device - I3C device object
|
||||
* @dev: device object to register the I3C dev to the device model
|
||||
* @desc: pointer to an i3c device descriptor object. This link is updated
|
||||
* every time the I3C device is rediscovered with a different dynamic
|
||||
* address assigned
|
||||
* @bus: I3C bus this device is attached to
|
||||
*
|
||||
* I3C device object exposed to I3C device drivers. The takes care of linking
|
||||
* this object to the relevant &struct_i3c_dev_desc one.
|
||||
* All I3C devs on the I3C bus are represented, including I3C masters. For each
|
||||
* of them, we have an instance of &struct i3c_device.
|
||||
*/
|
||||
struct i3c_device {
|
||||
struct device dev;
|
||||
struct i3c_dev_desc *desc;
|
||||
struct i3c_bus *bus;
|
||||
};
|
||||
|
||||
/*
|
||||
* The I3C specification says the maximum number of devices connected on the
|
||||
* bus is 11, but this number depends on external parameters like trace length,
|
||||
* capacitive load per Device, and the types of Devices present on the Bus.
|
||||
* I3C master can also have limitations, so this number is just here as a
|
||||
* reference and should be adjusted on a per-controller/per-board basis.
|
||||
*/
|
||||
#define I3C_BUS_MAX_DEVS 11
|
||||
|
||||
#define I3C_BUS_MAX_I3C_SCL_RATE 12900000
|
||||
#define I3C_BUS_TYP_I3C_SCL_RATE 12500000
|
||||
#define I3C_BUS_I2C_FM_PLUS_SCL_RATE 1000000
|
||||
#define I3C_BUS_I2C_FM_SCL_RATE 400000
|
||||
#define I3C_BUS_TLOW_OD_MIN_NS 200
|
||||
|
||||
/**
|
||||
* enum i3c_bus_mode - I3C bus mode
|
||||
* @I3C_BUS_MODE_PURE: only I3C devices are connected to the bus. No limitation
|
||||
* expected
|
||||
* @I3C_BUS_MODE_MIXED_FAST: I2C devices with 50ns spike filter are present on
|
||||
* the bus. The only impact in this mode is that the
|
||||
* high SCL pulse has to stay below 50ns to trick I2C
|
||||
* devices when transmitting I3C frames
|
||||
* @I3C_BUS_MODE_MIXED_SLOW: I2C devices without 50ns spike filter are present
|
||||
* on the bus
|
||||
*/
|
||||
enum i3c_bus_mode {
|
||||
I3C_BUS_MODE_PURE,
|
||||
I3C_BUS_MODE_MIXED_FAST,
|
||||
I3C_BUS_MODE_MIXED_SLOW,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum i3c_addr_slot_status - I3C address slot status
|
||||
* @I3C_ADDR_SLOT_FREE: address is free
|
||||
* @I3C_ADDR_SLOT_RSVD: address is reserved
|
||||
* @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device
|
||||
* @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device
|
||||
* @I3C_ADDR_SLOT_STATUS_MASK: address slot mask
|
||||
*
|
||||
* On an I3C bus, addresses are assigned dynamically, and we need to know which
|
||||
* addresses are free to use and which ones are already assigned.
|
||||
*
|
||||
* Addresses marked as reserved are those reserved by the I3C protocol
|
||||
* (broadcast address, ...).
|
||||
*/
|
||||
enum i3c_addr_slot_status {
|
||||
I3C_ADDR_SLOT_FREE,
|
||||
I3C_ADDR_SLOT_RSVD,
|
||||
I3C_ADDR_SLOT_I2C_DEV,
|
||||
I3C_ADDR_SLOT_I3C_DEV,
|
||||
I3C_ADDR_SLOT_STATUS_MASK = 3,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_bus - I3C bus object
|
||||
* @cur_master: I3C master currently driving the bus. Since I3C is multi-master
|
||||
* this can change over the time. Will be used to let a master
|
||||
* know whether it needs to request bus ownership before sending
|
||||
* a frame or not
|
||||
* @id: bus ID. Assigned by the framework when register the bus
|
||||
* @addrslots: a bitmap with 2-bits per-slot to encode the address status and
|
||||
* ease the DAA (Dynamic Address Assignment) procedure (see
|
||||
* &enum i3c_addr_slot_status)
|
||||
* @mode: bus mode (see &enum i3c_bus_mode)
|
||||
* @scl_rate.i3c: maximum rate for the clock signal when doing I3C SDR/priv
|
||||
* transfers
|
||||
* @scl_rate.i2c: maximum rate for the clock signal when doing I2C transfers
|
||||
* @scl_rate: SCL signal rate for I3C and I2C mode
|
||||
* @devs.i3c: contains a list of I3C device descriptors representing I3C
|
||||
* devices connected on the bus and successfully attached to the
|
||||
* I3C master
|
||||
* @devs.i2c: contains a list of I2C device descriptors representing I2C
|
||||
* devices connected on the bus and successfully attached to the
|
||||
* I3C master
|
||||
* @devs: 2 lists containing all I3C/I2C devices connected to the bus
|
||||
* @lock: read/write lock on the bus. This is needed to protect against
|
||||
* operations that have an impact on the whole bus and the devices
|
||||
* connected to it. For example, when asking slaves to drop their
|
||||
* dynamic address (RSTDAA CCC), we need to make sure no one is trying
|
||||
* to send I3C frames to these devices.
|
||||
* Note that this lock does not protect against concurrency between
|
||||
* devices: several drivers can send different I3C/I2C frames through
|
||||
* the same master in parallel. This is the responsibility of the
|
||||
* master to guarantee that frames are actually sent sequentially and
|
||||
* not interlaced
|
||||
*
|
||||
* The I3C bus is represented with its own object and not implicitly described
|
||||
* by the I3C master to cope with the multi-master functionality, where one bus
|
||||
* can be shared amongst several masters, each of them requesting bus ownership
|
||||
* when they need to.
|
||||
*/
|
||||
struct i3c_bus {
|
||||
struct i3c_dev_desc *cur_master;
|
||||
int id;
|
||||
unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG];
|
||||
enum i3c_bus_mode mode;
|
||||
struct {
|
||||
unsigned long i3c;
|
||||
unsigned long i2c;
|
||||
} scl_rate;
|
||||
struct {
|
||||
struct list_head i3c;
|
||||
struct list_head i2c;
|
||||
} devs;
|
||||
struct rw_semaphore lock;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_master_controller_ops - I3C master methods
|
||||
* @bus_init: hook responsible for the I3C bus initialization. You should at
|
||||
* least call master_set_info() from there and set the bus mode.
|
||||
* You can also put controller specific initialization in there.
|
||||
* This method is mandatory.
|
||||
* @bus_cleanup: cleanup everything done in
|
||||
* &i3c_master_controller_ops->bus_init().
|
||||
* This method is optional.
|
||||
* @attach_i3c_dev: called every time an I3C device is attached to the bus. It
|
||||
* can be after a DAA or when a device is statically declared
|
||||
* by the FW, in which case it will only have a static address
|
||||
* and the dynamic address will be 0.
|
||||
* When this function is called, device information have not
|
||||
* been retrieved yet.
|
||||
* This is a good place to attach master controller specific
|
||||
* data to I3C devices.
|
||||
* This method is optional.
|
||||
* @reattach_i3c_dev: called every time an I3C device has its addressed
|
||||
* changed. It can be because the device has been powered
|
||||
* down and has lost its address, or it can happen when a
|
||||
* device had a static address and has been assigned a
|
||||
* dynamic address with SETDASA.
|
||||
* This method is optional.
|
||||
* @detach_i3c_dev: called when an I3C device is detached from the bus. Usually
|
||||
* happens when the master device is unregistered.
|
||||
* This method is optional.
|
||||
* @do_daa: do a DAA (Dynamic Address Assignment) procedure. This is procedure
|
||||
* should send an ENTDAA CCC command and then add all devices
|
||||
* discovered sure the DAA using i3c_master_add_i3c_dev_locked().
|
||||
* Add devices added with i3c_master_add_i3c_dev_locked() will then be
|
||||
* attached or re-attached to the controller.
|
||||
* This method is mandatory.
|
||||
* @supports_ccc_cmd: should return true if the CCC command is supported, false
|
||||
* otherwise.
|
||||
* This method is optional, if not provided the core assumes
|
||||
* all CCC commands are supported.
|
||||
* @send_ccc_cmd: send a CCC command
|
||||
* This method is mandatory.
|
||||
* @priv_xfers: do one or several private I3C SDR transfers
|
||||
* This method is mandatory.
|
||||
* @attach_i2c_dev: called every time an I2C device is attached to the bus.
|
||||
* This is a good place to attach master controller specific
|
||||
* data to I2C devices.
|
||||
* This method is optional.
|
||||
* @detach_i2c_dev: called when an I2C device is detached from the bus. Usually
|
||||
* happens when the master device is unregistered.
|
||||
* This method is optional.
|
||||
* @i2c_xfers: do one or several I2C transfers. Note that, unlike i3c
|
||||
* transfers, the core does not guarantee that buffers attached to
|
||||
* the transfers are DMA-safe. If drivers want to have DMA-safe
|
||||
* buffers, they should use the i2c_get_dma_safe_msg_buf()
|
||||
* and i2c_put_dma_safe_msg_buf() helpers provided by the I2C
|
||||
* framework.
|
||||
* This method is mandatory.
|
||||
* @i2c_funcs: expose the supported I2C functionalities.
|
||||
* This method is mandatory.
|
||||
* @request_ibi: attach an IBI handler to an I3C device. This implies defining
|
||||
* an IBI handler and the constraints of the IBI (maximum payload
|
||||
* length and number of pre-allocated slots).
|
||||
* Some controllers support less IBI-capable devices than regular
|
||||
* devices, so this method might return -%EBUSY if there's no
|
||||
* more space for an extra IBI registration
|
||||
* This method is optional.
|
||||
* @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
|
||||
* should have been disabled with ->disable_irq() prior to that
|
||||
* This method is mandatory only if ->request_ibi is not NULL.
|
||||
* @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
|
||||
* prior to ->enable_ibi(). The controller should first enable
|
||||
* the IBI on the controller end (for example, unmask the hardware
|
||||
* IRQ) and then send the ENEC CCC command (with the IBI flag set)
|
||||
* to the I3C device.
|
||||
* This method is mandatory only if ->request_ibi is not NULL.
|
||||
* @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
|
||||
* flag set and then deactivate the hardware IRQ on the
|
||||
* controller end.
|
||||
* This method is mandatory only if ->request_ibi is not NULL.
|
||||
* @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
|
||||
* processed by its handler. The IBI slot should be put back
|
||||
* in the IBI slot pool so that the controller can re-use it
|
||||
* for a future IBI
|
||||
* This method is mandatory only if ->request_ibi is not
|
||||
* NULL.
|
||||
*/
|
||||
struct i3c_master_controller_ops {
|
||||
int (*bus_init)(struct i3c_master_controller *master);
|
||||
void (*bus_cleanup)(struct i3c_master_controller *master);
|
||||
int (*attach_i3c_dev)(struct i3c_dev_desc *dev);
|
||||
int (*reattach_i3c_dev)(struct i3c_dev_desc *dev, u8 old_dyn_addr);
|
||||
void (*detach_i3c_dev)(struct i3c_dev_desc *dev);
|
||||
int (*do_daa)(struct i3c_master_controller *master);
|
||||
bool (*supports_ccc_cmd)(struct i3c_master_controller *master,
|
||||
const struct i3c_ccc_cmd *cmd);
|
||||
int (*send_ccc_cmd)(struct i3c_master_controller *master,
|
||||
struct i3c_ccc_cmd *cmd);
|
||||
int (*priv_xfers)(struct i3c_dev_desc *dev,
|
||||
struct i3c_priv_xfer *xfers,
|
||||
int nxfers);
|
||||
int (*attach_i2c_dev)(struct i2c_dev_desc *dev);
|
||||
void (*detach_i2c_dev)(struct i2c_dev_desc *dev);
|
||||
int (*i2c_xfers)(struct i2c_dev_desc *dev,
|
||||
const struct i2c_msg *xfers, int nxfers);
|
||||
u32 (*i2c_funcs)(struct i3c_master_controller *master);
|
||||
int (*request_ibi)(struct i3c_dev_desc *dev,
|
||||
const struct i3c_ibi_setup *req);
|
||||
void (*free_ibi)(struct i3c_dev_desc *dev);
|
||||
int (*enable_ibi)(struct i3c_dev_desc *dev);
|
||||
int (*disable_ibi)(struct i3c_dev_desc *dev);
|
||||
void (*recycle_ibi_slot)(struct i3c_dev_desc *dev,
|
||||
struct i3c_ibi_slot *slot);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct i3c_master_controller - I3C master controller object
|
||||
* @dev: device to be registered to the device-model
|
||||
* @this: an I3C device object representing this master. This device will be
|
||||
* added to the list of I3C devs available on the bus
|
||||
* @i2c: I2C adapter used for backward compatibility. This adapter is
|
||||
* registered to the I2C subsystem to be as transparent as possible to
|
||||
* existing I2C drivers
|
||||
* @ops: master operations. See &struct i3c_master_controller_ops
|
||||
* @secondary: true if the master is a secondary master
|
||||
* @init_done: true when the bus initialization is done
|
||||
* @boardinfo.i3c: list of I3C boardinfo objects
|
||||
* @boardinfo.i2c: list of I2C boardinfo objects
|
||||
* @boardinfo: board-level information attached to devices connected on the bus
|
||||
* @bus: I3C bus exposed by this master
|
||||
* @wq: workqueue used to execute IBI handlers. Can also be used by master
|
||||
* drivers if they need to postpone operations that need to take place
|
||||
* in a thread context. Typical examples are Hot Join processing which
|
||||
* requires taking the bus lock in maintenance, which in turn, can only
|
||||
* be done from a sleep-able context
|
||||
*
|
||||
* A &struct i3c_master_controller has to be registered to the I3C subsystem
|
||||
* through i3c_master_register(). None of &struct i3c_master_controller fields
|
||||
* should be set manually, just pass appropriate values to
|
||||
* i3c_master_register().
|
||||
*/
|
||||
struct i3c_master_controller {
|
||||
struct device dev;
|
||||
struct i3c_dev_desc *this;
|
||||
struct i2c_adapter i2c;
|
||||
const struct i3c_master_controller_ops *ops;
|
||||
unsigned int secondary : 1;
|
||||
unsigned int init_done : 1;
|
||||
struct {
|
||||
struct list_head i3c;
|
||||
struct list_head i2c;
|
||||
} boardinfo;
|
||||
struct i3c_bus bus;
|
||||
struct workqueue_struct *wq;
|
||||
};
|
||||
|
||||
/**
|
||||
* i3c_bus_for_each_i2cdev() - iterate over all I2C devices present on the bus
|
||||
* @bus: the I3C bus
|
||||
* @dev: an I2C device descriptor pointer updated to point to the current slot
|
||||
* at each iteration of the loop
|
||||
*
|
||||
* Iterate over all I2C devs present on the bus.
|
||||
*/
|
||||
#define i3c_bus_for_each_i2cdev(bus, dev) \
|
||||
list_for_each_entry(dev, &(bus)->devs.i2c, common.node)
|
||||
|
||||
/**
|
||||
* i3c_bus_for_each_i3cdev() - iterate over all I3C devices present on the bus
|
||||
* @bus: the I3C bus
|
||||
* @dev: and I3C device descriptor pointer updated to point to the current slot
|
||||
* at each iteration of the loop
|
||||
*
|
||||
* Iterate over all I3C devs present on the bus.
|
||||
*/
|
||||
#define i3c_bus_for_each_i3cdev(bus, dev) \
|
||||
list_for_each_entry(dev, &(bus)->devs.i3c, common.node)
|
||||
|
||||
int i3c_master_do_i2c_xfers(struct i3c_master_controller *master,
|
||||
const struct i2c_msg *xfers,
|
||||
int nxfers);
|
||||
|
||||
int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr,
|
||||
u8 evts);
|
||||
int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr,
|
||||
u8 evts);
|
||||
int i3c_master_entdaa_locked(struct i3c_master_controller *master);
|
||||
int i3c_master_defslvs_locked(struct i3c_master_controller *master);
|
||||
|
||||
int i3c_master_get_free_addr(struct i3c_master_controller *master,
|
||||
u8 start_addr);
|
||||
|
||||
int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master,
|
||||
u8 addr);
|
||||
int i3c_master_do_daa(struct i3c_master_controller *master);
|
||||
|
||||
int i3c_master_set_info(struct i3c_master_controller *master,
|
||||
const struct i3c_device_info *info);
|
||||
|
||||
int i3c_master_register(struct i3c_master_controller *master,
|
||||
struct device *parent,
|
||||
const struct i3c_master_controller_ops *ops,
|
||||
bool secondary);
|
||||
int i3c_master_unregister(struct i3c_master_controller *master);
|
||||
|
||||
/**
|
||||
* i3c_dev_get_master_data() - get master private data attached to an I3C
|
||||
* device descriptor
|
||||
* @dev: the I3C device descriptor to get private data from
|
||||
*
|
||||
* Return: the private data previously attached with i3c_dev_set_master_data()
|
||||
* or NULL if no data has been attached to the device.
|
||||
*/
|
||||
static inline void *i3c_dev_get_master_data(const struct i3c_dev_desc *dev)
|
||||
{
|
||||
return dev->common.master_priv;
|
||||
}
|
||||
|
||||
/**
|
||||
* i3c_dev_set_master_data() - attach master private data to an I3C device
|
||||
* descriptor
|
||||
* @dev: the I3C device descriptor to attach private data to
|
||||
* @data: private data
|
||||
*
|
||||
* This functions allows a master controller to attach per-device private data
|
||||
* which can then be retrieved with i3c_dev_get_master_data().
|
||||
*/
|
||||
static inline void i3c_dev_set_master_data(struct i3c_dev_desc *dev,
|
||||
void *data)
|
||||
{
|
||||
dev->common.master_priv = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_dev_get_master_data() - get master private data attached to an I2C
|
||||
* device descriptor
|
||||
* @dev: the I2C device descriptor to get private data from
|
||||
*
|
||||
* Return: the private data previously attached with i2c_dev_set_master_data()
|
||||
* or NULL if no data has been attached to the device.
|
||||
*/
|
||||
static inline void *i2c_dev_get_master_data(const struct i2c_dev_desc *dev)
|
||||
{
|
||||
return dev->common.master_priv;
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_dev_set_master_data() - attach master private data to an I2C device
|
||||
* descriptor
|
||||
* @dev: the I2C device descriptor to attach private data to
|
||||
* @data: private data
|
||||
*
|
||||
* This functions allows a master controller to attach per-device private data
|
||||
* which can then be retrieved with i2c_device_get_master_data().
|
||||
*/
|
||||
static inline void i2c_dev_set_master_data(struct i2c_dev_desc *dev,
|
||||
void *data)
|
||||
{
|
||||
dev->common.master_priv = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* i3c_dev_get_master() - get master used to communicate with a device
|
||||
* @dev: I3C dev
|
||||
*
|
||||
* Return: the master controller driving @dev
|
||||
*/
|
||||
static inline struct i3c_master_controller *
|
||||
i3c_dev_get_master(struct i3c_dev_desc *dev)
|
||||
{
|
||||
return dev->common.master;
|
||||
}
|
||||
|
||||
/**
|
||||
* i2c_dev_get_master() - get master used to communicate with a device
|
||||
* @dev: I2C dev
|
||||
*
|
||||
* Return: the master controller driving @dev
|
||||
*/
|
||||
static inline struct i3c_master_controller *
|
||||
i2c_dev_get_master(struct i2c_dev_desc *dev)
|
||||
{
|
||||
return dev->common.master;
|
||||
}
|
||||
|
||||
/**
|
||||
* i3c_master_get_bus() - get the bus attached to a master
|
||||
* @master: master object
|
||||
*
|
||||
* Return: the I3C bus @master is connected to
|
||||
*/
|
||||
static inline struct i3c_bus *
|
||||
i3c_master_get_bus(struct i3c_master_controller *master)
|
||||
{
|
||||
return &master->bus;
|
||||
}
|
||||
|
||||
struct i3c_generic_ibi_pool;
|
||||
|
||||
struct i3c_generic_ibi_pool *
|
||||
i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev,
|
||||
const struct i3c_ibi_setup *req);
|
||||
void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool);
|
||||
|
||||
struct i3c_ibi_slot *
|
||||
i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool);
|
||||
void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool,
|
||||
struct i3c_ibi_slot *slot);
|
||||
|
||||
void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot);
|
||||
|
||||
struct i3c_ibi_slot *i3c_master_get_free_ibi_slot(struct i3c_dev_desc *dev);
|
||||
|
||||
#endif /* I3C_MASTER_H */
|
||||
|
|
@ -448,6 +448,23 @@ struct pci_epf_device_id {
|
|||
kernel_ulong_t driver_data;
|
||||
};
|
||||
|
||||
/* i3c */
|
||||
|
||||
#define I3C_MATCH_DCR 0x1
|
||||
#define I3C_MATCH_MANUF 0x2
|
||||
#define I3C_MATCH_PART 0x4
|
||||
#define I3C_MATCH_EXTRA_INFO 0x8
|
||||
|
||||
struct i3c_device_id {
|
||||
__u8 match_flags;
|
||||
__u8 dcr;
|
||||
__u16 manuf_id;
|
||||
__u16 part_id;
|
||||
__u16 extra_info;
|
||||
|
||||
const void *data;
|
||||
};
|
||||
|
||||
/* spi */
|
||||
|
||||
#define SPI_NAME_SIZE 32
|
||||
|
|
|
|||
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