net: atlantic: A2 hw_ops skeleton
This patch adds basic hw_ops layout for A2. Actual implementation will be added in the follow-up patches. Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Igor Russkikh
David S. Miller
Родитель
5cfd54d7dc
Коммит
b3f0c79cba
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@ -25,6 +25,7 @@ atlantic-objs := aq_main.o \
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hw_atl/hw_atl_utils.o \
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hw_atl/hw_atl_utils_fw2x.o \
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hw_atl/hw_atl_llh.o \
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hw_atl2/hw_atl2.o \
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hw_atl2/hw_atl2_utils_fw.o \
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hw_atl2/hw_atl2_llh.o \
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macsec/macsec_api.o
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@ -55,6 +55,7 @@ struct aq_hw_caps_s {
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u8 rx_rings;
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bool flow_control;
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bool is_64_dma;
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u32 priv_data_len;
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};
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struct aq_hw_link_status_s {
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@ -16,6 +16,7 @@
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#include "aq_pci_func.h"
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#include "hw_atl/hw_atl_a0.h"
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#include "hw_atl/hw_atl_b0.h"
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#include "hw_atl2/hw_atl2.h"
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#include "aq_filters.h"
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#include "aq_drvinfo.h"
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#include "aq_macsec.h"
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@ -41,6 +42,13 @@ static const struct pci_device_id aq_pci_tbl[] = {
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111S), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112S), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC113DEV), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC113CS), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC114CS), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC113), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC113C), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC115C), },
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{}
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};
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@ -70,6 +78,13 @@ static const struct aq_board_revision_s hw_atl_boards[] = {
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{ AQ_DEVICE_ID_AQC109S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109s, },
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{ AQ_DEVICE_ID_AQC111S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111s, },
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{ AQ_DEVICE_ID_AQC112S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112s, },
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{ AQ_DEVICE_ID_AQC113DEV, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, },
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{ AQ_DEVICE_ID_AQC113, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, },
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{ AQ_DEVICE_ID_AQC113CS, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, },
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{ AQ_DEVICE_ID_AQC114CS, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, },
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{ AQ_DEVICE_ID_AQC113C, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, },
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{ AQ_DEVICE_ID_AQC115C, AQ_HWREV_ANY, &hw_atl2_ops, &hw_atl2_caps_aqc113, },
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};
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MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
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@ -104,10 +119,8 @@ int aq_pci_func_init(struct pci_dev *pdev)
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int err;
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
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if (!err) {
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if (!err)
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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}
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if (err) {
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (!err)
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@ -237,6 +250,15 @@ static int aq_pci_probe(struct pci_dev *pdev,
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goto err_ioremap;
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}
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self->aq_hw->aq_nic_cfg = aq_nic_get_cfg(self);
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if (self->aq_hw->aq_nic_cfg->aq_hw_caps->priv_data_len) {
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int len = self->aq_hw->aq_nic_cfg->aq_hw_caps->priv_data_len;
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self->aq_hw->priv = kzalloc(len, GFP_KERNEL);
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if (!self->aq_hw->priv) {
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err = -ENOMEM;
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goto err_free_aq_hw;
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}
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}
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for (bar = 0; bar < 4; ++bar) {
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if (IORESOURCE_MEM & pci_resource_flags(pdev, bar)) {
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@ -245,19 +267,19 @@ static int aq_pci_probe(struct pci_dev *pdev,
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mmio_pa = pci_resource_start(pdev, bar);
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if (mmio_pa == 0U) {
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err = -EIO;
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goto err_free_aq_hw;
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goto err_free_aq_hw_priv;
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}
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reg_sz = pci_resource_len(pdev, bar);
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if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
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err = -EIO;
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goto err_free_aq_hw;
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goto err_free_aq_hw_priv;
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}
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self->aq_hw->mmio = ioremap(mmio_pa, reg_sz);
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if (!self->aq_hw->mmio) {
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err = -EIO;
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goto err_free_aq_hw;
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goto err_free_aq_hw_priv;
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}
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break;
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}
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@ -265,7 +287,7 @@ static int aq_pci_probe(struct pci_dev *pdev,
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if (bar == 4) {
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err = -EIO;
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goto err_free_aq_hw;
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goto err_free_aq_hw_priv;
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}
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numvecs = min((u8)AQ_CFG_VECS_DEF,
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@ -305,6 +327,8 @@ err_register:
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aq_pci_free_irq_vectors(self);
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err_hwinit:
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iounmap(self->aq_hw->mmio);
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err_free_aq_hw_priv:
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kfree(self->aq_hw->priv);
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err_free_aq_hw:
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kfree(self->aq_hw);
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err_ioremap:
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@ -332,6 +356,7 @@ static void aq_pci_remove(struct pci_dev *pdev)
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aq_nic_free_vectors(self);
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aq_pci_free_irq_vectors(self);
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iounmap(self->aq_hw->mmio);
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kfree(self->aq_hw->priv);
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kfree(self->aq_hw);
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pci_release_regions(pdev);
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free_netdev(self->ndev);
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@ -0,0 +1,226 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Atlantic Network Driver
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include "aq_hw.h"
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#include "hw_atl2_utils.h"
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#include "hw_atl2_internal.h"
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#define DEFAULT_BOARD_BASIC_CAPABILITIES \
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.is_64_dma = true, \
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.msix_irqs = 8U, \
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.irq_mask = ~0U, \
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.vecs = HW_ATL2_RSS_MAX, \
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.tcs = HW_ATL2_TC_MAX, \
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.rxd_alignment = 1U, \
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.rxd_size = HW_ATL2_RXD_SIZE, \
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.rxds_max = HW_ATL2_MAX_RXD, \
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.rxds_min = HW_ATL2_MIN_RXD, \
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.txd_alignment = 1U, \
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.txd_size = HW_ATL2_TXD_SIZE, \
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.txds_max = HW_ATL2_MAX_TXD, \
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.txds_min = HW_ATL2_MIN_TXD, \
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.txhwb_alignment = 4096U, \
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.tx_rings = HW_ATL2_TX_RINGS, \
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.rx_rings = HW_ATL2_RX_RINGS, \
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.hw_features = NETIF_F_HW_CSUM | \
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NETIF_F_RXCSUM | \
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NETIF_F_RXHASH | \
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NETIF_F_SG | \
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NETIF_F_TSO | \
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NETIF_F_TSO6 | \
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NETIF_F_LRO | \
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NETIF_F_NTUPLE | \
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NETIF_F_HW_VLAN_CTAG_FILTER | \
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NETIF_F_HW_VLAN_CTAG_RX | \
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NETIF_F_HW_VLAN_CTAG_TX | \
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NETIF_F_GSO_UDP_L4 | \
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NETIF_F_GSO_PARTIAL, \
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.hw_priv_flags = IFF_UNICAST_FLT, \
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.flow_control = true, \
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.mtu = HW_ATL2_MTU_JUMBO, \
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.mac_regs_count = 72, \
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.hw_alive_check_addr = 0x10U, \
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.priv_data_len = sizeof(struct hw_atl2_priv)
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const struct aq_hw_caps_s hw_atl2_caps_aqc113 = {
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DEFAULT_BOARD_BASIC_CAPABILITIES,
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.media_type = AQ_HW_MEDIA_TYPE_TP,
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.link_speed_msk = AQ_NIC_RATE_10G |
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AQ_NIC_RATE_5G |
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AQ_NIC_RATE_2GS |
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AQ_NIC_RATE_1G |
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AQ_NIC_RATE_100M |
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AQ_NIC_RATE_10M,
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};
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static int hw_atl2_hw_reset(struct aq_hw_s *self)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_rss_hash_set(struct aq_hw_s *self,
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struct aq_rss_parameters *rss_params)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_rss_set(struct aq_hw_s *self,
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struct aq_rss_parameters *rss_params)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_offload_set(struct aq_hw_s *self,
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struct aq_nic_cfg_s *aq_nic_cfg)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_init(struct aq_hw_s *self, u8 *mac_addr)
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{
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struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv;
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u8 base_index, count;
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int err;
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err = hw_atl2_utils_get_action_resolve_table_caps(self, &base_index,
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&count);
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if (err)
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return err;
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priv->art_base_index = 8 * base_index;
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_tx_start(struct aq_hw_s *self,
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struct aq_ring_s *ring)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_rx_start(struct aq_hw_s *self,
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struct aq_ring_s *ring)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_start(struct aq_hw_s *self)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_tx_xmit(struct aq_hw_s *self,
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struct aq_ring_s *ring,
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unsigned int frags)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_rx_init(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring,
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struct aq_ring_param_s *aq_ring_param)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_tx_init(struct aq_hw_s *self,
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struct aq_ring_s *aq_ring,
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struct aq_ring_param_s *aq_ring_param)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_rx_fill(struct aq_hw_s *self, struct aq_ring_s *ring,
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unsigned int sw_tail_old)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_tx_head_update(struct aq_hw_s *self,
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struct aq_ring_s *ring)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_rx_receive(struct aq_hw_s *self,
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struct aq_ring_s *ring)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_irq_enable(struct aq_hw_s *self, u64 mask)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_irq_disable(struct aq_hw_s *self, u64 mask)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_irq_read(struct aq_hw_s *self, u64 *mask)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_interrupt_moderation_set(struct aq_hw_s *self)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_stop(struct aq_hw_s *self)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring)
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{
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return -EOPNOTSUPP;
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}
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static int hw_atl2_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring)
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{
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return -EOPNOTSUPP;
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}
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static struct aq_stats_s *hw_atl2_utils_get_hw_stats(struct aq_hw_s *self)
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{
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return &self->curr_stats;
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}
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const struct aq_hw_ops hw_atl2_ops = {
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.hw_set_mac_address = hw_atl2_hw_mac_addr_set,
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.hw_init = hw_atl2_hw_init,
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.hw_reset = hw_atl2_hw_reset,
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.hw_start = hw_atl2_hw_start,
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.hw_ring_tx_start = hw_atl2_hw_ring_tx_start,
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.hw_ring_tx_stop = hw_atl2_hw_ring_tx_stop,
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.hw_ring_rx_start = hw_atl2_hw_ring_rx_start,
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.hw_ring_rx_stop = hw_atl2_hw_ring_rx_stop,
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.hw_stop = hw_atl2_hw_stop,
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.hw_ring_tx_xmit = hw_atl2_hw_ring_tx_xmit,
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.hw_ring_tx_head_update = hw_atl2_hw_ring_tx_head_update,
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.hw_ring_rx_receive = hw_atl2_hw_ring_rx_receive,
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.hw_ring_rx_fill = hw_atl2_hw_ring_rx_fill,
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.hw_irq_enable = hw_atl2_hw_irq_enable,
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.hw_irq_disable = hw_atl2_hw_irq_disable,
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.hw_irq_read = hw_atl2_hw_irq_read,
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.hw_ring_rx_init = hw_atl2_hw_ring_rx_init,
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.hw_ring_tx_init = hw_atl2_hw_ring_tx_init,
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.hw_interrupt_moderation_set = hw_atl2_hw_interrupt_moderation_set,
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.hw_rss_set = hw_atl2_hw_rss_set,
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.hw_rss_hash_set = hw_atl2_hw_rss_hash_set,
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.hw_get_hw_stats = hw_atl2_utils_get_hw_stats,
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.hw_set_offload = hw_atl2_hw_offload_set,
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};
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Atlantic Network Driver
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef HW_ATL2_H
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#define HW_ATL2_H
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#include "aq_common.h"
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extern const struct aq_hw_caps_s hw_atl2_caps_aqc113;
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extern const struct aq_hw_ops hw_atl2_ops;
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#endif /* HW_ATL2_H */
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@ -9,9 +9,29 @@
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#include "hw_atl2_utils.h"
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#define HW_ATL2_MTU_JUMBO 16352U
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#define HW_ATL2_MTU 1514U
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#define HW_ATL2_TX_RINGS 4U
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#define HW_ATL2_RX_RINGS 4U
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|
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#define HW_ATL2_RINGS_MAX 32U
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#define HW_ATL2_TXD_SIZE (16U)
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#define HW_ATL2_RXD_SIZE (16U)
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#define HW_ATL2_TC_MAX 1U
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#define HW_ATL2_RSS_MAX 8U
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|
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#define HW_ATL2_MIN_RXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))
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#define HW_ATL2_MIN_TXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))
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#define HW_ATL2_MAX_RXD 8184U
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#define HW_ATL2_MAX_TXD 8184U
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|
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struct hw_atl2_priv {
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struct statistics_s last_stats;
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unsigned int art_base_index;
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||||
};
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||||
|
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#endif /* HW_ATL2_INTERNAL_H */
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