Merge branch 'clk-shmobile-for-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
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@ -10,9 +10,11 @@ Required Properties:
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- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
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- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
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- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
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- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
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- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
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- "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
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- "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
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- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
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- "renesas,cpg-div6-clock" for generic DIV6 clocks
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and "renesas,cpg-div6-clock" as a fallback.
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- reg: Base address and length of the memory resource used by the DIV6 clock
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- clocks: Reference to the parent clock(s); either one, four, or eight
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clocks must be specified. For clocks with multiple parents, invalid
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@ -13,12 +13,14 @@ Required Properties:
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- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
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- "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
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- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
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- "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
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- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
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- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
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- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
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- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
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- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
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- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
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- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
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- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
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and "renesas,cpg-mstp-clocks" as a fallback.
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- reg: Base address and length of the I/O mapped registers used by the MSTP
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clocks. The first register is the clock control register and is mandatory.
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The second register is the clock status register and is optional when not
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@ -10,7 +10,7 @@ Required Properties:
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- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
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- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
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- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
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- "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
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and "renesas,rcar-gen2-cpg-clocks" as a fallback.
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- reg: Base address and length of the memory resource used by the CPG
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@ -7,7 +7,7 @@ Required Properties:
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- compatible: Must be one of
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- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
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- "renesas,rz-cpg-clocks" for the generic RZ CPG
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and "renesas,rz-cpg-clocks" as a fallback.
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: References to possible parent clocks. Order must match clock modes
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in the datasheet. For the r7s72100, this is extal, usb_x1.
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