Staging: et131x: clean up word 3 definition
This is basically not really used so turn it into a u32 and comment the format for reference Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -603,16 +603,16 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
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if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
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if (++etdev->TxRing.TxPacketsSinceLastinterrupt ==
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PARM_TX_NUM_BUFS_DEF) {
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CurDesc[FragmentNumber - 1].word3.value = 0x5;
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/* Last element & Interrupt flag */
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CurDesc[FragmentNumber - 1].word3 = 0x5;
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etdev->TxRing.TxPacketsSinceLastinterrupt = 0;
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} else {
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CurDesc[FragmentNumber - 1].word3.value = 0x1;
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} else { /* Last element */
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CurDesc[FragmentNumber - 1].word3 = 0x1;
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}
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} else {
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CurDesc[FragmentNumber - 1].word3.value = 0x5;
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CurDesc[FragmentNumber - 1].word3 = 0x5;
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}
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CurDesc[0].word3.bits.f = 1;
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CurDesc[0].word3 |= 2; /* First element flag */
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pMpTcb->WrIndexStart = etdev->TxRing.txDmaReadyToSend;
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pMpTcb->PacketStaleCount = 0;
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@ -84,56 +84,32 @@ typedef union _txdesc_word2_t {
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} TXDESC_WORD2_t, *PTXDESC_WORD2_t;
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/*
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* TXDESC_WORD3_t structure holds part of the control bits in the Tx Descriptor
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* ring for the ET-1310
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* word 3 of the control bits in the Tx Descriptor ring for the
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* ET-1310
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*
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* 0: last packet in the sequence
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* 1: first packet in the sequence
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* 2: interrupt the processor when this pkt sent
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* 3: Control word - no packet data
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* 4: Issue half-duplex backpressure : XON/XOFF
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* 5: send pause frame
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* 6: Tx frame has error
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* 7: append CRC
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* 8: MAC override
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* 9: pad packet
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* 10: Packet is a Huge packet
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* 11: append VLAN tag
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* 12: IP checksum assist
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* 13: TCP checksum assist
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* 14: UDP checksum assist
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*/
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typedef union _txdesc_word3_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 unused:17; /* bits 15-31 */
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u32 udpa:1; /* bit 14(UDP checksum assist) */
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u32 tcpa:1; /* bit 13(TCP checksum assist) */
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u32 ipa:1; /* bit 12(IP checksum assist) */
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u32 vlan:1; /* bit 11(append VLAN tag) */
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u32 hp:1; /* bit 10(Packet is a Huge packet) */
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u32 pp:1; /* bit 9(pad packet) */
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u32 mac:1; /* bit 8(MAC override) */
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u32 crc:1; /* bit 7(append CRC) */
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u32 e:1; /* bit 6(Tx frame has error) */
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u32 pf:1; /* bit 5(send pause frame) */
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u32 bp:1; /* bit 4(Issue half-duplex backpressure (XON/XOFF) */
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u32 cw:1; /* bit 3(Control word - no packet data) */
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u32 ir:1; /* bit 2(interrupt the processor when this pkt sent) */
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u32 f:1; /* bit 1(first packet in the sequence) */
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u32 l:1; /* bit 0(last packet in the sequence) */
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#else
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u32 l:1; /* bit 0(last packet in the sequence) */
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u32 f:1; /* bit 1(first packet in the sequence) */
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u32 ir:1; /* bit 2(interrupt the processor when this pkt sent) */
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u32 cw:1; /* bit 3(Control word - no packet data) */
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u32 bp:1; /* bit 4(Issue half-duplex backpressure (XON/XOFF) */
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u32 pf:1; /* bit 5(send pause frame) */
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u32 e:1; /* bit 6(Tx frame has error) */
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u32 crc:1; /* bit 7(append CRC) */
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u32 mac:1; /* bit 8(MAC override) */
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u32 pp:1; /* bit 9(pad packet) */
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u32 hp:1; /* bit 10(Packet is a Huge packet) */
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u32 vlan:1; /* bit 11(append VLAN tag) */
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u32 ipa:1; /* bit 12(IP checksum assist) */
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u32 tcpa:1; /* bit 13(TCP checksum assist) */
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u32 udpa:1; /* bit 14(UDP checksum assist) */
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u32 unused:17; /* bits 15-31 */
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#endif /* _BIT_FIELDS_HTOL */
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} bits;
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} TXDESC_WORD3_t, *PTXDESC_WORD3_t;
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/* TX_DESC_ENTRY_t is sructure representing each descriptor on the ring */
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typedef struct _tx_desc_entry_t {
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u32 DataBufferPtrHigh;
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u32 DataBufferPtrLow;
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TXDESC_WORD2_t word2; /* control words how to xmit the */
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TXDESC_WORD3_t word3; /* data (detailed above) */
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u32 word3; /* data (detailed above) */
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} TX_DESC_ENTRY_t, *PTX_DESC_ENTRY_t;
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