drm/amdgpu: fix xclk freq on CHIP_STONEY
According to Alex, most APUs from that time seem to have the same issue (vbios says 48Mhz, actual is 100Mhz). I only have a CHIP_STONEY so I limit the fixup to CHIP_STONEY Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -542,8 +542,15 @@ static u32 vi_get_xclk(struct amdgpu_device *adev)
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u32 reference_clock = adev->clock.spll.reference_freq;
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u32 tmp;
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if (adev->flags & AMD_IS_APU)
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return reference_clock;
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if (adev->flags & AMD_IS_APU) {
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switch (adev->asic_type) {
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case CHIP_STONEY:
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/* vbios says 48Mhz, but the actual freq is 100Mhz */
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return 10000;
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default:
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return reference_clock;
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}
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}
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tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
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if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
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