Merge branch 'pci/ctrl/loongson'
- Wrap ARM64-specific MCFG quirks in #ifdef so Loongson can use the file (Huacai Chen) - Use generic (not 32-bit only) config accesses for LS2K/LS7A (Huacai Chen) - Add ACPI and MCFG support for Loongson LS7A (Huacai Chen) - Avoid config reads to non-existent LS2K/LS7A devices because a hardware defect causes machine hangs (Huacai Chen) - Work around LS7A integrated devices that report incorrect Interrupt Pin values (Jianmin Lv) * pci/ctrl/loongson: PCI: loongson: Work around LS7A incorrect Interrupt Pin registers PCI: loongson: Don't access non-existent devices PCI: loongson: Add ACPI init support PCI: loongson: Use generic 8/16/32-bit config ops on LS2K/LS7A PCI/ACPI: Guard ARM64-specific mcfg_quirks
This commit is contained in:
Bjorn Helgaas
Коммит
b4773c53c5
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@ -41,6 +41,8 @@ struct mcfg_fixup {
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static struct mcfg_fixup mcfg_quirks[] = {
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/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
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#ifdef CONFIG_ARM64
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#define AL_ECAM(table_id, rev, seg, ops) \
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{ "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
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@ -169,6 +171,17 @@ static struct mcfg_fixup mcfg_quirks[] = {
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ALTRA_ECAM_QUIRK(1, 13),
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ALTRA_ECAM_QUIRK(1, 14),
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ALTRA_ECAM_QUIRK(1, 15),
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#endif /* ARM64 */
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#ifdef CONFIG_LOONGARCH
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#define LOONGSON_ECAM_MCFG(table_id, seg) \
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{ "LOONGS", table_id, 1, seg, MCFG_BUS_ANY, &loongson_pci_ecam_ops }
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LOONGSON_ECAM_MCFG("\0", 0),
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LOONGSON_ECAM_MCFG("LOONGSON", 0),
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LOONGSON_ECAM_MCFG("\0", 1),
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LOONGSON_ECAM_MCFG("LOONGSON", 1),
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#endif /* LOONGARCH */
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};
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static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
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@ -293,7 +293,7 @@ config PCI_HYPERV_INTERFACE
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config PCI_LOONGSON
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bool "LOONGSON PCI Controller"
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depends on MACH_LOONGSON64 || COMPILE_TEST
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depends on OF
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depends on OF || ACPI
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depends on PCI_QUIRKS
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default MACH_LOONGSON64
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help
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@ -9,6 +9,8 @@
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include "../pci.h"
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@ -18,18 +20,31 @@
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#define DEV_PCIE_PORT_2 0x7a29
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#define DEV_LS2K_APB 0x7a02
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#define DEV_LS7A_CONF 0x7a10
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#define DEV_LS7A_GMAC 0x7a03
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#define DEV_LS7A_DC1 0x7a06
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#define DEV_LS7A_LPC 0x7a0c
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#define DEV_LS7A_AHCI 0x7a08
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#define DEV_LS7A_CONF 0x7a10
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#define DEV_LS7A_GNET 0x7a13
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#define DEV_LS7A_EHCI 0x7a14
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#define DEV_LS7A_DC2 0x7a36
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#define DEV_LS7A_HDMI 0x7a37
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#define FLAG_CFG0 BIT(0)
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#define FLAG_CFG1 BIT(1)
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#define FLAG_DEV_FIX BIT(2)
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#define FLAG_DEV_HIDDEN BIT(3)
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struct loongson_pci_data {
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u32 flags;
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struct pci_ops *ops;
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};
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struct loongson_pci {
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void __iomem *cfg0_base;
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void __iomem *cfg1_base;
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struct platform_device *pdev;
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u32 flags;
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const struct loongson_pci_data *data;
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};
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/* Fixup wrong class code in PCIe bridges */
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@ -92,55 +107,106 @@ static void loongson_mrrs_quirk(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
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static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
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unsigned int devfn, int where)
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static void loongson_pci_pin_quirk(struct pci_dev *pdev)
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{
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unsigned long addroff = 0x0;
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pdev->pin = 1 + (PCI_FUNC(pdev->devfn) & 3);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_DC1, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_DC2, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_GMAC, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_AHCI, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_EHCI, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_GNET, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_HDMI, loongson_pci_pin_quirk);
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if (bus != 0)
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addroff |= BIT(28); /* Type 1 Access */
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addroff |= (where & 0xff) | ((where & 0xf00) << 16);
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addroff |= (bus << 16) | (devfn << 8);
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return priv->cfg1_base + addroff;
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static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
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{
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struct pci_config_window *cfg;
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if (acpi_disabled)
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return (struct loongson_pci *)(bus->sysdata);
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cfg = bus->sysdata;
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return (struct loongson_pci *)(cfg->priv);
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}
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static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
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unsigned int devfn, int where)
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static void __iomem *cfg0_map(struct loongson_pci *priv, struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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unsigned long addroff = 0x0;
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unsigned char busnum = bus->number;
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if (bus != 0)
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if (!pci_is_root_bus(bus)) {
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addroff |= BIT(24); /* Type 1 Access */
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addroff |= (bus << 16) | (devfn << 8) | where;
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addroff |= (busnum << 16);
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}
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addroff |= (devfn << 8) | where;
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return priv->cfg0_base + addroff;
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}
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static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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static void __iomem *cfg1_map(struct loongson_pci *priv, struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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unsigned long addroff = 0x0;
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unsigned char busnum = bus->number;
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struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
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struct loongson_pci *priv = pci_host_bridge_priv(bridge);
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if (!pci_is_root_bus(bus)) {
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addroff |= BIT(28); /* Type 1 Access */
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addroff |= (busnum << 16);
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}
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addroff |= (devfn << 8) | (where & 0xff) | ((where & 0xf00) << 16);
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return priv->cfg1_base + addroff;
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}
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static bool pdev_may_exist(struct pci_bus *bus, unsigned int device,
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unsigned int function)
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{
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return !(pci_is_root_bus(bus) &&
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(device >= 9 && device <= 20) && (function > 0));
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}
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static void __iomem *pci_loongson_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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unsigned int device = PCI_SLOT(devfn);
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unsigned int function = PCI_FUNC(devfn);
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struct loongson_pci *priv = pci_bus_to_loongson_pci(bus);
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/*
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* Do not read more than one device on the bus other than
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* the host bus. For our hardware the root bus is always bus 0.
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* the host bus.
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*/
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if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
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PCI_SLOT(devfn) > 0)
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return NULL;
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if ((priv->data->flags & FLAG_DEV_FIX) && bus->self) {
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if (!pci_is_root_bus(bus) && (device > 0))
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return NULL;
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}
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/* Don't access non-existent devices */
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if (priv->data->flags & FLAG_DEV_HIDDEN) {
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if (!pdev_may_exist(bus, device, function))
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return NULL;
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}
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/* CFG0 can only access standard space */
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if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
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return cfg0_map(priv, busnum, devfn, where);
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return cfg0_map(priv, bus, devfn, where);
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/* CFG1 can access extended space */
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if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
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return cfg1_map(priv, busnum, devfn, where);
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return cfg1_map(priv, bus, devfn, where);
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return NULL;
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}
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#ifdef CONFIG_OF
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static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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@ -159,20 +225,42 @@ static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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return val;
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}
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/* H/w only accept 32-bit PCI operations */
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/* LS2K/LS7A accept 8/16/32-bit PCI config operations */
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static struct pci_ops loongson_pci_ops = {
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.map_bus = pci_loongson_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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/* RS780/SR5690 only accept 32-bit PCI config operations */
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static struct pci_ops loongson_pci_ops32 = {
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.map_bus = pci_loongson_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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};
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static const struct loongson_pci_data ls2k_pci_data = {
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.flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN,
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.ops = &loongson_pci_ops,
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};
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static const struct loongson_pci_data ls7a_pci_data = {
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.flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN,
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.ops = &loongson_pci_ops,
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};
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static const struct loongson_pci_data rs780e_pci_data = {
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.flags = FLAG_CFG0,
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.ops = &loongson_pci_ops32,
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};
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static const struct of_device_id loongson_pci_of_match[] = {
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{ .compatible = "loongson,ls2k-pci",
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.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
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.data = &ls2k_pci_data, },
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{ .compatible = "loongson,ls7a-pci",
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.data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
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.data = &ls7a_pci_data, },
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{ .compatible = "loongson,rs780e-pci",
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.data = (void *)(FLAG_CFG0), },
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.data = &rs780e_pci_data, },
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{}
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};
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@ -193,20 +281,20 @@ static int loongson_pci_probe(struct platform_device *pdev)
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priv = pci_host_bridge_priv(bridge);
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priv->pdev = pdev;
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priv->flags = (unsigned long)of_device_get_match_data(dev);
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priv->data = of_device_get_match_data(dev);
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!regs) {
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dev_err(dev, "missing mem resources for cfg0\n");
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return -EINVAL;
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if (priv->data->flags & FLAG_CFG0) {
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!regs)
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dev_err(dev, "missing mem resources for cfg0\n");
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else {
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priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(priv->cfg0_base))
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return PTR_ERR(priv->cfg0_base);
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}
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}
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priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(priv->cfg0_base))
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return PTR_ERR(priv->cfg0_base);
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/* CFG1 is optional */
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if (priv->flags & FLAG_CFG1) {
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if (priv->data->flags & FLAG_CFG1) {
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!regs)
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dev_info(dev, "missing mem resource for cfg1\n");
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@ -218,7 +306,7 @@ static int loongson_pci_probe(struct platform_device *pdev)
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}
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bridge->sysdata = priv;
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bridge->ops = &loongson_pci_ops;
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bridge->ops = priv->data->ops;
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bridge->map_irq = loongson_map_irq;
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return pci_host_probe(bridge);
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@ -232,3 +320,41 @@ static struct platform_driver loongson_pci_driver = {
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.probe = loongson_pci_probe,
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};
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builtin_platform_driver(loongson_pci_driver);
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#endif
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#ifdef CONFIG_ACPI
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static int loongson_pci_ecam_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct loongson_pci *priv;
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struct loongson_pci_data *data;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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cfg->priv = priv;
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data->flags = FLAG_CFG1 | FLAG_DEV_HIDDEN;
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priv->data = data;
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priv->cfg1_base = cfg->win - (cfg->busr.start << 16);
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return 0;
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}
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const struct pci_ecam_ops loongson_pci_ecam_ops = {
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.bus_shift = 16,
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.init = loongson_pci_ecam_init,
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.pci_ops = {
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.map_bus = pci_loongson_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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}
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};
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#endif
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@ -87,6 +87,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
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extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
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extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
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extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
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extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
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#endif
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#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
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