drm/i915: load boot context at driver init time
According to the bspec for MBCTL: Driver must set bit in the following scenarios: - to realod teh h/w boot context every time it gets loaded through OS - after an FLR clears the register (BIOS won't run afterwards) References: https://bugs.freedesktop.org/show_bug.cgi?id=50237 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3363,6 +3363,9 @@ static void gen6_init_clock_gating(struct drm_device *dev)
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ILK_DPARB_CLK_GATE |
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ILK_DPFD_CLK_GATE);
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I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
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GEN6_MBCTL_ENABLE_BOOT_FETCH);
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for_each_pipe(pipe) {
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I915_WRITE(DSPCNTR(pipe),
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I915_READ(DSPCNTR(pipe)) |
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@ -3441,6 +3444,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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intel_flush_display_plane(dev_priv, pipe);
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}
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I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
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GEN6_MBCTL_ENABLE_BOOT_FETCH);
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gen7_setup_fixed_func_scheduler(dev_priv);
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/* WaDisable4x2SubspanOptimization */
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@ -3484,6 +3490,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
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I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
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GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
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GEN6_MBCTL_ENABLE_BOOT_FETCH);
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/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
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* gating disable must be set. Failure to set it results in
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