Docs: dt: Add PCI MSI map bindings
Currently msi-parent is used by a few bindings to describe the relationship between a PCI root complex and a single MSI controller, but this property does not have a generic binding document. Additionally, msi-parent is insufficient to describe more complex relationships between MSI controllers and devices under a root complex, where devices may be able to target multiple MSI controllers, or where MSI controllers use (non-probeable) sideband information to distinguish devices. This patch adds a generic binding for mapping PCI devices to MSI controllers. This document covers msi-parent, and a new msi-map property (specific to PCI*) which may be used to map devices (identified by their Requester ID) to sideband data for each MSI controller that they may target. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Mark Rutland
Marc Zyngier
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This document describes the generic device tree binding for describing the
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relationship between PCI devices and MSI controllers.
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Each PCI device under a root complex is uniquely identified by its Requester ID
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(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
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Function number.
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For the purpose of this document, when treated as a numeric value, a RID is
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formatted such that:
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* Bits [15:8] are the Bus number.
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* Bits [7:3] are the Device number.
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* Bits [2:0] are the Function number.
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* Any other bits required for padding must be zero.
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MSIs may be distinguished in part through the use of sideband data accompanying
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writes. In the case of PCI devices, this sideband data may be derived from the
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Requester ID. A mechanism is required to associate a device with both the MSI
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controllers it can address, and the sideband data that will be associated with
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its writes to those controllers.
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For generic MSI bindings, see
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Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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PCI root complex
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================
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Optional properties
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-------------------
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- msi-map: Maps a Requester ID to an MSI controller and associated
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msi-specifier data. The property is an arbitrary number of tuples of
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(rid-base,msi-controller,msi-base,length), where:
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* rid-base is a single cell describing the first RID matched by the entry.
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* msi-controller is a single phandle to an MSI controller
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* msi-base is an msi-specifier describing the msi-specifier produced for the
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first RID matched by the entry.
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* length is a single cell describing how many consecutive RIDs are matched
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following the rid-base.
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Any RID r in the interval [rid-base, rid-base + length) is associated with
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the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
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- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped
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to an msi-specifier per the msi-map property.
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- msi-parent: Describes the MSI parent of the root complex itself. Where
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the root complex and MSI controller do not pass sideband data with MSI
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writes, this property may be used to describe the MSI controller(s)
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used by PCI devices under the root complex, if defined as such in the
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binding for the root complex.
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Example (1)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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msi: msi-controller@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-controller";
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msi-controller;
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#msi-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the MSI controller is
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* the RID, identity-mapped.
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*/
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msi-map = <0x0 &msi_a 0x0 0x10000>,
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};
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};
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Example (2)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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msi: msi-controller@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-controller";
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msi-controller;
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#msi-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the MSI controller is
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* the RID, masked to only the device and function bits.
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*/
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msi-map = <0x0 &msi_a 0x0 0x100>,
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msi-map-mask = <0xff>
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};
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};
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Example (3)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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msi: msi-controller@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-controller";
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msi-controller;
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#msi-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the MSI controller is
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* the RID, but the high bit of the bus number is
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* ignored.
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*/
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msi-map = <0x0000 &msi 0x0000 0x8000>,
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<0x8000 &msi 0x0000 0x8000>;
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};
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};
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Example (4)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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msi: msi-controller@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-controller";
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msi-controller;
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#msi-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the MSI controller is
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* the RID, but the high bit of the bus number is
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* negated.
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*/
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msi-map = <0x0000 &msi 0x8000 0x8000>,
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<0x8000 &msi 0x0000 0x8000>;
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};
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};
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Example (5)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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msi_a: msi-controller@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-controller";
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msi-controller;
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#msi-cells = <1>;
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};
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msi_b: msi-controller@b {
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reg = <0xb 0x1>;
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compatible = "vendor,some-controller";
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msi-controller;
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#msi-cells = <1>;
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};
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msi_c: msi-controller@c {
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reg = <0xc 0x1>;
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compatible = "vendor,some-controller";
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msi-controller;
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#msi-cells = <1>;
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};
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pci: pci@c {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to MSI controller a is the
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* RID, but the high bit of the bus number is negated.
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* The sideband data provided to MSI controller b is the
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* RID, identity-mapped.
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* MSI controller c is not addressable.
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*/
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msi-map = <0x0000 &msi_a 0x8000 0x08000>,
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<0x8000 &msi_a 0x0000 0x08000>,
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<0x0000 &msi_b 0x0000 0x10000>;
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};
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};
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