ASoC: atmel-i2s: add driver for the new Atmel I2S controller
This patch adds support for the Atmel I2S controller embedded into sama5d2x SoCs. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cyrille Pitchen
Mark Brown
Родитель
969cc0528e
Коммит
b543e467d1
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@ -88,4 +88,13 @@ config SND_ATMEL_SOC_TSE850_PCM5142
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help
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Say Y if you want to add support for the ASoC driver for the
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Axentia TSE-850 with a PCM5142 codec.
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config SND_ATMEL_SOC_I2S
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tristate "Atmel ASoC driver for boards using I2S"
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depends on OF && (ARCH_AT91 || COMPILE_TEST)
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select SND_SOC_GENERIC_DMAENGINE_PCM
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select REGMAP_MMIO
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help
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Say Y or M if you want to add support for Atmel ASoc driver for boards
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using I2S.
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endif
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@ -3,10 +3,12 @@
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snd-soc-atmel-pcm-pdc-objs := atmel-pcm-pdc.o
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snd-soc-atmel-pcm-dma-objs := atmel-pcm-dma.o
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snd-soc-atmel_ssc_dai-objs := atmel_ssc_dai.o
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snd-soc-atmel-i2s-objs := atmel-i2s.o
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obj-$(CONFIG_SND_ATMEL_SOC_PDC) += snd-soc-atmel-pcm-pdc.o
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obj-$(CONFIG_SND_ATMEL_SOC_DMA) += snd-soc-atmel-pcm-dma.o
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obj-$(CONFIG_SND_ATMEL_SOC_SSC) += snd-soc-atmel_ssc_dai.o
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obj-$(CONFIG_SND_ATMEL_SOC_I2S) += snd-soc-atmel-i2s.o
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# AT91 Machine Support
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snd-soc-sam9g20-wm8731-objs := sam9g20_wm8731.o
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@ -0,0 +1,765 @@
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/*
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* Driver for Atmel I2S controller
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*
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* Copyright (C) 2015 Atmel Corporation
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*
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* Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#define ATMEL_I2SC_MAX_TDM_CHANNELS 8
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/*
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* ---- I2S Controller Register map ----
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*/
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#define ATMEL_I2SC_CR 0x0000 /* Control Register */
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#define ATMEL_I2SC_MR 0x0004 /* Mode Register */
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#define ATMEL_I2SC_SR 0x0008 /* Status Register */
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#define ATMEL_I2SC_SCR 0x000c /* Status Clear Register */
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#define ATMEL_I2SC_SSR 0x0010 /* Status Set Register */
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#define ATMEL_I2SC_IER 0x0014 /* Interrupt Enable Register */
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#define ATMEL_I2SC_IDR 0x0018 /* Interrupt Disable Register */
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#define ATMEL_I2SC_IMR 0x001c /* Interrupt Mask Register */
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#define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */
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#define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */
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#define ATMEL_I2SC_VERSION 0x0028 /* Version Register */
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/*
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* ---- Control Register (Write-only) ----
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*/
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#define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */
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#define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */
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#define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */
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#define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */
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#define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */
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#define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */
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#define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */
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/*
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* ---- Mode Register (Read/Write) ----
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*/
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#define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0)
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#define ATMEL_I2SC_MR_MODE_SLAVE (0 << 0)
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#define ATMEL_I2SC_MR_MODE_MASTER (1 << 0)
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#define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2)
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#define ATMEL_I2SC_MR_DATALENGTH_32_BITS (0 << 2)
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#define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2)
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#define ATMEL_I2SC_MR_DATALENGTH_20_BITS (2 << 2)
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#define ATMEL_I2SC_MR_DATALENGTH_18_BITS (3 << 2)
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#define ATMEL_I2SC_MR_DATALENGTH_16_BITS (4 << 2)
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#define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT (5 << 2)
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#define ATMEL_I2SC_MR_DATALENGTH_8_BITS (6 << 2)
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#define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2)
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#define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6)
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#define ATMEL_I2SC_MR_FORMAT_I2S (0 << 6)
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#define ATMEL_I2SC_MR_FORMAT_LJ (1 << 6) /* Left Justified */
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#define ATMEL_I2SC_MR_FORMAT_TDM (2 << 6)
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#define ATMEL_I2SC_MR_FORMAT_TDMLJ (3 << 6)
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/* Left audio samples duplicated to right audio channel */
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#define ATMEL_I2SC_MR_RXMONO BIT(8)
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/* Receiver uses one DMA channel ... */
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#define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9)
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#define ATMEL_I2SC_MR_RXDMA_SINGLE (0 << 9) /* for all audio channels */
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#define ATMEL_I2SC_MR_RXDMA_MULTIPLE (1 << 9) /* per audio channel */
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/* I2SDO output of I2SC is internally connected to I2SDI input */
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#define ATMEL_I2SC_MR_RXLOOP BIT(10)
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/* Left audio samples duplicated to right audio channel */
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#define ATMEL_I2SC_MR_TXMONO BIT(12)
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/* Transmitter uses one DMA channel ... */
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#define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13)
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#define ATMEL_I2SC_MR_TXDMA_SINGLE (0 << 13) /* for all audio channels */
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#define ATMEL_I2SC_MR_TXDME_MULTIPLE (1 << 13) /* per audio channel */
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/* x sample transmitted when underrun */
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#define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14)
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#define ATMEL_I2SC_MR_TXSAME_ZERO (0 << 14) /* Zero sample */
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#define ATMEL_I2SC_MR_TXSAME_PREVIOUS (1 << 14) /* Previous sample */
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/* Audio Clock to I2SC Master Clock ratio */
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#define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16)
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#define ATMEL_I2SC_MR_IMCKDIV(div) \
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(((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK)
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/* Master Clock to fs ratio */
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#define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24)
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#define ATMEL_I2SC_MR_IMCKFS(fs) \
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(((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK)
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/* Master Clock mode */
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#define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30)
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/* 0: No master clock generated (selected clock drives I2SCK pin) */
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#define ATMEL_I2SC_MR_IMCKMODE_I2SCK (0 << 30)
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/* 1: master clock generated (internally generated clock drives I2SMCK pin) */
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#define ATMEL_I2SC_MR_IMCKMODE_I2SMCK (1 << 30)
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/* Slot Width */
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/* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
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/* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
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#define ATMEL_I2SC_MR_IWS BIT(31)
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/*
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* ---- Status Registers ----
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*/
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#define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */
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#define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */
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#define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */
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#define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */
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#define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */
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#define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */
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/* Receive Overrun Channel */
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#define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8)
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#define ATMEL_I2SC_SR_RXORCH(ch) (1 << (((ch) & 0x7) + 8))
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/* Transmit Underrun Channel */
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#define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20)
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#define ATMEL_I2SC_SR_TXURCH(ch) (1 << (((ch) & 0x7) + 20))
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/*
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* ---- Interrupt Enable/Disable/Mask Registers ----
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*/
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#define ATMEL_I2SC_INT_RXRDY ATMEL_I2SC_SR_RXRDY
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#define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR
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#define ATMEL_I2SC_INT_TXRDY ATMEL_I2SC_SR_TXRDY
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#define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR
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static const struct regmap_config atmel_i2s_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = ATMEL_I2SC_VERSION,
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};
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struct atmel_i2s_gck_param {
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int fs;
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unsigned long mck;
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int imckdiv;
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int imckfs;
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};
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#define I2S_MCK_12M288 12288000UL
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#define I2S_MCK_11M2896 11289600UL
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/* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */
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static const struct atmel_i2s_gck_param gck_params[] = {
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/* mck = 12.288MHz */
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{ 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */
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{ 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */
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{ 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */
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{ 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */
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{ 48000, I2S_MCK_12M288, 7, 63}, /* mck = 256 fs */
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{ 64000, I2S_MCK_12M288, 7, 47}, /* mck = 192 fs */
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{ 96000, I2S_MCK_12M288, 7, 31}, /* mck = 128 fs */
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{192000, I2S_MCK_12M288, 7, 15}, /* mck = 64 fs */
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/* mck = 11.2896MHz */
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{ 11025, I2S_MCK_11M2896, 1, 63}, /* mck = 1024 fs */
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{ 22050, I2S_MCK_11M2896, 3, 63}, /* mck = 512 fs */
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{ 44100, I2S_MCK_11M2896, 7, 63}, /* mck = 256 fs */
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{ 88200, I2S_MCK_11M2896, 7, 31}, /* mck = 128 fs */
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{176400, I2S_MCK_11M2896, 7, 15}, /* mck = 64 fs */
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};
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struct atmel_i2s_dev;
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struct atmel_i2s_caps {
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int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np);
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};
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struct atmel_i2s_dev {
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struct device *dev;
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struct regmap *regmap;
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struct clk *pclk;
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struct clk *gclk;
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struct clk *aclk;
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struct snd_dmaengine_dai_dma_data playback;
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struct snd_dmaengine_dai_dma_data capture;
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unsigned int fmt;
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const struct atmel_i2s_gck_param *gck_param;
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const struct atmel_i2s_caps *caps;
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};
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static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id)
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{
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struct atmel_i2s_dev *dev = dev_id;
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unsigned int sr, imr, pending, ch, mask;
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irqreturn_t ret = IRQ_NONE;
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regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
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regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr);
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pending = sr & imr;
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if (!pending)
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return IRQ_NONE;
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if (pending & ATMEL_I2SC_INT_RXOR) {
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mask = ATMEL_I2SC_SR_RXOR;
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for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
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if (sr & ATMEL_I2SC_SR_RXORCH(ch)) {
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mask |= ATMEL_I2SC_SR_RXORCH(ch);
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dev_err(dev->dev,
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"RX overrun on channel %d\n", ch);
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}
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}
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regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
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ret = IRQ_HANDLED;
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}
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if (pending & ATMEL_I2SC_INT_TXUR) {
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mask = ATMEL_I2SC_SR_TXUR;
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for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
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if (sr & ATMEL_I2SC_SR_TXURCH(ch)) {
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mask |= ATMEL_I2SC_SR_TXURCH(ch);
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dev_err(dev->dev,
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"TX underrun on channel %d\n", ch);
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}
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}
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regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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#define ATMEL_I2S_RATES SNDRV_PCM_RATE_8000_192000
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#define ATMEL_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S18_3LE | \
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SNDRV_PCM_FMTBIT_S20_3LE | \
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SNDRV_PCM_FMTBIT_S24_3LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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dev->fmt = fmt;
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return 0;
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}
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static int atmel_i2s_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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unsigned int rhr, sr = 0;
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if (is_playback) {
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regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
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if (sr & ATMEL_I2SC_SR_RXRDY) {
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/*
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* The RX Ready flag should not be set. However if here,
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* we flush (read) the Receive Holding Register to start
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* from a clean state.
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*/
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dev_dbg(dev->dev, "RXRDY is set\n");
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regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr);
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}
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}
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return 0;
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}
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static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs)
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{
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int i, best;
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if (!dev->gclk || !dev->aclk) {
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dev_err(dev->dev, "cannot generate the I2S Master Clock\n");
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return -EINVAL;
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}
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/*
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* Find the best possible settings to generate the I2S Master Clock
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* from the PLL Audio.
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*/
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dev->gck_param = NULL;
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best = INT_MAX;
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for (i = 0; i < ARRAY_SIZE(gck_params); ++i) {
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const struct atmel_i2s_gck_param *gck_param = &gck_params[i];
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int val = abs(fs - gck_param->fs);
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if (val < best) {
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best = val;
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dev->gck_param = gck_param;
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}
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}
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return 0;
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}
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static int atmel_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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unsigned int mr = 0;
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int ret;
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switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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mr |= ATMEL_I2SC_MR_FORMAT_I2S;
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break;
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default:
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dev_err(dev->dev, "unsupported bus format\n");
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return -EINVAL;
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}
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switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* codec is slave, so cpu is master */
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mr |= ATMEL_I2SC_MR_MODE_MASTER;
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ret = atmel_i2s_get_gck_param(dev, params_rate(params));
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if (ret)
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return ret;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
|
||||
/* codec is master, so cpu is slave */
|
||||
mr |= ATMEL_I2SC_MR_MODE_SLAVE;
|
||||
dev->gck_param = NULL;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(dev->dev, "unsupported master/slave mode\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (params_channels(params)) {
|
||||
case 1:
|
||||
if (is_playback)
|
||||
mr |= ATMEL_I2SC_MR_TXMONO;
|
||||
else
|
||||
mr |= ATMEL_I2SC_MR_RXMONO;
|
||||
break;
|
||||
case 2:
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "unsupported number of audio channels\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S8:
|
||||
mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S18_3LE:
|
||||
mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S20_3LE:
|
||||
mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S24_3LE:
|
||||
mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return regmap_write(dev->regmap, ATMEL_I2SC_MR, mr);
|
||||
}
|
||||
|
||||
static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev,
|
||||
bool enabled)
|
||||
{
|
||||
unsigned int mr, mr_mask;
|
||||
unsigned long aclk_rate;
|
||||
int ret;
|
||||
|
||||
mr = 0;
|
||||
mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK |
|
||||
ATMEL_I2SC_MR_IMCKFS_MASK |
|
||||
ATMEL_I2SC_MR_IMCKMODE_MASK);
|
||||
|
||||
if (!enabled) {
|
||||
/* Disable the I2S Master Clock generator. */
|
||||
ret = regmap_write(dev->regmap, ATMEL_I2SC_CR,
|
||||
ATMEL_I2SC_CR_CKDIS);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Reset the I2S Master Clock generator settings. */
|
||||
ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR,
|
||||
mr_mask, mr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Disable/unprepare the PMC generated clock. */
|
||||
clk_disable_unprepare(dev->gclk);
|
||||
|
||||
/* Disable/unprepare the PLL audio clock. */
|
||||
clk_disable_unprepare(dev->aclk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!dev->gck_param)
|
||||
return -EINVAL;
|
||||
|
||||
aclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1);
|
||||
|
||||
/* Fist change the PLL audio clock frequency ... */
|
||||
ret = clk_set_rate(dev->aclk, aclk_rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* ... then set the PMC generated clock rate to the very same frequency
|
||||
* to set the gclk parent to aclk.
|
||||
*/
|
||||
ret = clk_set_rate(dev->gclk, aclk_rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Prepare and enable the PLL audio clock first ... */
|
||||
ret = clk_prepare_enable(dev->aclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* ... then prepare and enable the PMC generated clock. */
|
||||
ret = clk_prepare_enable(dev->gclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Update the Mode Register to generate the I2S Master Clock. */
|
||||
mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv);
|
||||
mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs);
|
||||
mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK;
|
||||
ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Finally enable the I2S Master Clock generator. */
|
||||
return regmap_write(dev->regmap, ATMEL_I2SC_CR,
|
||||
ATMEL_I2SC_CR_CKEN);
|
||||
}
|
||||
|
||||
static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
|
||||
bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
|
||||
bool is_master, mck_enabled;
|
||||
unsigned int cr, mr;
|
||||
int err;
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN;
|
||||
mck_enabled = true;
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS;
|
||||
mck_enabled = false;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Read the Mode Register to retrieve the master/slave state. */
|
||||
err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr);
|
||||
if (err)
|
||||
return err;
|
||||
is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER;
|
||||
|
||||
/* If master starts, enable the audio clock. */
|
||||
if (is_master && mck_enabled)
|
||||
err = atmel_i2s_switch_mck_generator(dev, true);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* If master stops, disable the audio clock. */
|
||||
if (is_master && !mck_enabled)
|
||||
err = atmel_i2s_switch_mck_generator(dev, false);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops atmel_i2s_dai_ops = {
|
||||
.prepare = atmel_i2s_prepare,
|
||||
.trigger = atmel_i2s_trigger,
|
||||
.hw_params = atmel_i2s_hw_params,
|
||||
.set_fmt = atmel_i2s_set_dai_fmt,
|
||||
};
|
||||
|
||||
static int atmel_i2s_dai_probe(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
|
||||
|
||||
snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct snd_soc_dai_driver atmel_i2s_dai = {
|
||||
.probe = atmel_i2s_dai_probe,
|
||||
.playback = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = ATMEL_I2S_RATES,
|
||||
.formats = ATMEL_I2S_FORMATS,
|
||||
},
|
||||
.capture = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = ATMEL_I2S_RATES,
|
||||
.formats = ATMEL_I2S_FORMATS,
|
||||
},
|
||||
.ops = &atmel_i2s_dai_ops,
|
||||
.symmetric_rates = 1,
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver atmel_i2s_component = {
|
||||
.name = "atmel-i2s",
|
||||
};
|
||||
|
||||
static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct clk *muxclk;
|
||||
int err;
|
||||
|
||||
if (!dev->gclk)
|
||||
return 0;
|
||||
|
||||
/* muxclk is optional, so we return error for probe defer only */
|
||||
muxclk = devm_clk_get(dev->dev, "muxclk");
|
||||
if (IS_ERR(muxclk)) {
|
||||
err = PTR_ERR(muxclk);
|
||||
if (err == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
dev_warn(dev->dev,
|
||||
"failed to get the I2S clock control: %d\n", err);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return clk_set_parent(muxclk, dev->gclk);
|
||||
}
|
||||
|
||||
static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = {
|
||||
.mck_init = atmel_i2s_sama5d2_mck_init,
|
||||
};
|
||||
|
||||
static const struct of_device_id atmel_i2s_dt_ids[] = {
|
||||
{
|
||||
.compatible = "atmel,sama5d2-i2s",
|
||||
.data = (void *)&atmel_i2s_sama5d2_caps,
|
||||
},
|
||||
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids);
|
||||
|
||||
static int atmel_i2s_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *match;
|
||||
struct atmel_i2s_dev *dev;
|
||||
struct resource *mem;
|
||||
struct regmap *regmap;
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
int err = -ENXIO;
|
||||
unsigned int pcm_flags = 0;
|
||||
unsigned int version;
|
||||
|
||||
/* Get memory for driver data. */
|
||||
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
|
||||
if (!dev)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Get hardware capabilities. */
|
||||
match = of_match_node(atmel_i2s_dt_ids, np);
|
||||
if (match)
|
||||
dev->caps = match->data;
|
||||
|
||||
/* Map I/O registers. */
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(&pdev->dev, mem);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
||||
&atmel_i2s_regmap_config);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
/* Request IRQ. */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,
|
||||
dev_name(&pdev->dev), dev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Get the peripheral clock. */
|
||||
dev->pclk = devm_clk_get(&pdev->dev, "pclk");
|
||||
if (IS_ERR(dev->pclk)) {
|
||||
err = PTR_ERR(dev->pclk);
|
||||
dev_err(&pdev->dev,
|
||||
"failed to get the peripheral clock: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Get audio clocks to generate the I2S Master Clock (I2S_MCK) */
|
||||
dev->aclk = devm_clk_get(&pdev->dev, "aclk");
|
||||
dev->gclk = devm_clk_get(&pdev->dev, "gclk");
|
||||
if (IS_ERR(dev->aclk) && IS_ERR(dev->gclk)) {
|
||||
if (PTR_ERR(dev->aclk) == -EPROBE_DEFER ||
|
||||
PTR_ERR(dev->gclk) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
/* Master Mode not supported */
|
||||
dev->aclk = NULL;
|
||||
dev->gclk = NULL;
|
||||
} else if (IS_ERR(dev->gclk)) {
|
||||
err = PTR_ERR(dev->gclk);
|
||||
dev_err(&pdev->dev,
|
||||
"failed to get the PMC generated clock: %d\n", err);
|
||||
return err;
|
||||
} else if (IS_ERR(dev->aclk)) {
|
||||
err = PTR_ERR(dev->aclk);
|
||||
dev_err(&pdev->dev,
|
||||
"failed to get the PLL audio clock: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
dev->dev = &pdev->dev;
|
||||
dev->regmap = regmap;
|
||||
platform_set_drvdata(pdev, dev);
|
||||
|
||||
/* Do hardware specific settings to initialize I2S_MCK generator */
|
||||
if (dev->caps && dev->caps->mck_init) {
|
||||
err = dev->caps->mck_init(dev, np);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Enable the peripheral clock. */
|
||||
err = clk_prepare_enable(dev->pclk);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Get IP version. */
|
||||
regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version);
|
||||
dev_info(&pdev->dev, "hw version: %#x\n", version);
|
||||
|
||||
/* Enable error interrupts. */
|
||||
regmap_write(dev->regmap, ATMEL_I2SC_IER,
|
||||
ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR);
|
||||
|
||||
err = devm_snd_soc_register_component(&pdev->dev,
|
||||
&atmel_i2s_component,
|
||||
&atmel_i2s_dai, 1);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
|
||||
clk_disable_unprepare(dev->pclk);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Prepare DMA config. */
|
||||
dev->playback.addr = (dma_addr_t)mem->start + ATMEL_I2SC_THR;
|
||||
dev->playback.maxburst = 1;
|
||||
dev->capture.addr = (dma_addr_t)mem->start + ATMEL_I2SC_RHR;
|
||||
dev->capture.maxburst = 1;
|
||||
|
||||
if (of_property_match_string(np, "dma-names", "rx-tx") == 0)
|
||||
pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX;
|
||||
err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
|
||||
clk_disable_unprepare(dev->pclk);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_i2s_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct atmel_i2s_dev *dev = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(dev->pclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver atmel_i2s_driver = {
|
||||
.driver = {
|
||||
.name = "atmel_i2s",
|
||||
.of_match_table = of_match_ptr(atmel_i2s_dt_ids),
|
||||
},
|
||||
.probe = atmel_i2s_probe,
|
||||
.remove = atmel_i2s_remove,
|
||||
};
|
||||
module_platform_driver(atmel_i2s_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Atmel I2S Controller driver");
|
||||
MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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