Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu into next
Pull m68knommu updates from Greg Ungerer: "Nothing too big, just a handfull of small changes. A couple of dragonball fixes, coldfire qspi cleanup and fixes, and some coldfire gpio cleanup, fixes and extensions" * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68knommu: Implement gpio support for m54xx. m68knommu: Make everything thats not exported, static. m68knommu: setting the gpio data direction register to output doesn't dependent upon the value to output! m68knommu: add to_irq function so we can map gpios to external interrupts. m68knommu: qspi declutter. m68knommu: Fix the 5249/525x qspi base address. m68knommu: Add qspi clk for Coldfire SoCs without real clks. m68k: fix a compiler warning when building for DragonBall m68knommu: Fix mach_sched_init for EZ and VZ DragonBall chips
This commit is contained in:
Коммит
b55a0ff8df
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@ -105,7 +105,7 @@
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/*
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* QSPI module.
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*/
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#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
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#define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */
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#define MCFQSPI_SIZE 0x40 /* Register set size */
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#ifdef CONFIG_M5249
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@ -55,9 +55,15 @@
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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#define MCFGPIO_PODR (MCF_MBAR + 0xA00)
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#define MCFGPIO_PDDR (MCF_MBAR + 0xA10)
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#define MCFGPIO_PPDR (MCF_MBAR + 0xA20)
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#define MCFGPIO_SETR (MCF_MBAR + 0xA20)
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#define MCFGPIO_CLRR (MCF_MBAR + 0xA30)
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#define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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/*
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* EDGE Port support.
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@ -139,7 +139,8 @@ static inline void gpio_free(unsigned gpio)
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#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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/*
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* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
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* read-modify-write to change an output and a GPIO module which has separate
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@ -195,7 +196,8 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
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return MCFSIM2_GPIO1READ;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPPDR;
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@ -237,7 +239,8 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
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return MCFSIM2_GPIO1WRITE;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPDR;
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@ -279,7 +282,8 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
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return MCFSIM2_GPIO1ENABLE;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPDDR;
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@ -58,17 +58,16 @@ void (*mach_halt)(void);
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void (*mach_power_off)(void);
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#ifdef CONFIG_M68000
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#if defined(CONFIG_M68328)
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#define CPU_NAME "MC68328"
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#elif defined(CONFIG_M68EZ328)
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#define CPU_NAME "MC68EZ328"
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#elif defined(CONFIG_M68VZ328)
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#define CPU_NAME "MC68VZ328"
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#else
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#define CPU_NAME "MC68000"
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#endif
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#ifdef CONFIG_M68328
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#define CPU_NAME "MC68328"
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#endif
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#ifdef CONFIG_M68EZ328
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#define CPU_NAME "MC68EZ328"
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#endif
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#ifdef CONFIG_M68VZ328
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#define CPU_NAME "MC68VZ328"
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#endif
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#endif /* CONFIG_M68000 */
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#ifdef CONFIG_M68360
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#define CPU_NAME "MC68360"
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#endif
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@ -69,7 +69,8 @@ void __init config_BSP(char *command, int len)
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if (p) strcpy(p,command);
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else command[0] = 0;
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#endif
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mach_sched_init = hw_timer_init;
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mach_hwclk = m68328_hwclk;
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mach_reset = m68ez328_reset;
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}
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@ -182,6 +182,7 @@ void __init config_BSP(char *command, int size)
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init_hardware(command, size);
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mach_sched_init = hw_timer_init;
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mach_hwclk = m68328_hwclk;
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mach_reset = m68vz328_reset;
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}
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@ -76,10 +76,7 @@ int __mcfgpio_direction_output(unsigned gpio, int value)
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local_irq_save(flags);
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data = mcfgpio_read(__mcfgpio_pddr(gpio));
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if (value)
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data |= mcfgpio_bit(gpio);
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else
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data &= mcfgpio_bit(gpio);
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data |= mcfgpio_bit(gpio);
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mcfgpio_write(data, __mcfgpio_pddr(gpio));
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/* now set the data to output */
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@ -117,37 +114,51 @@ EXPORT_SYMBOL(__mcfgpio_free);
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#ifdef CONFIG_GPIOLIB
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int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset)
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static int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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return __mcfgpio_direction_input(offset);
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}
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int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset)
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static int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset)
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{
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return __mcfgpio_get_value(offset);
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}
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int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
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static int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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return __mcfgpio_direction_output(offset, value);
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}
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void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
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static void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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__mcfgpio_set_value(offset, value);
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}
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int mcfgpio_request(struct gpio_chip *chip, unsigned offset)
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static int mcfgpio_request(struct gpio_chip *chip, unsigned offset)
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{
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return __mcfgpio_request(offset);
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}
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void mcfgpio_free(struct gpio_chip *chip, unsigned offset)
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static void mcfgpio_free(struct gpio_chip *chip, unsigned offset)
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{
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__mcfgpio_free(offset);
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}
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struct bus_type mcfgpio_subsys = {
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static int mcfgpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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#if defined(MCFGPIO_IRQ_MIN)
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if ((offset >= MCFGPIO_IRQ_MIN) && (offset < MCFGPIO_IRQ_MAX))
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#else
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if (offset < MCFGPIO_IRQ_MAX)
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#endif
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return MCFGPIO_IRQ_VECBASE + offset;
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else
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return -EINVAL;
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}
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static struct bus_type mcfgpio_subsys = {
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.name = "gpio",
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.dev_name = "gpio",
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};
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@ -160,6 +171,7 @@ static struct gpio_chip mcfgpio_chip = {
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.direction_output = mcfgpio_direction_output,
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.get = mcfgpio_get_value,
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.set = mcfgpio_set_value,
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.to_irq = mcfgpio_to_irq,
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.base = 0,
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.ngpio = MCFGPIO_PIN_MAX,
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};
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@ -118,10 +118,9 @@ static void __init m520x_clk_init(void)
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/***************************************************************************/
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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static void __init m520x_qspi_init(void)
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{
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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u16 par;
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/* setup Port QS for QSPI with gpio CS control */
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writeb(0x3f, MCF_GPIO_PAR_QSPI);
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@ -129,9 +128,8 @@ static void __init m520x_qspi_init(void)
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par = readw(MCF_GPIO_PAR_UART);
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par &= 0x00ff;
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writew(par, MCF_GPIO_PAR_UART);
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}
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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}
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/***************************************************************************/
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@ -176,9 +174,7 @@ void __init config_BSP(char *commandp, int size)
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m520x_clk_init();
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m520x_uarts_init();
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m520x_fec_init();
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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m520x_qspi_init();
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#endif
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}
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/***************************************************************************/
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@ -32,6 +32,7 @@ DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
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DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
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DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
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DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
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DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
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DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
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struct clk *mcf_clks[] = {
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@ -44,16 +45,16 @@ struct clk *mcf_clks[] = {
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&clk_mcfuart0,
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&clk_mcfuart1,
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&clk_mcfuart2,
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&clk_mcfqspi0,
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&clk_fec0,
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NULL
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};
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/***************************************************************************/
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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static void __init m523x_qspi_init(void)
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{
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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u16 par;
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/* setup QSPS pins for QSPI with gpio CS control */
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@ -62,9 +63,8 @@ static void __init m523x_qspi_init(void)
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par = readw(MCFGPIO_PAR_TIMER);
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par &= 0x3f3f;
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writew(par, MCFGPIO_PAR_TIMER);
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}
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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}
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/***************************************************************************/
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@ -80,9 +80,7 @@ void __init config_BSP(char *commandp, int size)
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{
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mach_sched_init = hw_timer_init;
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m523x_fec_init();
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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m523x_qspi_init();
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#endif
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}
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/***************************************************************************/
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|
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@ -26,6 +26,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
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DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
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DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
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DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
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DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
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struct clk *mcf_clks[] = {
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&clk_pll,
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@ -34,6 +35,7 @@ struct clk *mcf_clks[] = {
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&clk_mcftmr1,
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&clk_mcfuart0,
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&clk_mcfuart1,
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&clk_mcfqspi0,
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NULL
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};
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@ -71,17 +73,15 @@ static struct platform_device *m5249_devices[] __initdata = {
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/***************************************************************************/
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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static void __init m5249_qspi_init(void)
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{
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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/* QSPI irq setup */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
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MCFSIM_QSPIICR);
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mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
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}
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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}
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/***************************************************************************/
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|
@ -110,9 +110,7 @@ void __init config_BSP(char *commandp, int size)
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#ifdef CONFIG_M5249C3
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m5249_smc91x_init();
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#endif
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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m5249_qspi_init();
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#endif
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}
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/***************************************************************************/
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|
|
|
@ -26,6 +26,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
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DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
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DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
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DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
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DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
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struct clk *mcf_clks[] = {
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&clk_pll,
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|
@ -34,6 +35,7 @@ struct clk *mcf_clks[] = {
|
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&clk_mcftmr1,
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&clk_mcfuart0,
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&clk_mcfuart1,
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&clk_mcfqspi0,
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NULL
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};
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|
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|
|
|
@ -39,6 +39,7 @@ DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
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DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
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DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
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DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
|
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DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
|
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DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
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|
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struct clk *mcf_clks[] = {
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|
@ -50,6 +51,7 @@ struct clk *mcf_clks[] = {
|
|||
&clk_mcftmr3,
|
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&clk_mcfuart0,
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&clk_mcfuart1,
|
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&clk_mcfqspi0,
|
||||
&clk_fec0,
|
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NULL
|
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};
|
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|
|
|
@ -33,6 +33,7 @@ DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
|
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DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
|
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DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
|
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DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
|
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DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
|
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DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
|
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DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
|
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|
||||
|
@ -46,6 +47,7 @@ struct clk *mcf_clks[] = {
|
|||
&clk_mcfuart0,
|
||||
&clk_mcfuart1,
|
||||
&clk_mcfuart2,
|
||||
&clk_mcfqspi0,
|
||||
&clk_fec0,
|
||||
&clk_fec1,
|
||||
NULL
|
||||
|
@ -53,10 +55,9 @@ struct clk *mcf_clks[] = {
|
|||
|
||||
/***************************************************************************/
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
|
||||
static void __init m527x_qspi_init(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
#if defined(CONFIG_M5271)
|
||||
u16 par;
|
||||
|
||||
|
@ -70,9 +71,8 @@ static void __init m527x_qspi_init(void)
|
|||
/* setup QSPS pins for QSPI with gpio CS control */
|
||||
writew(0x003e, MCFGPIO_PAR_QSPI);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
|
||||
}
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
|
@ -120,9 +120,7 @@ void __init config_BSP(char *commandp, int size)
|
|||
mach_sched_init = hw_timer_init;
|
||||
m527x_uarts_init();
|
||||
m527x_fec_init();
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
m527x_qspi_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/***************************************************************************/
|
||||
|
|
|
@ -34,6 +34,7 @@ DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
|
|||
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
|
||||
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
|
||||
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
|
||||
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
|
||||
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
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||||
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||||
struct clk *mcf_clks[] = {
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||||
|
@ -46,21 +47,20 @@ struct clk *mcf_clks[] = {
|
|||
&clk_mcfuart0,
|
||||
&clk_mcfuart1,
|
||||
&clk_mcfuart2,
|
||||
&clk_mcfqspi0,
|
||||
&clk_fec0,
|
||||
NULL
|
||||
};
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
|
||||
static void __init m528x_qspi_init(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
/* setup Port QS for QSPI with gpio CS control */
|
||||
__raw_writeb(0x07, MCFGPIO_PQSPAR);
|
||||
}
|
||||
|
||||
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
|
||||
}
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
|
@ -126,9 +126,7 @@ void __init config_BSP(char *commandp, int size)
|
|||
mach_sched_init = hw_timer_init;
|
||||
m528x_uarts_init();
|
||||
m528x_fec_init();
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
m528x_qspi_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/***************************************************************************/
|
||||
|
|
|
@ -166,15 +166,13 @@ static void __init m53xx_clk_init(void)
|
|||
|
||||
/***************************************************************************/
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
|
||||
static void __init m53xx_qspi_init(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
/* setup QSPS pins for QSPI with gpio CS control */
|
||||
writew(0x01f0, MCFGPIO_PAR_QSPI);
|
||||
}
|
||||
|
||||
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
|
||||
}
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
|
@ -219,9 +217,7 @@ void __init config_BSP(char *commandp, int size)
|
|||
m53xx_clk_init();
|
||||
m53xx_uarts_init();
|
||||
m53xx_fec_init();
|
||||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
|
||||
m53xx_qspi_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BDM_DISABLE
|
||||
/*
|
||||
|
|
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