ARM: dts: at91: sama5d2: switch to new clock binding
Switch sama5d2 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Alexandre Belloni
Родитель
dcfc827d44
Коммит
b605578768
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@ -165,7 +165,7 @@
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&flx1_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mikrobus_i2c>;
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atmel,fifo-size = <16>;
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@ -211,7 +211,7 @@
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&flx3_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
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clock-names = "usart";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx3_default>;
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@ -223,7 +223,7 @@
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&flx3_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
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clock-names = "spi_clk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx3_default>;
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@ -240,7 +240,7 @@
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&flx4_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
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clock-names = "usart";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx4_default>;
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@ -252,7 +252,7 @@
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&flx4_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
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clock-names = "spi_clk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>;
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@ -268,7 +268,7 @@
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&flx4_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx4_default>;
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atmel,fifo-size = <16>;
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@ -197,7 +197,7 @@
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&flx0_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx0_default>;
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atmel,fifo-size = <16>;
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@ -258,7 +258,7 @@
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&flx0_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
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clock-names = "usart";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx0_default>;
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@ -313,7 +313,7 @@
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&flx4_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx4_default>;
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atmel,fifo-size = <16>;
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@ -84,7 +84,7 @@
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0x740000 0x1000>;
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clocks = <&mck>;
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clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
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clock-names = "apb_pclk";
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in-ports {
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@ -100,7 +100,7 @@
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x73C000 0x1000>;
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clocks = <&mck>;
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clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
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clock-names = "apb_pclk";
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out-ports {
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@ -154,7 +154,7 @@
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reg = <0x00300000 0x100000
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0xfc02c000 0x400>;
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udphs_clk>, <&utmi>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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@ -281,7 +281,7 @@
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00400000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
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clock-names = "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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@ -290,7 +290,7 @@
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00500000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&utmi>, <&uhphs_clk>;
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clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
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clock-names = "usb_clk", "ehci_clk";
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status = "disabled";
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};
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@ -314,7 +314,7 @@
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0x1 0x0 0x60000000 0x10000000
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0x2 0x0 0x70000000 0x10000000
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0x3 0x0 0x80000000 0x10000000>;
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clocks = <&h32ck>;
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clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
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status = "disabled";
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nand_controller: nand-controller {
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@ -333,7 +333,7 @@
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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@ -342,7 +342,7 @@
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xb0000000 0x300>;
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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@ -362,7 +362,7 @@
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compatible = "atmel,sama5d2-hlcdc";
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reg = <0xf0000000 0x2000>;
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interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
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clock-names = "periph_clk","sys_clk", "slow_clk";
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status = "disabled";
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@ -388,7 +388,7 @@
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compatible = "atmel,sama5d2-isc";
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reg = <0xf0008000 0x4000>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
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clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
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clock-names = "hclock", "iscck", "gck";
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#clock-cells = <0>;
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clock-output-names = "isc-mck";
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@ -398,7 +398,7 @@
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ramc0: ramc@f000c000 {
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compatible = "atmel,sama5d3-ddramc";
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reg = <0xf000c000 0x200>;
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clocks = <&ddrck>, <&mpddr_clk>;
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clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
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clock-names = "ddrck", "mpddr";
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};
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@ -407,7 +407,7 @@
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reg = <0xf0010000 0x1000>;
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interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&dma0_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
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clock-names = "dma_clk";
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};
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@ -417,7 +417,7 @@
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reg = <0xf0004000 0x1000>;
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interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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clocks = <&dma1_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
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clock-names = "dma_clk";
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};
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@ -425,559 +425,9 @@
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compatible = "atmel,sama5d2-pmc", "syscon";
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reg = <0xf0014000 0x160>;
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interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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main_rc_osc: main_rc_osc {
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compatible = "atmel,at91sam9x5-clk-main-rc-osc";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCRCS>;
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clock-frequency = <12000000>;
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clock-accuracy = <100000000>;
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};
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main_osc: main_osc {
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compatible = "atmel,at91rm9200-clk-main-osc";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCS>;
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clocks = <&main_xtal>;
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};
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MOSCSELS>;
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clocks = <&main_rc_osc &main_osc>;
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};
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plla: pllack {
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compatible = "atmel,sama5d3-clk-pll";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_LOCKA>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <12000000 12000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
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};
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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audio_pll_frac: audiopll_fracck {
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compatible = "atmel,sama5d2-clk-audio-pll-frac";
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#clock-cells = <0>;
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clocks = <&main>;
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};
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audio_pll_pad: audiopll_padck {
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compatible = "atmel,sama5d2-clk-audio-pll-pad";
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#clock-cells = <0>;
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clocks = <&audio_pll_frac>;
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};
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audio_pll_pmc: audiopll_pmcck {
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compatible = "atmel,sama5d2-clk-audio-pll-pmc";
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#clock-cells = <0>;
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clocks = <&audio_pll_frac>;
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};
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utmi: utmick {
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compatible = "atmel,at91sam9x5-clk-utmi";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_LOCKU>;
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clocks = <&main>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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interrupt-parent = <&pmc>;
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interrupts = <AT91_PMC_MCKRDY>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
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atmel,clk-output-range = <124000000 166000000>;
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atmel,clk-divisors = <1 2 4 3>;
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};
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h32ck: h32mxck {
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#clock-cells = <0>;
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compatible = "atmel,sama5d4-clk-h32mx";
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clocks = <&mck>;
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};
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usb: usbck {
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compatible = "atmel,at91sam9x5-clk-usb";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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prog: progck {
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compatible = "atmel,at91sam9x5-clk-programmable";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0: prog0 {
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#clock-cells = <0>;
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reg = <0>;
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interrupts = <AT91_PMC_PCKRDY(0)>;
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};
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prog1: prog1 {
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#clock-cells = <0>;
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reg = <1>;
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interrupts = <AT91_PMC_PCKRDY(1)>;
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};
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prog2: prog2 {
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#clock-cells = <0>;
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reg = <2>;
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interrupts = <AT91_PMC_PCKRDY(2)>;
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};
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};
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systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck: ddrck {
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#clock-cells = <0>;
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reg = <2>;
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clocks = <&mck>;
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};
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lcdck: lcdck {
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#clock-cells = <0>;
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reg = <3>;
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clocks = <&mck>;
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};
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uhpck: uhpck {
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#clock-cells = <0>;
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reg = <6>;
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clocks = <&usb>;
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};
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udpck: udpck {
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#clock-cells = <0>;
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reg = <7>;
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clocks = <&usb>;
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};
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pck0: pck0 {
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#clock-cells = <0>;
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reg = <8>;
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clocks = <&prog0>;
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};
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pck1: pck1 {
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#clock-cells = <0>;
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reg = <9>;
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clocks = <&prog1>;
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};
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||||
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pck2: pck2 {
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#clock-cells = <0>;
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reg = <10>;
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clocks = <&prog2>;
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};
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iscck: iscck {
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#clock-cells = <0>;
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reg = <18>;
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clocks = <&mck>;
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};
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};
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periph32ck {
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compatible = "atmel,at91sam9x5-clk-peripheral";
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#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
clocks = <&h32ck>;
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||||
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||||
macb0_clk: macb0_clk {
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||||
#clock-cells = <0>;
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reg = <5>;
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atmel,clk-output-range = <0 83000000>;
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};
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||||
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||||
tdes_clk: tdes_clk {
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||||
#clock-cells = <0>;
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||||
reg = <11>;
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atmel,clk-output-range = <0 83000000>;
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||||
};
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||||
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matrix1_clk: matrix1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <14>;
|
||||
};
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||||
|
||||
hsmc_clk: hsmc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
pioA_clk: pioA_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <18>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
flx0_clk: flx0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <19>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
flx1_clk: flx1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <20>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
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||||
|
||||
flx2_clk: flx2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <21>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
flx3_clk: flx3_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <22>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
flx4_clk: flx4_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <23>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart0_clk: uart0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <24>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart1_clk: uart1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <25>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart2_clk: uart2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <26>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart3_clk: uart3_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <27>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart4_clk: uart4_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <28>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
twi0_clk: twi0_clk {
|
||||
reg = <29>;
|
||||
#clock-cells = <0>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
twi1_clk: twi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <30>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
spi0_clk: spi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <33>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
spi1_clk: spi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <34>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
tcb0_clk: tcb0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <35>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
tcb1_clk: tcb1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <36>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
pwm_clk: pwm_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <38>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
adc_clk: adc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <40>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uhphs_clk: uhphs_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <41>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
udphs_clk: udphs_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <42>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
ssc0_clk: ssc0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <43>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
ssc1_clk: ssc1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <44>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
trng_clk: trng_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <47>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
pdmic_clk: pdmic_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <48>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
securam_clk: securam_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <51>;
|
||||
};
|
||||
|
||||
i2s0_clk: i2s0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <54>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
i2s1_clk: i2s1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <55>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
can0_clk: can0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <56>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
can1_clk: can1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <57>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
classd_clk: classd_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <59>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
};
|
||||
|
||||
periph64ck {
|
||||
compatible = "atmel,at91sam9x5-clk-peripheral";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mck>;
|
||||
|
||||
dma0_clk: dma0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
dma1_clk: dma1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
aes_clk: aes_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
aesb_clk: aesb_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
};
|
||||
|
||||
sha_clk: sha_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <12>;
|
||||
};
|
||||
|
||||
mpddr_clk: mpddr_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <13>;
|
||||
};
|
||||
|
||||
matrix0_clk: matrix0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <15>;
|
||||
};
|
||||
|
||||
sdmmc0_hclk: sdmmc0_hclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <31>;
|
||||
};
|
||||
|
||||
sdmmc1_hclk: sdmmc1_hclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <32>;
|
||||
};
|
||||
|
||||
lcdc_clk: lcdc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <45>;
|
||||
};
|
||||
|
||||
isc_clk: isc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <46>;
|
||||
};
|
||||
|
||||
qspi0_clk: qspi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <52>;
|
||||
};
|
||||
|
||||
qspi1_clk: qspi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <53>;
|
||||
};
|
||||
};
|
||||
|
||||
gck {
|
||||
compatible = "atmel,sama5d2-clk-generated";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
|
||||
|
||||
sdmmc0_gclk: sdmmc0_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <31>;
|
||||
};
|
||||
|
||||
sdmmc1_gclk: sdmmc1_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <32>;
|
||||
};
|
||||
|
||||
tcb0_gclk: tcb0_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <35>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
tcb1_gclk: tcb1_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <36>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
pwm_gclk: pwm_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <38>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
isc_gclk: isc_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <46>;
|
||||
};
|
||||
|
||||
pdmic_gclk: pdmic_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <48>;
|
||||
};
|
||||
|
||||
i2s0_gclk: i2s0_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <54>;
|
||||
};
|
||||
|
||||
i2s1_gclk: i2s1_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <55>;
|
||||
};
|
||||
|
||||
can0_gclk: can0_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <56>;
|
||||
atmel,clk-output-range = <0 80000000>;
|
||||
};
|
||||
|
||||
can1_gclk: can1_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <57>;
|
||||
atmel,clk-output-range = <0 80000000>;
|
||||
};
|
||||
|
||||
classd_gclk: classd_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <59>;
|
||||
atmel,clk-output-range = <0 100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s_clkmux {
|
||||
compatible = "atmel,sama5d2-clk-i2s-mux";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2s0muxck: i2s0_muxclk {
|
||||
clocks = <&i2s0_clk>, <&i2s0_gclk>;
|
||||
#clock-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
i2s1muxck: i2s1_muxclk {
|
||||
clocks = <&i2s1_clk>, <&i2s1_gclk>;
|
||||
#clock-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
#clock-cells = <2>;
|
||||
clocks = <&clk32k>, <&main_xtal>;
|
||||
clock-names = "slow_clk", "main_xtal";
|
||||
};
|
||||
|
||||
qspi0: spi@f0020000 {
|
||||
|
|
@ -985,7 +435,7 @@
|
|||
reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
|
||||
reg-names = "qspi_base", "qspi_mmap";
|
||||
interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&qspi0_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -996,7 +446,7 @@
|
|||
reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
|
||||
reg-names = "qspi_base", "qspi_mmap";
|
||||
interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&qspi1_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -1010,7 +460,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(30))>;
|
||||
dma-names = "tx";
|
||||
clocks = <&sha_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
|
||||
clock-names = "sha_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1026,7 +476,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(27))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&aes_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
|
||||
clock-names = "aes_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1042,7 +492,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(7))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&spi0_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
|
||||
clock-names = "spi_clk";
|
||||
atmel,fifo-size = <16>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1061,7 +511,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(22))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&ssc0_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1074,7 +524,7 @@
|
|||
67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&macb0_clk>, <&macb0_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
|
||||
clock-names = "hclk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1085,7 +535,7 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0xf800c000 0x100>;
|
||||
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&tcb0_clk>, <&clk32k>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
|
||||
clock-names = "t0_clk", "slow_clk";
|
||||
};
|
||||
|
||||
|
|
@ -1095,7 +545,7 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0xf8010000 0x100>;
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&tcb1_clk>, <&clk32k>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
|
||||
clock-names = "t0_clk", "slow_clk";
|
||||
};
|
||||
|
||||
|
|
@ -1103,7 +553,7 @@
|
|||
compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
|
||||
reg = <0xf8014000 0x1000>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
clocks = <&hsmc_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
|
@ -1123,7 +573,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
|
||||
| AT91_XDMAC_DT_PERID(50))>;
|
||||
dma-names = "rx";
|
||||
clocks = <&pdmic_clk>, <&pdmic_gclk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
|
||||
clock-names = "pclk", "gclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1139,7 +589,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(36))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&uart0_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1155,7 +605,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(38))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&uart1_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1171,7 +621,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(40))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&uart2_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1189,7 +639,7 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&twi0_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
|
||||
atmel,fifo-size = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1199,7 +649,7 @@
|
|||
reg = <0xf802c000 0x4000>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&pwm_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
|
||||
};
|
||||
|
||||
sfr: sfr@f8030000 {
|
||||
|
|
@ -1210,7 +660,7 @@
|
|||
flx0: flexcom@f8034000 {
|
||||
compatible = "atmel,sama5d2-flexcom";
|
||||
reg = <0xf8034000 0x200>;
|
||||
clocks = <&flx0_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xf8034000 0x800>;
|
||||
|
|
@ -1220,7 +670,7 @@
|
|||
flx1: flexcom@f8038000 {
|
||||
compatible = "atmel,sama5d2-flexcom";
|
||||
reg = <0xf8038000 0x200>;
|
||||
clocks = <&flx1_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xf8038000 0x800>;
|
||||
|
|
@ -1230,7 +680,7 @@
|
|||
securam: sram@f8044000 {
|
||||
compatible = "atmel,sama5d2-securam", "mmio-sram";
|
||||
reg = <0xf8044000 0x1420>;
|
||||
clocks = <&securam_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xf8044000 0x1420>;
|
||||
|
|
@ -1255,7 +705,7 @@
|
|||
compatible = "atmel,at91sam9260-pit";
|
||||
reg = <0xf8048030 0x10>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
clocks = <&h32ck>;
|
||||
clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
|
||||
};
|
||||
|
||||
watchdog@f8048040 {
|
||||
|
|
@ -1292,10 +742,10 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(32))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&i2s0_clk>, <&i2s0_gclk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
|
||||
clock-names = "pclk", "gclk";
|
||||
assigned-clocks = <&i2s0muxck>;
|
||||
assigned-clock-parents = <&i2s0_gclk>;
|
||||
assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1306,10 +756,10 @@
|
|||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
|
||||
<64 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&can0_clk>, <&can0_gclk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&can0_gclk>;
|
||||
assigned-clock-parents = <&utmi>;
|
||||
assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
|
|
@ -1326,7 +776,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(9))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&spi1_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
|
||||
clock-names = "spi_clk";
|
||||
atmel,fifo-size = <16>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1345,7 +795,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(42))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&uart3_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1361,7 +811,7 @@
|
|||
AT91_XDMAC_DT_PERID(44))>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&uart4_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1369,7 +819,7 @@
|
|||
flx2: flexcom@fc010000 {
|
||||
compatible = "atmel,sama5d2-flexcom";
|
||||
reg = <0xfc010000 0x200>;
|
||||
clocks = <&flx2_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xfc010000 0x800>;
|
||||
|
|
@ -1379,7 +829,7 @@
|
|||
flx3: flexcom@fc014000 {
|
||||
compatible = "atmel,sama5d2-flexcom";
|
||||
reg = <0xfc014000 0x200>;
|
||||
clocks = <&flx3_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xfc014000 0x800>;
|
||||
|
|
@ -1389,7 +839,7 @@
|
|||
flx4: flexcom@fc018000 {
|
||||
compatible = "atmel,sama5d2-flexcom";
|
||||
reg = <0xfc018000 0x200>;
|
||||
clocks = <&flx4_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xfc018000 0x800>;
|
||||
|
|
@ -1400,7 +850,7 @@
|
|||
compatible = "atmel,at91sam9g45-trng";
|
||||
reg = <0xfc01c000 0x100>;
|
||||
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&trng_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
|
||||
};
|
||||
|
||||
aic: interrupt-controller@fc020000 {
|
||||
|
|
@ -1424,7 +874,7 @@
|
|||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&twi1_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
|
||||
atmel,fifo-size = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1433,7 +883,7 @@
|
|||
compatible = "atmel,sama5d2-adc";
|
||||
reg = <0xfc030000 0x100>;
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&adc_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
|
||||
clock-names = "adc_clk";
|
||||
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
|
||||
dma-names = "rx";
|
||||
|
|
@ -1466,7 +916,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
clocks = <&pioA_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
|
||||
};
|
||||
|
||||
secumod@fc040000 {
|
||||
|
|
@ -1485,7 +935,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(29))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&tdes_clk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
|
||||
clock-names = "tdes_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1498,7 +948,7 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(47))>;
|
||||
dma-names = "tx";
|
||||
clocks = <&classd_clk>, <&classd_gclk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
|
||||
clock-names = "pclk", "gclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1514,10 +964,10 @@
|
|||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
||||
AT91_XDMAC_DT_PERID(34))>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&i2s1_clk>, <&i2s1_gclk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
|
||||
clock-names = "pclk", "gclk";
|
||||
assigned-clocks = <&i2s1muxck>;
|
||||
assigned-parrents = <&i2s1_gclk>;
|
||||
assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
|
||||
assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1528,10 +978,10 @@
|
|||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
|
||||
<65 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&can1_clk>, <&can1_gclk>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&can1_gclk>;
|
||||
assigned-clock-parents = <&utmi>;
|
||||
assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
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