KVM: arm/arm64: vgic: Get rid of unnecessary save_maint_int_state
Now when we don't look at the MISR and EISR values anymore, we can get rid of the logic to save them in the GIC save/restore code. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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@ -22,45 +22,6 @@
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu,
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void __iomem *base)
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{
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struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
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u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
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u32 eisr0, eisr1;
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int i;
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bool expect_mi;
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expect_mi = !!(cpu_if->vgic_hcr & GICH_HCR_UIE);
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for (i = 0; i < used_lrs && !expect_mi; i++)
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expect_mi |= (!(cpu_if->vgic_lr[i] & GICH_LR_HW) &&
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(cpu_if->vgic_lr[i] & GICH_LR_EOI));
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if (expect_mi) {
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cpu_if->vgic_misr = readl_relaxed(base + GICH_MISR);
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if (cpu_if->vgic_misr & GICH_MISR_EOI) {
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eisr0 = readl_relaxed(base + GICH_EISR0);
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if (unlikely(used_lrs > 32))
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eisr1 = readl_relaxed(base + GICH_EISR1);
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else
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eisr1 = 0;
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} else {
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eisr0 = eisr1 = 0;
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}
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} else {
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cpu_if->vgic_misr = 0;
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eisr0 = eisr1 = 0;
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}
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#ifdef CONFIG_CPU_BIG_ENDIAN
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cpu_if->vgic_eisr = ((u64)eisr0 << 32) | eisr1;
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#else
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cpu_if->vgic_eisr = ((u64)eisr1 << 32) | eisr0;
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#endif
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}
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static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
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{
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struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
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@ -111,7 +72,6 @@ void __hyp_text __vgic_v2_save_state(struct kvm_vcpu *vcpu)
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if (used_lrs) {
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cpu_if->vgic_apr = readl_relaxed(base + GICH_APR);
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save_maint_int_state(vcpu, base);
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save_elrsr(vcpu, base);
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save_lrs(vcpu, base);
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@ -118,33 +118,6 @@ static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
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}
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}
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static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
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int i;
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bool expect_mi;
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u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
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expect_mi = !!(cpu_if->vgic_hcr & ICH_HCR_UIE);
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for (i = 0; i < used_lrs; i++) {
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expect_mi |= (!(cpu_if->vgic_lr[i] & ICH_LR_HW) &&
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(cpu_if->vgic_lr[i] & ICH_LR_EOI));
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}
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if (expect_mi) {
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cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
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if (cpu_if->vgic_misr & ICH_MISR_EOI)
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cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
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else
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cpu_if->vgic_eisr = 0;
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} else {
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cpu_if->vgic_misr = 0;
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cpu_if->vgic_eisr = 0;
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}
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}
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void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
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@ -168,8 +141,6 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
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val = read_gicreg(ICH_VTR_EL2);
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nr_pri_bits = vtr_to_nr_pri_bits(val);
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save_maint_int_state(vcpu);
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for (i = 0; i <= used_lrs; i++) {
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if (cpu_if->vgic_elrsr & (1 << i))
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cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
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