[SERIAL] Fix status reporting with PL011 serial driver
The receiver status register reports latched error conditions, which must be cleared by writing to it. However, the data register reports unlatched conditions which are associated with the current character. Use the data register to interpret error status rather than the RSR. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Russell King
Родитель
811803c557
Коммит
b63d4f0fb8
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@ -49,7 +49,6 @@
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#include <linux/serial.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/sizes.h>
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#include <asm/hardware/amba.h>
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#include <asm/hardware/clock.h>
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@ -63,7 +62,8 @@
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#define AMBA_ISR_PASS_LIMIT 256
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#define UART_DUMMY_RSR_RX 256
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#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
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#define UART_DUMMY_DR_RX (1 << 16)
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/*
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* We wrap our port structure around the generic uart_port.
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@ -116,7 +116,7 @@ pl011_rx_chars(struct uart_amba_port *uap)
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#endif
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{
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struct tty_struct *tty = uap->port.info->tty;
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unsigned int status, ch, flag, rsr, max_count = 256;
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unsigned int status, ch, flag, max_count = 256;
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status = readw(uap->port.membase + UART01x_FR);
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while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
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@ -129,7 +129,7 @@ pl011_rx_chars(struct uart_amba_port *uap)
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*/
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}
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ch = readw(uap->port.membase + UART01x_DR);
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ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
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flag = TTY_NORMAL;
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uap->port.icount.rx++;
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@ -137,34 +137,33 @@ pl011_rx_chars(struct uart_amba_port *uap)
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* Note that the error handling code is
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* out of the main execution path
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*/
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rsr = readw(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
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if (unlikely(rsr & UART01x_RSR_ANY)) {
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if (rsr & UART01x_RSR_BE) {
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rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
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if (unlikely(ch & UART_DR_ERROR)) {
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if (ch & UART011_DR_BE) {
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ch &= ~(UART011_DR_FE | UART011_DR_PE);
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uap->port.icount.brk++;
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if (uart_handle_break(&uap->port))
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goto ignore_char;
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} else if (rsr & UART01x_RSR_PE)
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} else if (ch & UART011_DR_PE)
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uap->port.icount.parity++;
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else if (rsr & UART01x_RSR_FE)
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else if (ch & UART011_DR_FE)
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uap->port.icount.frame++;
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if (rsr & UART01x_RSR_OE)
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if (ch & UART011_DR_OE)
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uap->port.icount.overrun++;
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rsr &= uap->port.read_status_mask;
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ch &= uap->port.read_status_mask;
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if (rsr & UART01x_RSR_BE)
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if (ch & UART011_DR_BE)
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flag = TTY_BREAK;
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else if (rsr & UART01x_RSR_PE)
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else if (ch & UART011_DR_PE)
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flag = TTY_PARITY;
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else if (rsr & UART01x_RSR_FE)
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else if (ch & UART011_DR_FE)
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flag = TTY_FRAME;
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}
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if (uart_handle_sysrq_char(&uap->port, ch, regs))
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goto ignore_char;
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uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
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uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
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ignore_char:
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status = readw(uap->port.membase + UART01x_FR);
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@ -476,33 +475,33 @@ pl011_set_termios(struct uart_port *port, struct termios *termios,
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*/
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uart_update_timeout(port, termios->c_cflag, baud);
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port->read_status_mask = UART01x_RSR_OE;
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port->read_status_mask = UART011_DR_OE | 255;
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if (termios->c_iflag & INPCK)
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port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
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port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
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if (termios->c_iflag & (BRKINT | PARMRK))
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port->read_status_mask |= UART01x_RSR_BE;
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port->read_status_mask |= UART011_DR_BE;
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/*
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* Characters to ignore
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*/
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port->ignore_status_mask = 0;
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if (termios->c_iflag & IGNPAR)
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port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
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port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
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if (termios->c_iflag & IGNBRK) {
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port->ignore_status_mask |= UART01x_RSR_BE;
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port->ignore_status_mask |= UART011_DR_BE;
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/*
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* If we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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*/
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if (termios->c_iflag & IGNPAR)
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port->ignore_status_mask |= UART01x_RSR_OE;
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port->ignore_status_mask |= UART011_DR_OE;
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}
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/*
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* Ignore all characters if CREAD is not set.
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*/
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if ((termios->c_cflag & CREAD) == 0)
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port->ignore_status_mask |= UART_DUMMY_RSR_RX;
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port->ignore_status_mask |= UART_DUMMY_DR_RX;
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if (UART_ENABLE_MS(port, termios->c_cflag))
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pl011_enable_ms(port);
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@ -50,6 +50,11 @@
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#define UART011_ICR 0x44 /* Interrupt clear register. */
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#define UART011_DMACR 0x48 /* DMA control register. */
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#define UART011_DR_OE (1 << 11)
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#define UART011_DR_BE (1 << 10)
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#define UART011_DR_PE (1 << 9)
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#define UART011_DR_FE (1 << 8)
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#define UART01x_RSR_OE 0x08
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#define UART01x_RSR_BE 0x04
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#define UART01x_RSR_PE 0x02
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