pinctrl: cygnus: add gpio/pinconf driver
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO controller, the chipCommonG GPIO controller, and the always-on GPIO controller. Basic PINCONF configurations such as bias pull up/down, and drive strength are also supported in this driver. Pins from the ASIU GPIO controller can be individually muxed to GPIO function, through interaction with the Cygnus IOMUX controller Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Tested-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Ray Jui
Linus Walleij
Родитель
2dffad825f
Коммит
b64333ce76
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@ -20,6 +20,28 @@ config PINCTRL_BCM2835
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select PINMUX
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select PINCONF
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config PINCTRL_CYGNUS_GPIO
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bool "Broadcom Cygnus GPIO (with PINCONF) driver"
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depends on OF_GPIO && ARCH_BCM_CYGNUS
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select GPIOLIB_IRQCHIP
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select PINCONF
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select GENERIC_PINCONF
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default ARCH_BCM_CYGNUS
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help
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Say yes here to enable the Broadcom Cygnus GPIO driver.
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The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
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GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
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the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are
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supported by this driver.
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All 3 Cygnus GPIO controllers support basic PINCONF functions such
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as bias pull up, pull down, and drive strength configurations, when
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these pins are muxed to GPIO.
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Pins from the ASIU GPIO can be individually muxed to GPIO function,
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through interaction with the Cygnus IOMUX controller.
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config PINCTRL_CYGNUS_MUX
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bool "Broadcom Cygnus IOMUX driver"
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depends on (ARCH_BCM_CYGNUS || COMPILE_TEST)
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@ -2,4 +2,5 @@
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obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
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obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
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obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o
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obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
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@ -0,0 +1,907 @@
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/*
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* Copyright (C) 2014-2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This file contains the Broadcom Cygnus GPIO driver that supports 3
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* GPIO controllers on Cygnus including the ASIU GPIO controller, the
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* chipCommonG GPIO controller, and the always-on GPIO controller. Basic
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* PINCONF such as bias pull up/down, and drive strength are also supported
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* in this driver.
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*
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* Pins from the ASIU GPIO can be individually muxed to GPIO function,
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* through the interaction with the Cygnus IOMUX controller
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/ioport.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "../pinctrl-utils.h"
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#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00
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#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04
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#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08
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#define CYGNUS_GPIO_IN_TYPE_OFFSET 0x0c
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#define CYGNUS_GPIO_INT_DE_OFFSET 0x10
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#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14
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#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18
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#define CYGNUS_GPIO_INT_STAT_OFFSET 0x1c
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#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20
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#define CYGNUS_GPIO_INT_CLR_OFFSET 0x24
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#define CYGNUS_GPIO_PAD_RES_OFFSET 0x34
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#define CYGNUS_GPIO_RES_EN_OFFSET 0x38
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/* drive strength control for ASIU GPIO */
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#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
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/* drive strength control for CCM/CRMU (AON) GPIO */
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#define CYGNUS_GPIO_DRV0_CTRL_OFFSET 0x00
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#define GPIO_BANK_SIZE 0x200
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#define NGPIOS_PER_BANK 32
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#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
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#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
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#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
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#define GPIO_DRV_STRENGTH_BIT_SHIFT 20
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#define GPIO_DRV_STRENGTH_BITS 3
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#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
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/*
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* Cygnus GPIO core
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*
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* @dev: pointer to device
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* @base: I/O register base for Cygnus GPIO controller
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* @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that
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* has the PINCONF support implemented outside of the GPIO block
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* @lock: lock to protect access to I/O registers
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* @gc: GPIO chip
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* @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
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* @pinmux_is_supported: flag to indicate this GPIO controller contains pins
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* that can be individually muxed to GPIO
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* @pctl: pointer to pinctrl_dev
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* @pctldesc: pinctrl descriptor
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*/
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struct cygnus_gpio {
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struct device *dev;
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void __iomem *base;
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void __iomem *io_ctrl;
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spinlock_t lock;
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struct gpio_chip gc;
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unsigned num_banks;
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bool pinmux_is_supported;
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struct pinctrl_dev *pctl;
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struct pinctrl_desc pctldesc;
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};
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static inline struct cygnus_gpio *to_cygnus_gpio(struct gpio_chip *gc)
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{
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return container_of(gc, struct cygnus_gpio, gc);
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}
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/*
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* Mapping from PINCONF pins to GPIO pins is 1-to-1
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*/
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static inline unsigned cygnus_pin_to_gpio(unsigned pin)
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{
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return pin;
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}
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/**
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* cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
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* Cygnus GPIO register
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*
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* @cygnus_gpio: Cygnus GPIO device
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* @reg: register offset
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* @gpio: GPIO pin
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* @set: set or clear
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*/
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static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg,
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unsigned gpio, bool set)
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{
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unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
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unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
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u32 val;
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val = readl(chip->base + offset);
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if (set)
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val |= BIT(shift);
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else
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val &= ~BIT(shift);
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writel(val, chip->base + offset);
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}
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static inline bool cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg,
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unsigned gpio)
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{
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unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
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unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
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return !!(readl(chip->base + offset) & BIT(shift));
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}
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static void cygnus_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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int i, bit;
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chained_irq_enter(irq_chip, desc);
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/* go through the entire GPIO banks and handle all interrupts */
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for (i = 0; i < chip->num_banks; i++) {
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unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
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CYGNUS_GPIO_INT_MSTAT_OFFSET);
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for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
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unsigned pin = NGPIOS_PER_BANK * i + bit;
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int child_irq = irq_find_mapping(gc->irqdomain, pin);
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/*
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* Clear the interrupt before invoking the
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* handler, so we do not leave any window
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*/
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writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
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CYGNUS_GPIO_INT_CLR_OFFSET);
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generic_handle_irq(child_irq);
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}
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}
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chained_irq_exit(irq_chip, desc);
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}
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static void cygnus_gpio_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned gpio = d->hwirq;
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unsigned int offset = CYGNUS_GPIO_REG(gpio,
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CYGNUS_GPIO_INT_CLR_OFFSET);
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unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
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u32 val = BIT(shift);
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writel(val, chip->base + offset);
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}
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/**
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* cygnus_gpio_irq_set_mask - mask/unmask a GPIO interrupt
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*
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* @d: IRQ chip data
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* @unmask: mask/unmask GPIO interrupt
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*/
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static void cygnus_gpio_irq_set_mask(struct irq_data *d, bool unmask)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned gpio = d->hwirq;
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cygnus_set_bit(chip, CYGNUS_GPIO_INT_MSK_OFFSET, gpio, unmask);
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}
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static void cygnus_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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cygnus_gpio_irq_set_mask(d, false);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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static void cygnus_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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cygnus_gpio_irq_set_mask(d, true);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned gpio = d->hwirq;
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bool level_triggered = false;
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bool dual_edge = false;
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bool rising_or_high = false;
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unsigned long flags;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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rising_or_high = true;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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break;
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case IRQ_TYPE_EDGE_BOTH:
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dual_edge = true;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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level_triggered = true;
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rising_or_high = true;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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level_triggered = true;
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break;
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default:
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dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
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type);
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return -EINVAL;
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}
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spin_lock_irqsave(&chip->lock, flags);
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cygnus_set_bit(chip, CYGNUS_GPIO_IN_TYPE_OFFSET, gpio,
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level_triggered);
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cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge);
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cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio,
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rising_or_high);
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev,
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"gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
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gpio, level_triggered, dual_edge, rising_or_high);
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return 0;
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}
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static struct irq_chip cygnus_gpio_irq_chip = {
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.name = "bcm-cygnus-gpio",
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.irq_ack = cygnus_gpio_irq_ack,
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.irq_mask = cygnus_gpio_irq_mask,
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.irq_unmask = cygnus_gpio_irq_unmask,
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.irq_set_type = cygnus_gpio_irq_set_type,
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};
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/*
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* Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO
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*/
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static int cygnus_gpio_request(struct gpio_chip *gc, unsigned offset)
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{
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned gpio = gc->base + offset;
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/* not all Cygnus GPIO pins can be muxed individually */
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if (!chip->pinmux_is_supported)
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return 0;
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return pinctrl_request_gpio(gpio);
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}
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static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset)
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{
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned gpio = gc->base + offset;
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if (!chip->pinmux_is_supported)
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return;
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pinctrl_free_gpio(gpio);
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}
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static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
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{
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, false);
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
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return 0;
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}
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static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
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int val)
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{
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, true);
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cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
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return 0;
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}
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static void cygnus_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
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{
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
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}
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static int cygnus_gpio_get(struct gpio_chip *gc, unsigned gpio)
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{
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struct cygnus_gpio *chip = to_cygnus_gpio(gc);
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unsigned int offset = CYGNUS_GPIO_REG(gpio,
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CYGNUS_GPIO_DATA_IN_OFFSET);
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unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
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return !!(readl(chip->base + offset) & BIT(shift));
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}
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static int cygnus_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return 1;
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}
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/*
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* Only one group: "gpio_grp", since this local pinctrl device only performs
|
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* GPIO specific PINCONF configurations
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*/
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static const char *cygnus_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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return "gpio_grp";
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}
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static const struct pinctrl_ops cygnus_pctrl_ops = {
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.get_groups_count = cygnus_get_groups_count,
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.get_group_name = cygnus_get_group_name,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_free_map = pinctrl_utils_dt_free_map,
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};
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static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio,
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bool disable, bool pull_up)
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{
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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if (disable) {
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cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, false);
|
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} else {
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cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio,
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pull_up);
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cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, true);
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}
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|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cygnus_gpio_get_pull(struct cygnus_gpio *chip, unsigned gpio,
|
||||
bool *disable, bool *pull_up)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
*disable = !cygnus_get_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio);
|
||||
*pull_up = cygnus_get_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio);
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
}
|
||||
|
||||
static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio,
|
||||
unsigned strength)
|
||||
{
|
||||
void __iomem *base;
|
||||
unsigned int i, offset, shift;
|
||||
u32 val;
|
||||
unsigned long flags;
|
||||
|
||||
/* make sure drive strength is supported */
|
||||
if (strength < 2 || strength > 16 || (strength % 2))
|
||||
return -ENOTSUPP;
|
||||
|
||||
if (chip->io_ctrl) {
|
||||
base = chip->io_ctrl;
|
||||
offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET;
|
||||
} else {
|
||||
base = chip->base;
|
||||
offset = CYGNUS_GPIO_REG(gpio,
|
||||
CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET);
|
||||
}
|
||||
|
||||
shift = CYGNUS_GPIO_SHIFT(gpio);
|
||||
|
||||
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
|
||||
strength);
|
||||
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
strength = (strength / 2) - 1;
|
||||
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
|
||||
val = readl(base + offset);
|
||||
val &= ~BIT(shift);
|
||||
val |= ((strength >> i) & 0x1) << shift;
|
||||
writel(val, base + offset);
|
||||
offset += 4;
|
||||
}
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio,
|
||||
u16 *strength)
|
||||
{
|
||||
void __iomem *base;
|
||||
unsigned int i, offset, shift;
|
||||
u32 val;
|
||||
unsigned long flags;
|
||||
|
||||
if (chip->io_ctrl) {
|
||||
base = chip->io_ctrl;
|
||||
offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET;
|
||||
} else {
|
||||
base = chip->base;
|
||||
offset = CYGNUS_GPIO_REG(gpio,
|
||||
CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET);
|
||||
}
|
||||
|
||||
shift = CYGNUS_GPIO_SHIFT(gpio);
|
||||
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
*strength = 0;
|
||||
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
|
||||
val = readl(base + offset) & BIT(shift);
|
||||
val >>= shift;
|
||||
*strength += (val << i);
|
||||
offset += 4;
|
||||
}
|
||||
|
||||
/* convert to mA */
|
||||
*strength = (*strength + 1) * 2;
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
|
||||
unsigned long *config)
|
||||
{
|
||||
struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
|
||||
enum pin_config_param param = pinconf_to_config_param(*config);
|
||||
unsigned gpio = cygnus_pin_to_gpio(pin);
|
||||
u16 arg;
|
||||
bool disable, pull_up;
|
||||
int ret;
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
|
||||
if (disable)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
|
||||
if (!disable && pull_up)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
|
||||
if (!disable && !pull_up)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
ret = cygnus_gpio_get_strength(chip, gpio, &arg);
|
||||
if (ret)
|
||||
return ret;
|
||||
else
|
||||
*config = pinconf_to_config_packed(param, arg);
|
||||
|
||||
return 0;
|
||||
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
|
||||
unsigned long *configs, unsigned num_configs)
|
||||
{
|
||||
struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
|
||||
enum pin_config_param param;
|
||||
u16 arg;
|
||||
unsigned i, gpio = cygnus_pin_to_gpio(pin);
|
||||
int ret = -ENOTSUPP;
|
||||
|
||||
for (i = 0; i < num_configs; i++) {
|
||||
param = pinconf_to_config_param(configs[i]);
|
||||
arg = pinconf_to_config_argument(configs[i]);
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
ret = cygnus_gpio_set_pull(chip, gpio, true, false);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
ret = cygnus_gpio_set_pull(chip, gpio, false, true);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
ret = cygnus_gpio_set_pull(chip, gpio, false, false);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
ret = cygnus_gpio_set_strength(chip, gpio, arg);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(chip->dev, "invalid configuration\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
} /* for each config */
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct pinconf_ops cygnus_pconf_ops = {
|
||||
.is_generic = true,
|
||||
.pin_config_get = cygnus_pin_config_get,
|
||||
.pin_config_set = cygnus_pin_config_set,
|
||||
};
|
||||
|
||||
/*
|
||||
* Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX
|
||||
* pinctrl pin space
|
||||
*/
|
||||
struct cygnus_gpio_pin_range {
|
||||
unsigned offset;
|
||||
unsigned pin_base;
|
||||
unsigned num_pins;
|
||||
};
|
||||
|
||||
#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n }
|
||||
|
||||
/*
|
||||
* Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins
|
||||
*/
|
||||
static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = {
|
||||
CYGNUS_PINRANGE(0, 42, 1),
|
||||
CYGNUS_PINRANGE(1, 44, 3),
|
||||
CYGNUS_PINRANGE(4, 48, 1),
|
||||
CYGNUS_PINRANGE(5, 50, 3),
|
||||
CYGNUS_PINRANGE(8, 126, 1),
|
||||
CYGNUS_PINRANGE(9, 155, 1),
|
||||
CYGNUS_PINRANGE(10, 152, 1),
|
||||
CYGNUS_PINRANGE(11, 154, 1),
|
||||
CYGNUS_PINRANGE(12, 153, 1),
|
||||
CYGNUS_PINRANGE(13, 127, 3),
|
||||
CYGNUS_PINRANGE(16, 140, 1),
|
||||
CYGNUS_PINRANGE(17, 145, 7),
|
||||
CYGNUS_PINRANGE(24, 130, 10),
|
||||
CYGNUS_PINRANGE(34, 141, 4),
|
||||
CYGNUS_PINRANGE(38, 54, 1),
|
||||
CYGNUS_PINRANGE(39, 56, 3),
|
||||
CYGNUS_PINRANGE(42, 60, 3),
|
||||
CYGNUS_PINRANGE(45, 64, 3),
|
||||
CYGNUS_PINRANGE(48, 68, 2),
|
||||
CYGNUS_PINRANGE(50, 84, 6),
|
||||
CYGNUS_PINRANGE(56, 94, 6),
|
||||
CYGNUS_PINRANGE(62, 72, 1),
|
||||
CYGNUS_PINRANGE(63, 70, 1),
|
||||
CYGNUS_PINRANGE(64, 80, 1),
|
||||
CYGNUS_PINRANGE(65, 74, 3),
|
||||
CYGNUS_PINRANGE(68, 78, 1),
|
||||
CYGNUS_PINRANGE(69, 82, 1),
|
||||
CYGNUS_PINRANGE(70, 156, 17),
|
||||
CYGNUS_PINRANGE(87, 104, 12),
|
||||
CYGNUS_PINRANGE(99, 102, 2),
|
||||
CYGNUS_PINRANGE(101, 90, 4),
|
||||
CYGNUS_PINRANGE(105, 116, 10),
|
||||
CYGNUS_PINRANGE(123, 11, 1),
|
||||
CYGNUS_PINRANGE(124, 38, 4),
|
||||
CYGNUS_PINRANGE(128, 43, 1),
|
||||
CYGNUS_PINRANGE(129, 47, 1),
|
||||
CYGNUS_PINRANGE(130, 49, 1),
|
||||
CYGNUS_PINRANGE(131, 53, 1),
|
||||
CYGNUS_PINRANGE(132, 55, 1),
|
||||
CYGNUS_PINRANGE(133, 59, 1),
|
||||
CYGNUS_PINRANGE(134, 63, 1),
|
||||
CYGNUS_PINRANGE(135, 67, 1),
|
||||
CYGNUS_PINRANGE(136, 71, 1),
|
||||
CYGNUS_PINRANGE(137, 73, 1),
|
||||
CYGNUS_PINRANGE(138, 77, 1),
|
||||
CYGNUS_PINRANGE(139, 79, 1),
|
||||
CYGNUS_PINRANGE(140, 81, 1),
|
||||
CYGNUS_PINRANGE(141, 83, 1),
|
||||
CYGNUS_PINRANGE(142, 10, 1)
|
||||
};
|
||||
|
||||
/*
|
||||
* The Cygnus IOMUX controller mainly supports group based mux configuration,
|
||||
* but certain pins can be muxed to GPIO individually. Only the ASIU GPIO
|
||||
* controller can support this, so it's an optional configuration
|
||||
*
|
||||
* Return -ENODEV means no support and that's fine
|
||||
*/
|
||||
static int cygnus_gpio_pinmux_add_range(struct cygnus_gpio *chip)
|
||||
{
|
||||
struct device_node *node = chip->dev->of_node;
|
||||
struct device_node *pinmux_node;
|
||||
struct platform_device *pinmux_pdev;
|
||||
struct gpio_chip *gc = &chip->gc;
|
||||
int i, ret = 0;
|
||||
|
||||
/* parse DT to find the phandle to the pinmux controller */
|
||||
pinmux_node = of_parse_phandle(node, "pinmux", 0);
|
||||
if (!pinmux_node)
|
||||
return -ENODEV;
|
||||
|
||||
pinmux_pdev = of_find_device_by_node(pinmux_node);
|
||||
/* no longer need the pinmux node */
|
||||
of_node_put(pinmux_node);
|
||||
if (!pinmux_pdev) {
|
||||
dev_err(chip->dev, "failed to get pinmux device\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* now need to create the mapping between local GPIO and PINMUX pins */
|
||||
for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) {
|
||||
ret = gpiochip_add_pin_range(gc, dev_name(&pinmux_pdev->dev),
|
||||
cygnus_gpio_pintable[i].offset,
|
||||
cygnus_gpio_pintable[i].pin_base,
|
||||
cygnus_gpio_pintable[i].num_pins);
|
||||
if (ret) {
|
||||
dev_err(chip->dev, "unable to add GPIO pin range\n");
|
||||
goto err_put_device;
|
||||
}
|
||||
}
|
||||
|
||||
chip->pinmux_is_supported = true;
|
||||
|
||||
/* no need for pinmux_pdev device reference anymore */
|
||||
put_device(&pinmux_pdev->dev);
|
||||
return 0;
|
||||
|
||||
err_put_device:
|
||||
put_device(&pinmux_pdev->dev);
|
||||
gpiochip_remove_pin_ranges(gc);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Cygnus GPIO controller supports some PINCONF related configurations such as
|
||||
* pull up, pull down, and drive strength, when the pin is configured to GPIO
|
||||
*
|
||||
* Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
|
||||
* local GPIO pins
|
||||
*/
|
||||
static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip)
|
||||
{
|
||||
struct pinctrl_desc *pctldesc = &chip->pctldesc;
|
||||
struct pinctrl_pin_desc *pins;
|
||||
struct gpio_chip *gc = &chip->gc;
|
||||
int i;
|
||||
|
||||
pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < gc->ngpio; i++) {
|
||||
pins[i].number = i;
|
||||
pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
|
||||
"gpio-%d", i);
|
||||
if (!pins[i].name)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pctldesc->name = dev_name(chip->dev);
|
||||
pctldesc->pctlops = &cygnus_pctrl_ops;
|
||||
pctldesc->pins = pins;
|
||||
pctldesc->npins = gc->ngpio;
|
||||
pctldesc->confops = &cygnus_pconf_ops;
|
||||
|
||||
chip->pctl = pinctrl_register(pctldesc, chip->dev, chip);
|
||||
if (!chip->pctl) {
|
||||
dev_err(chip->dev, "unable to register pinctrl device\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip)
|
||||
{
|
||||
if (chip->pctl)
|
||||
pinctrl_unregister(chip->pctl);
|
||||
}
|
||||
|
||||
struct cygnus_gpio_data {
|
||||
unsigned num_gpios;
|
||||
};
|
||||
|
||||
static const struct cygnus_gpio_data cygnus_cmm_gpio_data = {
|
||||
.num_gpios = 24,
|
||||
};
|
||||
|
||||
static const struct cygnus_gpio_data cygnus_asiu_gpio_data = {
|
||||
.num_gpios = 146,
|
||||
};
|
||||
|
||||
static const struct cygnus_gpio_data cygnus_crmu_gpio_data = {
|
||||
.num_gpios = 6,
|
||||
};
|
||||
|
||||
static const struct of_device_id cygnus_gpio_of_match[] = {
|
||||
{
|
||||
.compatible = "brcm,cygnus-ccm-gpio",
|
||||
.data = &cygnus_cmm_gpio_data,
|
||||
},
|
||||
{
|
||||
.compatible = "brcm,cygnus-asiu-gpio",
|
||||
.data = &cygnus_asiu_gpio_data,
|
||||
},
|
||||
{
|
||||
.compatible = "brcm,cygnus-crmu-gpio",
|
||||
.data = &cygnus_crmu_gpio_data,
|
||||
}
|
||||
};
|
||||
|
||||
static int cygnus_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
struct cygnus_gpio *chip;
|
||||
struct gpio_chip *gc;
|
||||
u32 ngpios;
|
||||
int irq, ret;
|
||||
const struct of_device_id *match;
|
||||
const struct cygnus_gpio_data *gpio_data;
|
||||
|
||||
match = of_match_device(cygnus_gpio_of_match, dev);
|
||||
if (!match)
|
||||
return -ENODEV;
|
||||
gpio_data = match->data;
|
||||
ngpios = gpio_data->num_gpios;
|
||||
|
||||
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->dev = dev;
|
||||
platform_set_drvdata(pdev, chip);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
chip->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(chip->base)) {
|
||||
dev_err(dev, "unable to map I/O memory\n");
|
||||
return PTR_ERR(chip->base);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (res) {
|
||||
chip->io_ctrl = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(chip->io_ctrl)) {
|
||||
dev_err(dev, "unable to map I/O memory\n");
|
||||
return PTR_ERR(chip->io_ctrl);
|
||||
}
|
||||
}
|
||||
|
||||
spin_lock_init(&chip->lock);
|
||||
|
||||
gc = &chip->gc;
|
||||
gc->base = -1;
|
||||
gc->ngpio = ngpios;
|
||||
chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
|
||||
gc->label = dev_name(dev);
|
||||
gc->dev = dev;
|
||||
gc->of_node = dev->of_node;
|
||||
gc->request = cygnus_gpio_request;
|
||||
gc->free = cygnus_gpio_free;
|
||||
gc->direction_input = cygnus_gpio_direction_input;
|
||||
gc->direction_output = cygnus_gpio_direction_output;
|
||||
gc->set = cygnus_gpio_set;
|
||||
gc->get = cygnus_gpio_get;
|
||||
|
||||
ret = gpiochip_add(gc);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "unable to add GPIO chip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = cygnus_gpio_pinmux_add_range(chip);
|
||||
if (ret && ret != -ENODEV) {
|
||||
dev_err(dev, "unable to add GPIO pin range\n");
|
||||
goto err_rm_gpiochip;
|
||||
}
|
||||
|
||||
ret = cygnus_gpio_register_pinconf(chip);
|
||||
if (ret) {
|
||||
dev_err(dev, "unable to register pinconf\n");
|
||||
goto err_rm_gpiochip;
|
||||
}
|
||||
|
||||
/* optional GPIO interrupt support */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq) {
|
||||
ret = gpiochip_irqchip_add(gc, &cygnus_gpio_irq_chip, 0,
|
||||
handle_simple_irq, IRQ_TYPE_NONE);
|
||||
if (ret) {
|
||||
dev_err(dev, "no GPIO irqchip\n");
|
||||
goto err_unregister_pinconf;
|
||||
}
|
||||
|
||||
gpiochip_set_chained_irqchip(gc, &cygnus_gpio_irq_chip, irq,
|
||||
cygnus_gpio_irq_handler);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister_pinconf:
|
||||
cygnus_gpio_unregister_pinconf(chip);
|
||||
|
||||
err_rm_gpiochip:
|
||||
gpiochip_remove(gc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver cygnus_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "cygnus-gpio",
|
||||
.of_match_table = cygnus_gpio_of_match,
|
||||
},
|
||||
.probe = cygnus_gpio_probe,
|
||||
};
|
||||
|
||||
static int __init cygnus_gpio_init(void)
|
||||
{
|
||||
return platform_driver_probe(&cygnus_gpio_driver, cygnus_gpio_probe);
|
||||
}
|
||||
arch_initcall_sync(cygnus_gpio_init);
|
||||
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