Merge branch 'netcp'
Murali Karicheri says: ==================== net: Add Keystone NetCP ethernet driver support The Network Coprocessor (NetCP) is a hardware accelerator that processes Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet switch sub-module to send and receive packets. NetCP also includes a packet accelerator (PA) module to perform packet classification operations such as header matching, and packet modification operations such as checksum generation. NetCP can also optionally include a Security Accelerator(SA) capable of performing IPSec operations on ingress/egress packets. Keystone SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates per Ethernet port. Both GBE and XGBE network processors supported using common driver. It is also designed to handle future variants of NetCP. version history --------------- v7->v8 - Reworked comments against v7, related to checker warning. - Patch 2/4 that has all of the driver code in v7 is now split into 3 patches based on functionality so that we have 3 smaller patches review instead of a big patch. - Patch for MAINTAINER is merged to 2/4 along with netcp core driver - Separate patch (3/4) for 1G and (4/4) for 10G - Removed big endian support for initial version (will add it later) v6->v7 - Fixed some minor documentation error and also modified the netcp driver to fix the set* functions to include correct le/be macros. v5->v6 - updated version after incorporating comments [6] from David Miller, David Laight & Geert Uytterhoeven on v5. I would like get this in for v3.19 merge window if the latest version is acceptable. v4->v5 - Sorry to spin v5 quickly but I missed few check-patch warnings which were pointed by Joe Perches(thanks). I folded his changes [5] along with few more check-patch warning fixes. I would like get this in for v3.18 merge window if David is happy with this version. v3->v4 - Couple of fixes in in error path as pointed [4] out by David. Rest of the patches are unchanged from v3. v2->v3 - Update v3 after incorporating Jamal and David Miller's comment/suggestion from earlier versions [1] [2]. After per the discussion here [3], the controversial custom exports have been dropped now. And for future future offload support additions, we will plug into generic frameworks as an when they are available. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
b66a4eaaee
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@ -0,0 +1,197 @@
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This document describes the device tree bindings associated with the
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keystone network coprocessor(NetCP) driver support.
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The network coprocessor (NetCP) is a hardware accelerator that processes
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Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsytem with a ethernet
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switch sub-module to send and receive packets. NetCP also includes a packet
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accelerator (PA) module to perform packet classification operations such as
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header matching, and packet modification operations such as checksum
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generation. NetCP can also optionally include a Security Accelerator (SA)
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capable of performing IPSec operations on ingress/egress packets.
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Keystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which
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includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
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per Ethernet port.
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Keystone NetCP driver has a plug-in module architecture where each of the NetCP
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sub-modules exist as a loadable kernel module which plug in to the netcp core.
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These sub-modules are represented as "netcp-devices" in the dts bindings. It is
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mandatory to have the ethernet switch sub-module for the ethernet interface to
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be operational. Any other sub-module like the PA is optional.
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NetCP Ethernet SubSystem Layout:
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-----------------------------
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NetCP subsystem(10G or 1G)
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-----------------------------
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|
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|-> NetCP Devices -> |
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| |-> GBE/XGBE Switch
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| |
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| |-> Packet Accelerator
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| |
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| |-> Security Accelerator
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|
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|
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|
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|-> NetCP Interfaces -> |
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|-> Ethernet Port 0
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|
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|-> Ethernet Port 1
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|
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|-> Ethernet Port 2
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|
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|-> Ethernet Port 3
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NetCP subsystem properties:
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Required properties:
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- compatible: Should be "ti,netcp-1.0"
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- clocks: phandle to the reference clocks for the subsystem.
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- dma-id: Navigator packet dma instance id.
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Optional properties:
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- reg: register location and the size for the following register
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regions in the specified order.
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- Efuse MAC address register
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- dma-coherent: Present if dma operations are coherent
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- big-endian: Keystone devices can be operated in a mode where the DSP is in
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the big endian mode. In such cases enable this option. This
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option should also be enabled if the ARM is operated in
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big endian mode with the DSP in little endian.
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NetCP device properties: Device specification for NetCP sub-modules.
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1Gb/10Gb (gbe/xgbe) ethernet switch sub-module specifications.
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Required properties:
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- label: Must be "netcp-gbe" for 1Gb & "netcp-xgbe" for 10Gb.
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- reg: register location and the size for the following register
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regions in the specified order.
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- subsystem registers
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- serdes registers
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- tx-channel: the navigator packet dma channel name for tx.
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- tx-queue: the navigator queue number associated with the tx dma channel.
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- interfaces: specification for each of the switch port to be registered as a
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network interface in the stack.
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-- slave-port: Switch port number, 0 based numbering.
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-- link-interface: type of link interface, supported options are
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- mac<->mac auto negotiate mode: 0
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- mac<->phy mode: 1
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- mac<->mac forced mode: 2
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- mac<->fiber mode: 3
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- mac<->phy mode with no mdio: 4
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- 10Gb mac<->phy mode : 10
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- 10Gb mac<->mac forced mode : 11
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----phy-handle: phandle to PHY device
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Optional properties:
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- enable-ale: NetCP driver keeps the address learning feature in the ethernet
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switch module disabled. This attribute is to enable the address
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learning.
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- secondary-slave-ports: specification for each of the switch port not be
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registered as a network interface. NetCP driver
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will only initialize these ports and attach PHY
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driver to them if needed.
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NetCP interface properties: Interface specification for NetCP sub-modules.
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Required properties:
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- rx-channel: the navigator packet dma channel name for rx.
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- rx-queue: the navigator queue number associated with rx dma channel.
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- rx-pool: specifies the number of descriptors to be used & the region-id
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for creating the rx descriptor pool.
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- tx-pool: specifies the number of descriptors to be used & the region-id
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for creating the tx descriptor pool.
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- rx-queue-depth: number of descriptors in each of the free descriptor
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queue (FDQ) for the pktdma Rx flow. There can be at
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present a maximum of 4 queues per Rx flow.
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- rx-buffer-size: the buffer size for each of the Rx flow FDQ.
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- tx-completion-queue: the navigator queue number where the descriptors are
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recycled after Tx DMA completion.
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Optional properties:
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- efuse-mac: If this is 1, then the MAC address for the interface is
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obtained from the device efuse mac address register
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- local-mac-address: the driver is designed to use the of_get_mac_address api
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only if efuse-mac is 0. When efuse-mac is 0, the MAC
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address is obtained from local-mac-address. If this
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attribute is not present, then the driver will use a
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random MAC address.
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- "netcp-device label": phandle to the device specification for each of NetCP
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sub-module attached to this interface.
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Example binding:
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netcp: netcp@2090000 {
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reg = <0x2620110 0x8>;
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reg-names = "efuse";
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compatible = "ti,netcp-1.0";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
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dma-coherent;
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/* big-endian; */
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dma-id = <0>;
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netcp-devices {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gbe@0x2090000 {
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label = "netcp-gbe";
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reg = <0x2090000 0xf00>;
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/* enable-ale; */
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tx-queue = <648>;
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tx-channel = <8>;
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interfaces {
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gbe0: interface-0 {
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slave-port = <0>;
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link-interface = <4>;
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};
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gbe1: interface-1 {
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slave-port = <1>;
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link-interface = <4>;
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};
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};
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secondary-slave-ports {
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port-2 {
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slave-port = <2>;
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link-interface = <2>;
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};
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port-3 {
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slave-port = <3>;
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link-interface = <2>;
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};
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};
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};
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};
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netcp-interfaces {
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interface-0 {
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rx-channel = <22>;
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rx-pool = <1024 12>;
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tx-pool = <1024 12>;
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rx-queue-depth = <128 128 0 0>;
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rx-buffer-size = <1518 4096 0 0>;
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rx-queue = <8704>;
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tx-completion-queue = <8706>;
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efuse-mac = <1>;
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netcp-gbe = <&gbe0>;
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};
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interface-1 {
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rx-channel = <23>;
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rx-pool = <1024 12>;
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tx-pool = <1024 12>;
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rx-queue-depth = <128 128 0 0>;
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rx-buffer-size = <1518 4096 0 0>;
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rx-queue = <8705>;
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tx-completion-queue = <8707>;
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efuse-mac = <0>;
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local-mac-address = [02 18 31 7e 3e 6f];
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netcp-gbe = <&gbe1>;
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};
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};
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};
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@ -9609,6 +9609,13 @@ F: drivers/power/lp8788-charger.c
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F: drivers/regulator/lp8788-*.c
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F: include/linux/mfd/lp8788*.h
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TI NETCP ETHERNET DRIVER
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M: Wingman Kwok <w-kwok2@ti.com>
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M: Murali Karicheri <m-karicheri2@ti.com>
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L: netdev@vger.kernel.org
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S: Maintained
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F: drivers/net/ethernet/ti/netcp*
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TI TWL4030 SERIES SOC CODEC DRIVER
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M: Peter Ujfalusi <peter.ujfalusi@ti.com>
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L: alsa-devel@alsa-project.org (moderated for non-subscribers)
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@ -73,12 +73,23 @@ config TI_CPSW
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config TI_CPTS
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boolean "TI Common Platform Time Sync (CPTS) Support"
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depends on TI_CPSW
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depends on TI_CPSW || TI_KEYSTONE_NET
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select PTP_1588_CLOCK
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---help---
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This driver supports the Common Platform Time Sync unit of
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the CPSW Ethernet Switch. The unit can time stamp PTP UDP/IPv4
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and Layer 2 packets, and the driver offers a PTP Hardware Clock.
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config TI_KEYSTONE_NETCP
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tristate "TI Keystone NETCP Ethernet subsystem Support"
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depends on OF
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depends on KEYSTONE_NAVIGATOR_DMA && KEYSTONE_NAVIGATOR_QMSS
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---help---
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This driver supports TI's Keystone NETCP Ethernet subsystem.
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To compile this driver as a module, choose M here: the module
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will be called keystone_netcp.
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config TLAN
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tristate "TI ThunderLAN support"
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depends on (PCI || EISA)
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@ -10,3 +10,7 @@ obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o
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obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o
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obj-$(CONFIG_TI_CPSW) += ti_cpsw.o
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ti_cpsw-y := cpsw_ale.o cpsw.o cpts.o
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obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o
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keystone_netcp-y := netcp_core.o netcp_ethss.o netcp_sgmii.o \
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netcp_xgbepcsr.o cpsw_ale.o cpts.o
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@ -0,0 +1,229 @@
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/*
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* NetCP driver local header
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*
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* Copyright (C) 2014 Texas Instruments Incorporated
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* Authors: Sandeep Nair <sandeep_n@ti.com>
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* Sandeep Paulraj <s-paulraj@ti.com>
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* Cyril Chemparathy <cyril@ti.com>
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Wingman Kwok <w-kwok2@ti.com>
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* Murali Karicheri <m-karicheri2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __NETCP_H__
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#define __NETCP_H__
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#include <linux/netdevice.h>
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#include <linux/soc/ti/knav_dma.h>
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/* Maximum Ethernet frame size supported by Keystone switch */
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#define NETCP_MAX_FRAME_SIZE 9504
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#define SGMII_LINK_MAC_MAC_AUTONEG 0
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#define SGMII_LINK_MAC_PHY 1
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#define SGMII_LINK_MAC_MAC_FORCED 2
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#define SGMII_LINK_MAC_FIBER 3
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#define SGMII_LINK_MAC_PHY_NO_MDIO 4
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#define XGMII_LINK_MAC_PHY 10
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#define XGMII_LINK_MAC_MAC_FORCED 11
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struct netcp_device;
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struct netcp_tx_pipe {
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struct netcp_device *netcp_device;
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void *dma_queue;
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unsigned int dma_queue_id;
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u8 dma_psflags;
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void *dma_channel;
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const char *dma_chan_name;
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};
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#define ADDR_NEW BIT(0)
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#define ADDR_VALID BIT(1)
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enum netcp_addr_type {
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ADDR_ANY,
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ADDR_DEV,
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ADDR_UCAST,
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ADDR_MCAST,
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ADDR_BCAST
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};
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struct netcp_addr {
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struct netcp_intf *netcp;
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unsigned char addr[ETH_ALEN];
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enum netcp_addr_type type;
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unsigned int flags;
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struct list_head node;
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};
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struct netcp_intf {
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struct device *dev;
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struct device *ndev_dev;
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struct net_device *ndev;
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bool big_endian;
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unsigned int tx_compl_qid;
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void *tx_pool;
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struct list_head txhook_list_head;
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unsigned int tx_pause_threshold;
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void *tx_compl_q;
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unsigned int tx_resume_threshold;
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void *rx_queue;
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void *rx_pool;
|
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struct list_head rxhook_list_head;
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unsigned int rx_queue_id;
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void *rx_fdq[KNAV_DMA_FDQ_PER_CHAN];
|
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u32 rx_buffer_sizes[KNAV_DMA_FDQ_PER_CHAN];
|
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struct napi_struct rx_napi;
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struct napi_struct tx_napi;
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|
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void *rx_channel;
|
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const char *dma_chan_name;
|
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u32 rx_pool_size;
|
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u32 rx_pool_region_id;
|
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u32 tx_pool_size;
|
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u32 tx_pool_region_id;
|
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struct list_head module_head;
|
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struct list_head interface_list;
|
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struct list_head addr_list;
|
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bool netdev_registered;
|
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bool primary_module_attached;
|
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|
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/* Lock used for protecting Rx/Tx hook list management */
|
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spinlock_t lock;
|
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struct netcp_device *netcp_device;
|
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struct device_node *node_interface;
|
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|
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/* DMA configuration data */
|
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u32 msg_enable;
|
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u32 rx_queue_depths[KNAV_DMA_FDQ_PER_CHAN];
|
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};
|
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|
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#define NETCP_PSDATA_LEN KNAV_DMA_NUM_PS_WORDS
|
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struct netcp_packet {
|
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struct sk_buff *skb;
|
||||
u32 *epib;
|
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u32 *psdata;
|
||||
unsigned int psdata_len;
|
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struct netcp_intf *netcp;
|
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struct netcp_tx_pipe *tx_pipe;
|
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bool rxtstamp_complete;
|
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void *ts_context;
|
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|
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int (*txtstamp_complete)(void *ctx, struct netcp_packet *pkt);
|
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};
|
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|
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static inline u32 *netcp_push_psdata(struct netcp_packet *p_info,
|
||||
unsigned int bytes)
|
||||
{
|
||||
u32 *buf;
|
||||
unsigned int words;
|
||||
|
||||
if ((bytes & 0x03) != 0)
|
||||
return NULL;
|
||||
words = bytes >> 2;
|
||||
|
||||
if ((p_info->psdata_len + words) > NETCP_PSDATA_LEN)
|
||||
return NULL;
|
||||
|
||||
p_info->psdata_len += words;
|
||||
buf = &p_info->psdata[NETCP_PSDATA_LEN - p_info->psdata_len];
|
||||
return buf;
|
||||
}
|
||||
|
||||
static inline int netcp_align_psdata(struct netcp_packet *p_info,
|
||||
unsigned int byte_align)
|
||||
{
|
||||
int padding;
|
||||
|
||||
switch (byte_align) {
|
||||
case 0:
|
||||
padding = -EINVAL;
|
||||
break;
|
||||
case 1:
|
||||
case 2:
|
||||
case 4:
|
||||
padding = 0;
|
||||
break;
|
||||
case 8:
|
||||
padding = (p_info->psdata_len << 2) % 8;
|
||||
break;
|
||||
case 16:
|
||||
padding = (p_info->psdata_len << 2) % 16;
|
||||
break;
|
||||
default:
|
||||
padding = (p_info->psdata_len << 2) % byte_align;
|
||||
break;
|
||||
}
|
||||
return padding;
|
||||
}
|
||||
|
||||
struct netcp_module {
|
||||
const char *name;
|
||||
struct module *owner;
|
||||
bool primary;
|
||||
|
||||
/* probe/remove: called once per NETCP instance */
|
||||
int (*probe)(struct netcp_device *netcp_device,
|
||||
struct device *device, struct device_node *node,
|
||||
void **inst_priv);
|
||||
int (*remove)(struct netcp_device *netcp_device, void *inst_priv);
|
||||
|
||||
/* attach/release: called once per network interface */
|
||||
int (*attach)(void *inst_priv, struct net_device *ndev,
|
||||
struct device_node *node, void **intf_priv);
|
||||
int (*release)(void *intf_priv);
|
||||
int (*open)(void *intf_priv, struct net_device *ndev);
|
||||
int (*close)(void *intf_priv, struct net_device *ndev);
|
||||
int (*add_addr)(void *intf_priv, struct netcp_addr *naddr);
|
||||
int (*del_addr)(void *intf_priv, struct netcp_addr *naddr);
|
||||
int (*add_vid)(void *intf_priv, int vid);
|
||||
int (*del_vid)(void *intf_priv, int vid);
|
||||
int (*ioctl)(void *intf_priv, struct ifreq *req, int cmd);
|
||||
|
||||
/* used internally */
|
||||
struct list_head module_list;
|
||||
struct list_head interface_list;
|
||||
};
|
||||
|
||||
int netcp_register_module(struct netcp_module *module);
|
||||
void netcp_unregister_module(struct netcp_module *module);
|
||||
void *netcp_module_get_intf_data(struct netcp_module *module,
|
||||
struct netcp_intf *intf);
|
||||
|
||||
int netcp_txpipe_init(struct netcp_tx_pipe *tx_pipe,
|
||||
struct netcp_device *netcp_device,
|
||||
const char *dma_chan_name, unsigned int dma_queue_id);
|
||||
int netcp_txpipe_open(struct netcp_tx_pipe *tx_pipe);
|
||||
int netcp_txpipe_close(struct netcp_tx_pipe *tx_pipe);
|
||||
|
||||
typedef int netcp_hook_rtn(int order, void *data, struct netcp_packet *packet);
|
||||
int netcp_register_txhook(struct netcp_intf *netcp_priv, int order,
|
||||
netcp_hook_rtn *hook_rtn, void *hook_data);
|
||||
int netcp_unregister_txhook(struct netcp_intf *netcp_priv, int order,
|
||||
netcp_hook_rtn *hook_rtn, void *hook_data);
|
||||
int netcp_register_rxhook(struct netcp_intf *netcp_priv, int order,
|
||||
netcp_hook_rtn *hook_rtn, void *hook_data);
|
||||
int netcp_unregister_rxhook(struct netcp_intf *netcp_priv, int order,
|
||||
netcp_hook_rtn *hook_rtn, void *hook_data);
|
||||
void *netcp_device_find_module(struct netcp_device *netcp_device,
|
||||
const char *name);
|
||||
|
||||
/* SGMII functions */
|
||||
int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port);
|
||||
int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port);
|
||||
int netcp_sgmii_config(void __iomem *sgmii_ofs, int port, u32 interface);
|
||||
|
||||
/* XGBE SERDES init functions */
|
||||
int netcp_xgbe_serdes_init(void __iomem *serdes_regs, void __iomem *xgbe_regs);
|
||||
|
||||
#endif /* __NETCP_H__ */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* SGMI module initialisation
|
||||
*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated
|
||||
* Authors: Sandeep Nair <sandeep_n@ti.com>
|
||||
* Sandeep Paulraj <s-paulraj@ti.com>
|
||||
* Wingman Kwok <w-kwok2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "netcp.h"
|
||||
|
||||
#define SGMII_REG_STATUS_LOCK BIT(4)
|
||||
#define SGMII_REG_STATUS_LINK BIT(0)
|
||||
#define SGMII_REG_STATUS_AUTONEG BIT(2)
|
||||
#define SGMII_REG_CONTROL_AUTONEG BIT(0)
|
||||
|
||||
#define SGMII23_OFFSET(x) ((x - 2) * 0x100)
|
||||
#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x)))
|
||||
|
||||
/* SGMII registers */
|
||||
#define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004)
|
||||
#define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010)
|
||||
#define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014)
|
||||
#define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018)
|
||||
|
||||
static void sgmii_write_reg(void __iomem *base, int reg, u32 val)
|
||||
{
|
||||
writel(val, base + reg);
|
||||
}
|
||||
|
||||
static u32 sgmii_read_reg(void __iomem *base, int reg)
|
||||
{
|
||||
return readl(base + reg);
|
||||
}
|
||||
|
||||
static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val)
|
||||
{
|
||||
writel((readl(base + reg) | val), base + reg);
|
||||
}
|
||||
|
||||
/* port is 0 based */
|
||||
int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port)
|
||||
{
|
||||
/* Soft reset */
|
||||
sgmii_write_reg_bit(sgmii_ofs, SGMII_SRESET_REG(port), 0x1);
|
||||
while (sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port)) != 0x0)
|
||||
;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port)
|
||||
{
|
||||
u32 status = 0, link = 0;
|
||||
|
||||
status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
|
||||
if ((status & SGMII_REG_STATUS_LINK) != 0)
|
||||
link = 1;
|
||||
return link;
|
||||
}
|
||||
|
||||
int netcp_sgmii_config(void __iomem *sgmii_ofs, int port, u32 interface)
|
||||
{
|
||||
unsigned int i, status, mask;
|
||||
u32 mr_adv_ability;
|
||||
u32 control;
|
||||
|
||||
switch (interface) {
|
||||
case SGMII_LINK_MAC_MAC_AUTONEG:
|
||||
mr_adv_ability = 0x9801;
|
||||
control = 0x21;
|
||||
break;
|
||||
|
||||
case SGMII_LINK_MAC_PHY:
|
||||
case SGMII_LINK_MAC_PHY_NO_MDIO:
|
||||
mr_adv_ability = 1;
|
||||
control = 1;
|
||||
break;
|
||||
|
||||
case SGMII_LINK_MAC_MAC_FORCED:
|
||||
mr_adv_ability = 0x9801;
|
||||
control = 0x20;
|
||||
break;
|
||||
|
||||
case SGMII_LINK_MAC_FIBER:
|
||||
mr_adv_ability = 0x20;
|
||||
control = 0x1;
|
||||
break;
|
||||
|
||||
default:
|
||||
WARN_ONCE(1, "Invalid sgmii interface: %d\n", interface);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), 0);
|
||||
|
||||
/* Wait for the SerDes pll to lock */
|
||||
for (i = 0; i < 1000; i++) {
|
||||
usleep_range(1000, 2000);
|
||||
status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
|
||||
if ((status & SGMII_REG_STATUS_LOCK) != 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if ((status & SGMII_REG_STATUS_LOCK) == 0)
|
||||
pr_err("serdes PLL not locked\n");
|
||||
|
||||
sgmii_write_reg(sgmii_ofs, SGMII_MRADV_REG(port), mr_adv_ability);
|
||||
sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), control);
|
||||
|
||||
mask = SGMII_REG_STATUS_LINK;
|
||||
if (control & SGMII_REG_CONTROL_AUTONEG)
|
||||
mask |= SGMII_REG_STATUS_AUTONEG;
|
||||
|
||||
for (i = 0; i < 1000; i++) {
|
||||
usleep_range(200, 500);
|
||||
status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
|
||||
if ((status & mask) == mask)
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,501 @@
|
|||
/*
|
||||
* XGE PCSR module initialisation
|
||||
*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated
|
||||
* Authors: Sandeep Nair <sandeep_n@ti.com>
|
||||
* WingMan Kwok <w-kwok2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include "netcp.h"
|
||||
|
||||
/* XGBE registers */
|
||||
#define XGBE_CTRL_OFFSET 0x0c
|
||||
#define XGBE_SGMII_1_OFFSET 0x0114
|
||||
#define XGBE_SGMII_2_OFFSET 0x0214
|
||||
|
||||
/* PCS-R registers */
|
||||
#define PCSR_CPU_CTRL_OFFSET 0x1fd0
|
||||
#define POR_EN BIT(29)
|
||||
|
||||
#define reg_rmw(addr, value, mask) \
|
||||
writel(((readl(addr) & (~(mask))) | \
|
||||
(value & (mask))), (addr))
|
||||
|
||||
/* bit mask of width w at offset s */
|
||||
#define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
|
||||
|
||||
/* shift value v to offset s */
|
||||
#define VAL_SH(v, s) (v << s)
|
||||
|
||||
#define PHY_A(serdes) 0
|
||||
|
||||
struct serdes_cfg {
|
||||
u32 ofs;
|
||||
u32 val;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
static struct serdes_cfg cfg_phyb_1p25g_156p25mhz_cmu0[] = {
|
||||
{0x0000, 0x00800002, 0x00ff00ff},
|
||||
{0x0014, 0x00003838, 0x0000ffff},
|
||||
{0x0060, 0x1c44e438, 0xffffffff},
|
||||
{0x0064, 0x00c18400, 0x00ffffff},
|
||||
{0x0068, 0x17078200, 0xffffff00},
|
||||
{0x006c, 0x00000014, 0x000000ff},
|
||||
{0x0078, 0x0000c000, 0x0000ff00},
|
||||
{0x0000, 0x00000003, 0x000000ff},
|
||||
};
|
||||
|
||||
static struct serdes_cfg cfg_phyb_10p3125g_156p25mhz_cmu1[] = {
|
||||
{0x0c00, 0x00030002, 0x00ff00ff},
|
||||
{0x0c14, 0x00005252, 0x0000ffff},
|
||||
{0x0c28, 0x80000000, 0xff000000},
|
||||
{0x0c2c, 0x000000f6, 0x000000ff},
|
||||
{0x0c3c, 0x04000405, 0xff00ffff},
|
||||
{0x0c40, 0xc0800000, 0xffff0000},
|
||||
{0x0c44, 0x5a202062, 0xffffffff},
|
||||
{0x0c48, 0x40040424, 0xffffffff},
|
||||
{0x0c4c, 0x00004002, 0x0000ffff},
|
||||
{0x0c50, 0x19001c00, 0xff00ff00},
|
||||
{0x0c54, 0x00002100, 0x0000ff00},
|
||||
{0x0c58, 0x00000060, 0x000000ff},
|
||||
{0x0c60, 0x80131e7c, 0xffffffff},
|
||||
{0x0c64, 0x8400cb02, 0xff00ffff},
|
||||
{0x0c68, 0x17078200, 0xffffff00},
|
||||
{0x0c6c, 0x00000016, 0x000000ff},
|
||||
{0x0c74, 0x00000400, 0x0000ff00},
|
||||
{0x0c78, 0x0000c000, 0x0000ff00},
|
||||
{0x0c00, 0x00000003, 0x000000ff},
|
||||
};
|
||||
|
||||
static struct serdes_cfg cfg_phyb_10p3125g_16bit_lane[] = {
|
||||
{0x0204, 0x00000080, 0x000000ff},
|
||||
{0x0208, 0x0000920d, 0x0000ffff},
|
||||
{0x0204, 0xfc000000, 0xff000000},
|
||||
{0x0208, 0x00009104, 0x0000ffff},
|
||||
{0x0210, 0x1a000000, 0xff000000},
|
||||
{0x0214, 0x00006b58, 0x00ffffff},
|
||||
{0x0218, 0x75800084, 0xffff00ff},
|
||||
{0x022c, 0x00300000, 0x00ff0000},
|
||||
{0x0230, 0x00003800, 0x0000ff00},
|
||||
{0x024c, 0x008f0000, 0x00ff0000},
|
||||
{0x0250, 0x30000000, 0xff000000},
|
||||
{0x0260, 0x00000002, 0x000000ff},
|
||||
{0x0264, 0x00000057, 0x000000ff},
|
||||
{0x0268, 0x00575700, 0x00ffff00},
|
||||
{0x0278, 0xff000000, 0xff000000},
|
||||
{0x0280, 0x00500050, 0x00ff00ff},
|
||||
{0x0284, 0x00001f15, 0x0000ffff},
|
||||
{0x028c, 0x00006f00, 0x0000ff00},
|
||||
{0x0294, 0x00000000, 0xffffff00},
|
||||
{0x0298, 0x00002640, 0xff00ffff},
|
||||
{0x029c, 0x00000003, 0x000000ff},
|
||||
{0x02a4, 0x00000f13, 0x0000ffff},
|
||||
{0x02a8, 0x0001b600, 0x00ffff00},
|
||||
{0x0380, 0x00000030, 0x000000ff},
|
||||
{0x03c0, 0x00000200, 0x0000ff00},
|
||||
{0x03cc, 0x00000018, 0x000000ff},
|
||||
{0x03cc, 0x00000000, 0x000000ff},
|
||||
};
|
||||
|
||||
static struct serdes_cfg cfg_phyb_10p3125g_comlane[] = {
|
||||
{0x0a00, 0x00000800, 0x0000ff00},
|
||||
{0x0a84, 0x00000000, 0x000000ff},
|
||||
{0x0a8c, 0x00130000, 0x00ff0000},
|
||||
{0x0a90, 0x77a00000, 0xffff0000},
|
||||
{0x0a94, 0x00007777, 0x0000ffff},
|
||||
{0x0b08, 0x000f0000, 0xffff0000},
|
||||
{0x0b0c, 0x000f0000, 0x00ffffff},
|
||||
{0x0b10, 0xbe000000, 0xff000000},
|
||||
{0x0b14, 0x000000ff, 0x000000ff},
|
||||
{0x0b18, 0x00000014, 0x000000ff},
|
||||
{0x0b5c, 0x981b0000, 0xffff0000},
|
||||
{0x0b64, 0x00001100, 0x0000ff00},
|
||||
{0x0b78, 0x00000c00, 0x0000ff00},
|
||||
{0x0abc, 0xff000000, 0xff000000},
|
||||
{0x0ac0, 0x0000008b, 0x000000ff},
|
||||
};
|
||||
|
||||
static struct serdes_cfg cfg_cm_c1_c2[] = {
|
||||
{0x0208, 0x00000000, 0x00000f00},
|
||||
{0x0208, 0x00000000, 0x0000001f},
|
||||
{0x0204, 0x00000000, 0x00040000},
|
||||
{0x0208, 0x000000a0, 0x000000e0},
|
||||
};
|
||||
|
||||
static void netcp_xgbe_serdes_cmu_init(void __iomem *serdes_regs)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* cmu0 setup */
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_phyb_1p25g_156p25mhz_cmu0); i++) {
|
||||
reg_rmw(serdes_regs + cfg_phyb_1p25g_156p25mhz_cmu0[i].ofs,
|
||||
cfg_phyb_1p25g_156p25mhz_cmu0[i].val,
|
||||
cfg_phyb_1p25g_156p25mhz_cmu0[i].mask);
|
||||
}
|
||||
|
||||
/* cmu1 setup */
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_156p25mhz_cmu1); i++) {
|
||||
reg_rmw(serdes_regs + cfg_phyb_10p3125g_156p25mhz_cmu1[i].ofs,
|
||||
cfg_phyb_10p3125g_156p25mhz_cmu1[i].val,
|
||||
cfg_phyb_10p3125g_156p25mhz_cmu1[i].mask);
|
||||
}
|
||||
}
|
||||
|
||||
/* lane is 0 based */
|
||||
static void netcp_xgbe_serdes_lane_config(
|
||||
void __iomem *serdes_regs, int lane)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* lane setup */
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_16bit_lane); i++) {
|
||||
reg_rmw(serdes_regs +
|
||||
cfg_phyb_10p3125g_16bit_lane[i].ofs +
|
||||
(0x200 * lane),
|
||||
cfg_phyb_10p3125g_16bit_lane[i].val,
|
||||
cfg_phyb_10p3125g_16bit_lane[i].mask);
|
||||
}
|
||||
|
||||
/* disable auto negotiation*/
|
||||
reg_rmw(serdes_regs + (0x200 * lane) + 0x0380,
|
||||
0x00000000, 0x00000010);
|
||||
|
||||
/* disable link training */
|
||||
reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0,
|
||||
0x00000000, 0x00000200);
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_com_enable(void __iomem *serdes_regs)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_comlane); i++) {
|
||||
reg_rmw(serdes_regs + cfg_phyb_10p3125g_comlane[i].ofs,
|
||||
cfg_phyb_10p3125g_comlane[i].val,
|
||||
cfg_phyb_10p3125g_comlane[i].mask);
|
||||
}
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_lane_enable(
|
||||
void __iomem *serdes_regs, int lane)
|
||||
{
|
||||
/* Set Lane Control Rate */
|
||||
writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane));
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_phyb_rst_clr(void __iomem *serdes_regs)
|
||||
{
|
||||
reg_rmw(serdes_regs + 0x0a00, 0x0000001f, 0x000000ff);
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_pll_disable(void __iomem *serdes_regs)
|
||||
{
|
||||
writel(0x88000000, serdes_regs + 0x1ff4);
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_pll_enable(void __iomem *serdes_regs)
|
||||
{
|
||||
netcp_xgbe_serdes_phyb_rst_clr(serdes_regs);
|
||||
writel(0xee000000, serdes_regs + 0x1ff4);
|
||||
}
|
||||
|
||||
static int netcp_xgbe_wait_pll_locked(void __iomem *sw_regs)
|
||||
{
|
||||
unsigned long timeout;
|
||||
int ret = 0;
|
||||
u32 val_1, val_0;
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(500);
|
||||
do {
|
||||
val_0 = (readl(sw_regs + XGBE_SGMII_1_OFFSET) & BIT(4));
|
||||
val_1 = (readl(sw_regs + XGBE_SGMII_2_OFFSET) & BIT(4));
|
||||
|
||||
if (val_1 && val_0)
|
||||
return 0;
|
||||
|
||||
if (time_after(jiffies, timeout)) {
|
||||
ret = -ETIMEDOUT;
|
||||
break;
|
||||
}
|
||||
|
||||
cpu_relax();
|
||||
} while (true);
|
||||
|
||||
pr_err("XGBE serdes not locked: time out.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_enable_xgmii_port(void __iomem *sw_regs)
|
||||
{
|
||||
writel(0x03, sw_regs + XGBE_CTRL_OFFSET);
|
||||
}
|
||||
|
||||
static u32 netcp_xgbe_serdes_read_tbus_val(void __iomem *serdes_regs)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
if (PHY_A(serdes_regs)) {
|
||||
tmp = (readl(serdes_regs + 0x0ec) >> 24) & 0x0ff;
|
||||
tmp |= ((readl(serdes_regs + 0x0fc) >> 16) & 0x00f00);
|
||||
} else {
|
||||
tmp = (readl(serdes_regs + 0x0f8) >> 16) & 0x0fff;
|
||||
}
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_write_tbus_addr(void __iomem *serdes_regs,
|
||||
int select, int ofs)
|
||||
{
|
||||
if (PHY_A(serdes_regs)) {
|
||||
reg_rmw(serdes_regs + 0x0008, ((select << 5) + ofs) << 24,
|
||||
~0x00ffffff);
|
||||
return;
|
||||
}
|
||||
|
||||
/* For 2 lane Phy-B, lane0 is actually lane1 */
|
||||
switch (select) {
|
||||
case 1:
|
||||
select = 2;
|
||||
break;
|
||||
case 2:
|
||||
select = 3;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
reg_rmw(serdes_regs + 0x00fc, ((select << 8) + ofs) << 16, ~0xf800ffff);
|
||||
}
|
||||
|
||||
static u32 netcp_xgbe_serdes_read_select_tbus(void __iomem *serdes_regs,
|
||||
int select, int ofs)
|
||||
{
|
||||
/* Set tbus address */
|
||||
netcp_xgbe_serdes_write_tbus_addr(serdes_regs, select, ofs);
|
||||
/* Get TBUS Value */
|
||||
return netcp_xgbe_serdes_read_tbus_val(serdes_regs);
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_reset_cdr(void __iomem *serdes_regs,
|
||||
void __iomem *sig_detect_reg, int lane)
|
||||
{
|
||||
u32 tmp, dlpf, tbus;
|
||||
|
||||
/*Get the DLPF values */
|
||||
tmp = netcp_xgbe_serdes_read_select_tbus(
|
||||
serdes_regs, lane + 1, 5);
|
||||
|
||||
dlpf = tmp >> 2;
|
||||
|
||||
if (dlpf < 400 || dlpf > 700) {
|
||||
reg_rmw(sig_detect_reg, VAL_SH(2, 1), MASK_WID_SH(2, 1));
|
||||
mdelay(1);
|
||||
reg_rmw(sig_detect_reg, VAL_SH(0, 1), MASK_WID_SH(2, 1));
|
||||
} else {
|
||||
tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane +
|
||||
1, 0xe);
|
||||
|
||||
pr_debug("XGBE: CDR centered, DLPF: %4d,%d,%d.\n",
|
||||
tmp >> 2, tmp & 3, (tbus >> 2) & 3);
|
||||
}
|
||||
}
|
||||
|
||||
/* Call every 100 ms */
|
||||
static int netcp_xgbe_check_link_status(void __iomem *serdes_regs,
|
||||
void __iomem *sw_regs, u32 lanes,
|
||||
u32 *current_state, u32 *lane_down)
|
||||
{
|
||||
void __iomem *pcsr_base = sw_regs + 0x0600;
|
||||
void __iomem *sig_detect_reg;
|
||||
u32 pcsr_rx_stat, blk_lock, blk_errs;
|
||||
int loss, i, status = 1;
|
||||
|
||||
for (i = 0; i < lanes; i++) {
|
||||
/* Get the Loss bit */
|
||||
loss = readl(serdes_regs + 0x1fc0 + 0x20 + (i * 0x04)) & 0x1;
|
||||
|
||||
/* Get Block Errors and Block Lock bits */
|
||||
pcsr_rx_stat = readl(pcsr_base + 0x0c + (i * 0x80));
|
||||
blk_lock = (pcsr_rx_stat >> 30) & 0x1;
|
||||
blk_errs = (pcsr_rx_stat >> 16) & 0x0ff;
|
||||
|
||||
/* Get Signal Detect Overlay Address */
|
||||
sig_detect_reg = serdes_regs + (i * 0x200) + 0x200 + 0x04;
|
||||
|
||||
/* If Block errors maxed out, attempt recovery! */
|
||||
if (blk_errs == 0x0ff)
|
||||
blk_lock = 0;
|
||||
|
||||
switch (current_state[i]) {
|
||||
case 0:
|
||||
/* if good link lock the signal detect ON! */
|
||||
if (!loss && blk_lock) {
|
||||
pr_debug("XGBE PCSR Linked Lane: %d\n", i);
|
||||
reg_rmw(sig_detect_reg, VAL_SH(3, 1),
|
||||
MASK_WID_SH(2, 1));
|
||||
current_state[i] = 1;
|
||||
} else if (!blk_lock) {
|
||||
/* if no lock, then reset CDR */
|
||||
pr_debug("XGBE PCSR Recover Lane: %d\n", i);
|
||||
netcp_xgbe_serdes_reset_cdr(serdes_regs,
|
||||
sig_detect_reg, i);
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
if (!blk_lock) {
|
||||
/* Link Lost? */
|
||||
lane_down[i] = 1;
|
||||
current_state[i] = 2;
|
||||
}
|
||||
break;
|
||||
|
||||
case 2:
|
||||
if (blk_lock)
|
||||
/* Nope just noise */
|
||||
current_state[i] = 1;
|
||||
else {
|
||||
/* Lost the block lock, reset CDR if it is
|
||||
* not centered and go back to sync state
|
||||
*/
|
||||
netcp_xgbe_serdes_reset_cdr(serdes_regs,
|
||||
sig_detect_reg, i);
|
||||
current_state[i] = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
pr_err("XGBE: unknown current_state[%d] %d\n",
|
||||
i, current_state[i]);
|
||||
break;
|
||||
}
|
||||
|
||||
if (blk_errs > 0) {
|
||||
/* Reset the Error counts! */
|
||||
reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x19, 0),
|
||||
MASK_WID_SH(8, 0));
|
||||
|
||||
reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x00, 0),
|
||||
MASK_WID_SH(8, 0));
|
||||
}
|
||||
|
||||
status &= (current_state[i] == 1);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int netcp_xgbe_serdes_check_lane(void __iomem *serdes_regs,
|
||||
void __iomem *sw_regs)
|
||||
{
|
||||
u32 current_state[2] = {0, 0};
|
||||
int retries = 0, link_up;
|
||||
u32 lane_down[2];
|
||||
|
||||
do {
|
||||
lane_down[0] = 0;
|
||||
lane_down[1] = 0;
|
||||
|
||||
link_up = netcp_xgbe_check_link_status(serdes_regs, sw_regs, 2,
|
||||
current_state,
|
||||
lane_down);
|
||||
|
||||
/* if we did not get link up then wait 100ms before calling
|
||||
* it again
|
||||
*/
|
||||
if (link_up)
|
||||
break;
|
||||
|
||||
if (lane_down[0])
|
||||
pr_debug("XGBE: detected link down on lane 0\n");
|
||||
|
||||
if (lane_down[1])
|
||||
pr_debug("XGBE: detected link down on lane 1\n");
|
||||
|
||||
if (++retries > 1) {
|
||||
pr_debug("XGBE: timeout waiting for serdes link up\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
mdelay(100);
|
||||
} while (!link_up);
|
||||
|
||||
pr_debug("XGBE: PCSR link is up\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void netcp_xgbe_serdes_setup_cm_c1_c2(void __iomem *serdes_regs,
|
||||
int lane, int cm, int c1, int c2)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_cm_c1_c2); i++) {
|
||||
reg_rmw(serdes_regs + cfg_cm_c1_c2[i].ofs + (0x200 * lane),
|
||||
cfg_cm_c1_c2[i].val,
|
||||
cfg_cm_c1_c2[i].mask);
|
||||
}
|
||||
}
|
||||
|
||||
static void netcp_xgbe_reset_serdes(void __iomem *serdes_regs)
|
||||
{
|
||||
/* Toggle the POR_EN bit in CONFIG.CPU_CTRL */
|
||||
/* enable POR_EN bit */
|
||||
reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, POR_EN, POR_EN);
|
||||
usleep_range(10, 100);
|
||||
|
||||
/* disable POR_EN bit */
|
||||
reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, 0, POR_EN);
|
||||
usleep_range(10, 100);
|
||||
}
|
||||
|
||||
static int netcp_xgbe_serdes_config(void __iomem *serdes_regs,
|
||||
void __iomem *sw_regs)
|
||||
{
|
||||
u32 ret, i;
|
||||
|
||||
netcp_xgbe_serdes_pll_disable(serdes_regs);
|
||||
netcp_xgbe_serdes_cmu_init(serdes_regs);
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
netcp_xgbe_serdes_lane_config(serdes_regs, i);
|
||||
|
||||
netcp_xgbe_serdes_com_enable(serdes_regs);
|
||||
/* This is EVM + RTM-BOC specific */
|
||||
for (i = 0; i < 2; i++)
|
||||
netcp_xgbe_serdes_setup_cm_c1_c2(serdes_regs, i, 0, 0, 5);
|
||||
|
||||
netcp_xgbe_serdes_pll_enable(serdes_regs);
|
||||
for (i = 0; i < 2; i++)
|
||||
netcp_xgbe_serdes_lane_enable(serdes_regs, i);
|
||||
|
||||
/* SB PLL Status Poll */
|
||||
ret = netcp_xgbe_wait_pll_locked(sw_regs);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
netcp_xgbe_serdes_enable_xgmii_port(sw_regs);
|
||||
netcp_xgbe_serdes_check_lane(serdes_regs, sw_regs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int netcp_xgbe_serdes_init(void __iomem *serdes_regs, void __iomem *xgbe_regs)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* read COMLANE bits 4:0 */
|
||||
val = readl(serdes_regs + 0xa00);
|
||||
if (val & 0x1f) {
|
||||
pr_debug("XGBE: serdes already in operation - reset\n");
|
||||
netcp_xgbe_reset_serdes(serdes_regs);
|
||||
}
|
||||
return netcp_xgbe_serdes_config(serdes_regs, xgbe_regs);
|
||||
}
|
||||
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