MTD: nand: make au1550nd.c a platform_driver
Transform the au1550nd.c driver into a platform_driver and hook it up in the PB1550 board (gen_nand works fine on the DB1550, but since I don't have a PB1550 to test this driver stays for now). Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-mtd@lists.infradead.org To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2875/ Patchwork: https://patchwork.linux-mips.org/patch/3160/ Acked-by: Artem Bityutskiy <dedekind1@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
Родитель
1c043f16a0
Коммит
b67a1a02d4
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@ -24,6 +24,7 @@
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#include <linux/platform_device.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1550nd.h>
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#include <asm/mach-au1x00/gpio.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include "platform.h"
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@ -131,6 +132,67 @@ static struct platform_device pb1550_i2c_dev = {
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.resource = au1550_psc2_res,
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};
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static struct mtd_partition pb1550_nand_parts[] = {
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[0] = {
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8 * 1024 * 1024,
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},
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[1] = {
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct au1550nd_platdata pb1550_nand_pd = {
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.parts = pb1550_nand_parts,
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.num_parts = ARRAY_SIZE(pb1550_nand_parts),
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.devwidth = 0, /* x8 NAND default, needs fixing up */
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};
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static struct resource pb1550_nand_res[] = {
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[0] = {
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.start = 0x20000000,
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.end = 0x20000fff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device pb1550_nand_dev = {
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.name = "au1550-nand",
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.id = -1,
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.resource = pb1550_nand_res,
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.num_resources = ARRAY_SIZE(pb1550_nand_res),
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.dev = {
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.platform_data = &pb1550_nand_pd,
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},
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};
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static void __init pb1550_nand_setup(void)
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{
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int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
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((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
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switch (boot_swapboot) {
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case 0:
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case 2:
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case 8:
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case 0xC:
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case 0xD:
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/* x16 NAND Flash */
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pb1550_nand_pd.devwidth = 1;
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/* fallthrough */
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case 1:
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case 9:
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case 3:
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case 0xE:
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case 0xF:
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/* x8 NAND, already set up */
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platform_device_register(&pb1550_nand_dev);
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}
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}
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static int __init pb1550_dev_init(void)
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{
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int swapped;
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@ -168,6 +230,10 @@ static int __init pb1550_dev_init(void)
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AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
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AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
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/* NAND setup */
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gpio_direction_input(206); /* GPIO206 high */
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pb1550_nand_setup();
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swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
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db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
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platform_device_register(&pb1550_pci_host);
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@ -0,0 +1,16 @@
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/*
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* platform data for the Au1550 NAND driver
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*/
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#ifndef _AU1550ND_H_
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#define _AU1550ND_H_
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#include <linux/mtd/partitions.h>
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struct au1550nd_platdata {
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struct mtd_partition *parts;
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int num_parts;
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int devwidth; /* 0 = 8bit device, 1 = 16bit device */
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};
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#endif
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@ -17,35 +17,19 @@
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1550nd.h>
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#ifdef CONFIG_MIPS_PB1550
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#include <asm/mach-pb1x00/pb1550.h>
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#elif defined(CONFIG_MIPS_DB1550)
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#include <asm/mach-db1x00/db1x00.h>
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#endif
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#include <asm/mach-db1x00/bcsr.h>
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/*
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* MTD structure for NAND controller
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*/
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static struct mtd_info *au1550_mtd = NULL;
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static void __iomem *p_nand;
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static int nand_width = 1; /* default x8 */
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static void (*au1550_write_byte)(struct mtd_info *, u_char);
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struct au1550nd_ctx {
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struct mtd_info info;
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struct nand_chip chip;
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/*
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* Define partitions for flash device
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*/
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static const struct mtd_partition partition_info[] = {
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{
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8 * 1024 * 1024},
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{
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL}
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int cs;
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void __iomem *base;
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void (*write_byte)(struct mtd_info *, u_char);
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};
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/**
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@ -259,24 +243,25 @@ static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
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static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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register struct nand_chip *this = mtd->priv;
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struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
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struct nand_chip *this = mtd->priv;
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switch (cmd) {
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case NAND_CTL_SETCLE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
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this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
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break;
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case NAND_CTL_CLRCLE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
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this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
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break;
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case NAND_CTL_SETALE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
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this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
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break;
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case NAND_CTL_CLRALE:
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this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
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this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
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/* FIXME: Nobody knows why this is necessary,
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* but it works only that way */
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udelay(1);
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@ -284,7 +269,7 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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case NAND_CTL_SETNCE:
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/* assert (force assert) chip enable */
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au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
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au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
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break;
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case NAND_CTL_CLRNCE:
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@ -331,9 +316,10 @@ static void au1550_select_chip(struct mtd_info *mtd, int chip)
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*/
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static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
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{
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register struct nand_chip *this = mtd->priv;
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struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
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struct nand_chip *this = mtd->priv;
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int ce_override = 0, i;
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ulong flags;
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unsigned long flags = 0;
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/* Begin command latch cycle */
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au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
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@ -354,9 +340,9 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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au1550_write_byte(mtd, readcmd);
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ctx->write_byte(mtd, readcmd);
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}
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au1550_write_byte(mtd, command);
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ctx->write_byte(mtd, command);
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/* Set ALE and clear CLE to start address cycle */
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au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
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@ -369,10 +355,10 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
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/* Adjust columns for 16 bit buswidth */
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if (this->options & NAND_BUSWIDTH_16)
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column >>= 1;
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au1550_write_byte(mtd, column);
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ctx->write_byte(mtd, column);
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}
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if (page_addr != -1) {
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au1550_write_byte(mtd, (u8)(page_addr & 0xff));
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ctx->write_byte(mtd, (u8)(page_addr & 0xff));
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if (command == NAND_CMD_READ0 ||
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command == NAND_CMD_READ1 ||
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@ -390,11 +376,12 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
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au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
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}
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au1550_write_byte(mtd, (u8)(page_addr >> 8));
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ctx->write_byte(mtd, (u8)(page_addr >> 8));
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/* One more address cycle for devices > 32MiB */
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if (this->chipsize > (32 << 20))
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au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
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ctx->write_byte(mtd,
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((page_addr >> 16) & 0x0f));
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}
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/* Latch in address */
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au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
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@ -440,121 +427,79 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
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while(!this->dev_ready(mtd));
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}
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/*
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* Main initialization routine
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*/
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static int __init au1xxx_nand_init(void)
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static int __devinit find_nand_cs(unsigned long nand_base)
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{
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struct nand_chip *this;
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u16 boot_swapboot = 0; /* default value */
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int retval;
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u32 mem_staddr;
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u32 nand_phys;
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void __iomem *base =
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(void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
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unsigned long addr, staddr, start, mask, end;
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int i;
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/* Allocate memory for MTD device structure and private data */
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au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
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if (!au1550_mtd) {
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printk("Unable to allocate NAND MTD dev structure.\n");
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for (i = 0; i < 4; i++) {
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addr = 0x1000 + (i * 0x10); /* CSx */
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staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
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/* figure out the decoded range of this CS */
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start = (staddr << 4) & 0xfffc0000;
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mask = (staddr << 18) & 0xfffc0000;
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end = (start | (start - 1)) & ~(start ^ mask);
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if ((nand_base >= start) && (nand_base < end))
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return i;
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}
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return -ENODEV;
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}
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static int __devinit au1550nd_probe(struct platform_device *pdev)
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{
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struct au1550nd_platdata *pd;
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struct au1550nd_ctx *ctx;
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struct nand_chip *this;
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struct resource *r;
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int ret, cs;
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pd = pdev->dev.platform_data;
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if (!pd) {
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dev_err(&pdev->dev, "missing platform data\n");
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return -ENODEV;
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}
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx) {
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dev_err(&pdev->dev, "no memory for NAND context\n");
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return -ENOMEM;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *)(&au1550_mtd[1]);
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/* Link the private data with the MTD structure */
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au1550_mtd->priv = this;
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au1550_mtd->owner = THIS_MODULE;
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/* MEM_STNDCTL: disable ints, disable nand boot */
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au_writel(0, MEM_STNDCTL);
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#ifdef CONFIG_MIPS_PB1550
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/* set gpio206 high */
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gpio_direction_input(206);
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boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
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switch (boot_swapboot) {
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case 0:
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case 2:
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case 8:
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case 0xC:
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case 0xD:
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/* x16 NAND Flash */
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nand_width = 0;
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break;
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case 1:
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case 9:
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case 3:
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case 0xE:
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case 0xF:
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/* x8 NAND Flash */
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nand_width = 1;
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break;
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default:
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printk("Pb1550 NAND: bad boot:swap\n");
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retval = -EINVAL;
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goto outmem;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "no NAND memory resource\n");
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ret = -ENODEV;
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goto out1;
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}
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#endif
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/* Configure chip-select; normally done by boot code, e.g. YAMON */
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#ifdef NAND_STCFG
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if (NAND_CS == 0) {
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au_writel(NAND_STCFG, MEM_STCFG0);
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au_writel(NAND_STTIME, MEM_STTIME0);
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au_writel(NAND_STADDR, MEM_STADDR0);
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if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
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dev_err(&pdev->dev, "cannot claim NAND memory area\n");
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ret = -ENOMEM;
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goto out1;
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}
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if (NAND_CS == 1) {
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au_writel(NAND_STCFG, MEM_STCFG1);
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au_writel(NAND_STTIME, MEM_STTIME1);
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au_writel(NAND_STADDR, MEM_STADDR1);
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ctx->base = ioremap_nocache(r->start, 0x1000);
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if (!ctx->base) {
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dev_err(&pdev->dev, "cannot remap NAND memory area\n");
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ret = -ENODEV;
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goto out2;
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}
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if (NAND_CS == 2) {
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au_writel(NAND_STCFG, MEM_STCFG2);
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au_writel(NAND_STTIME, MEM_STTIME2);
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au_writel(NAND_STADDR, MEM_STADDR2);
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this = &ctx->chip;
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ctx->info.priv = this;
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ctx->info.owner = THIS_MODULE;
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/* figure out which CS# r->start belongs to */
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cs = find_nand_cs(r->start);
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if (cs < 0) {
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dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
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ret = -ENODEV;
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goto out3;
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}
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if (NAND_CS == 3) {
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au_writel(NAND_STCFG, MEM_STCFG3);
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au_writel(NAND_STTIME, MEM_STTIME3);
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au_writel(NAND_STADDR, MEM_STADDR3);
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}
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#endif
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ctx->cs = cs;
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/* Locate NAND chip-select in order to determine NAND phys address */
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mem_staddr = 0x00000000;
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if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
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mem_staddr = au_readl(MEM_STADDR0);
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else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
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mem_staddr = au_readl(MEM_STADDR1);
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else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
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mem_staddr = au_readl(MEM_STADDR2);
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else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
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mem_staddr = au_readl(MEM_STADDR3);
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if (mem_staddr == 0x00000000) {
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printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
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kfree(au1550_mtd);
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return 1;
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}
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nand_phys = (mem_staddr << 4) & 0xFFFC0000;
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p_nand = ioremap(nand_phys, 0x1000);
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/* make controller and MTD agree */
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if (NAND_CS == 0)
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nand_width = au_readl(MEM_STCFG0) & (1 << 22);
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if (NAND_CS == 1)
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nand_width = au_readl(MEM_STCFG1) & (1 << 22);
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if (NAND_CS == 2)
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nand_width = au_readl(MEM_STCFG2) & (1 << 22);
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if (NAND_CS == 3)
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nand_width = au_readl(MEM_STCFG3) & (1 << 22);
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|
||||
/* Set address of hardware control function */
|
||||
this->dev_ready = au1550_device_ready;
|
||||
this->select_chip = au1550_select_chip;
|
||||
this->cmdfunc = au1550_command;
|
||||
|
|
@ -565,54 +510,57 @@ static int __init au1xxx_nand_init(void)
|
|||
|
||||
this->options = NAND_NO_AUTOINCR;
|
||||
|
||||
if (!nand_width)
|
||||
if (pd->devwidth)
|
||||
this->options |= NAND_BUSWIDTH_16;
|
||||
|
||||
this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
|
||||
au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
|
||||
this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
|
||||
ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
|
||||
this->read_word = au_read_word;
|
||||
this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
|
||||
this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
|
||||
this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
|
||||
this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
|
||||
this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
|
||||
this->verify_buf = (pd->devwidth) ? au_verify_buf16 : au_verify_buf;
|
||||
|
||||
/* Scan to find existence of the device */
|
||||
if (nand_scan(au1550_mtd, 1)) {
|
||||
retval = -ENXIO;
|
||||
goto outio;
|
||||
ret = nand_scan(&ctx->info, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
|
||||
goto out3;
|
||||
}
|
||||
|
||||
/* Register the partitions */
|
||||
mtd_device_register(au1550_mtd, partition_info,
|
||||
ARRAY_SIZE(partition_info));
|
||||
mtd_device_register(&ctx->info, pd->parts, pd->num_parts);
|
||||
|
||||
return 0;
|
||||
|
||||
outio:
|
||||
iounmap(p_nand);
|
||||
|
||||
outmem:
|
||||
kfree(au1550_mtd);
|
||||
return retval;
|
||||
out3:
|
||||
iounmap(ctx->base);
|
||||
out2:
|
||||
release_mem_region(r->start, resource_size(r));
|
||||
out1:
|
||||
kfree(ctx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
module_init(au1xxx_nand_init);
|
||||
|
||||
/*
|
||||
* Clean up routine
|
||||
*/
|
||||
static void __exit au1550_cleanup(void)
|
||||
static int __devexit au1550nd_remove(struct platform_device *pdev)
|
||||
{
|
||||
/* Release resources, unregister device */
|
||||
nand_release(au1550_mtd);
|
||||
struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
|
||||
struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
/* Free the MTD device structure */
|
||||
kfree(au1550_mtd);
|
||||
|
||||
/* Unmap */
|
||||
iounmap(p_nand);
|
||||
nand_release(&ctx->info);
|
||||
iounmap(ctx->base);
|
||||
release_mem_region(r->start, 0x1000);
|
||||
kfree(ctx);
|
||||
return 0;
|
||||
}
|
||||
|
||||
module_exit(au1550_cleanup);
|
||||
static struct platform_driver au1550nd_driver = {
|
||||
.driver = {
|
||||
.name = "au1550-nand",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = au1550nd_probe,
|
||||
.remove = __devexit_p(au1550nd_remove),
|
||||
};
|
||||
|
||||
module_platform_driver(au1550nd_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Embedded Edge, LLC");
|
||||
|
|
|
|||
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