ARM: S3C64XX: Migrate clock handling to Common Clock Framework
This patch migrates the s3c64xx platform to use the new clock driver using Common Clock Framework. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tomasz Figa
Kukjin Kim
Родитель
d0127f6fc1
Коммит
b69f460dc1
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@ -727,6 +727,7 @@ config ARCH_S3C64XX
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select ARM_VIC
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select CLKDEV_LOOKUP
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select CLKSRC_SAMSUNG_PWM
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select COMMON_CLK
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select CPU_V6
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select GENERIC_CLOCKEVENTS
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select GPIO_SAMSUNG
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@ -740,7 +741,6 @@ config ARCH_S3C64XX
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select S3C_DEV_NAND
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select S3C_GPIO_TRACK
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select SAMSUNG_ATAGS
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select SAMSUNG_CLKSRC
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select SAMSUNG_GPIOLIB_4BIT
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select SAMSUNG_WDT_RESET
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select USB_ARCH_HAS_OHCI
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@ -12,7 +12,7 @@ obj- :=
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# Core
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obj-y += common.o clock.o
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obj-y += common.o
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# Core support
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@ -17,6 +17,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/serial_core.h>
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@ -38,7 +39,6 @@
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/pm.h>
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#include <plat/gpio-cfg.h>
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@ -50,6 +50,19 @@
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#include "common.h"
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/* External clock frequency */
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static unsigned long xtal_f = 12000000, xusbxti_f = 48000000;
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void __init s3c64xx_set_xtal_freq(unsigned long freq)
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{
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xtal_f = freq;
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}
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void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
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{
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xusbxti_f = freq;
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}
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/* uart registration process */
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static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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@ -67,7 +80,6 @@ static struct cpu_table cpu_ids[] __initdata = {
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.idcode = S3C6400_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6400_map_io,
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.init_clocks = s3c6400_init_clocks,
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.init_uarts = s3c64xx_init_uarts,
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.init = s3c6400_init,
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.name = name_s3c6400,
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@ -75,7 +87,6 @@ static struct cpu_table cpu_ids[] __initdata = {
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.idcode = S3C6410_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6410_map_io,
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.init_clocks = s3c6410_init_clocks,
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.init_uarts = s3c64xx_init_uarts,
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.init = s3c6410_init,
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.name = name_s3c6410,
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@ -213,8 +224,10 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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{
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/*
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* FIXME: there is no better place to put this at the moment
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* (samsung_wdt_reset_init needs clocks)
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* (s3c64xx_clk_init needs ioremap and must happen before init_time
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* samsung_wdt_reset_init needs clocks)
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*/
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s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
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samsung_wdt_reset_init(S3C_VA_WATCHDOG);
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printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
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@ -22,18 +22,19 @@
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void s3c64xx_init_irq(u32 vic0, u32 vic1);
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void s3c64xx_init_io(struct map_desc *mach_desc, int size);
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void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
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void s3c64xx_setup_clocks(void);
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void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
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void s3c64xx_init_late(void);
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void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
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unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
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void s3c64xx_set_xtal_freq(unsigned long freq);
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void s3c64xx_set_xusbxti_freq(unsigned long freq);
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#ifdef CONFIG_CPU_S3C6400
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extern int s3c6400_init(void);
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extern void s3c6400_init_irq(void);
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extern void s3c6400_map_io(void);
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extern void s3c6400_init_clocks(int xtal);
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#else
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#define s3c6400_init_clocks NULL
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@ -46,7 +47,6 @@ extern void s3c6400_init_clocks(int xtal);
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extern int s3c6410_init(void);
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extern void s3c6410_init_irq(void);
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extern void s3c6410_map_io(void);
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extern void s3c6410_init_clocks(int xtal);
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#else
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#define s3c6410_init_clocks NULL
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@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = {
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static void __init anw6410_map_io(void)
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{
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s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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@ -743,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = {
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static void __init crag6410_map_io(void)
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{
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s3c64xx_init_io(NULL, 0);
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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@ -247,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = {
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static void __init hmt_map_io(void)
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{
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s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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}
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@ -231,7 +231,7 @@ static void __init mini6410_map_io(void)
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u32 tmp;
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s3c64xx_init_io(NULL, 0);
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {};
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static void __init ncp_map_io(void)
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{
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s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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}
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@ -337,13 +337,6 @@ err:
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return ret;
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}
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static int __init smartq_usb_otg_init(void)
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{
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clk_xusbxti.rate = 12000000;
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return 0;
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}
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static int __init smartq_wifi_init(void)
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{
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int ret;
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@ -377,7 +370,8 @@ static struct map_desc smartq_iodesc[] __initdata = {};
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void __init smartq_map_io(void)
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{
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s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c64xx_set_xusbxti_freq(12000000);
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s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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@ -399,7 +393,6 @@ void __init smartq_machine_init(void)
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WARN_ON(smartq_lcd_setup_gpio());
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WARN_ON(smartq_power_off_init());
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WARN_ON(smartq_usb_host_init());
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WARN_ON(smartq_usb_otg_init());
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WARN_ON(smartq_wifi_init());
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platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
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@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {};
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static void __init smdk6400_map_io(void)
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{
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s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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}
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@ -634,7 +634,7 @@ static void __init smdk6410_map_io(void)
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u32 tmp;
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s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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@ -58,12 +58,6 @@ void __init s3c6400_map_io(void)
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s3c64xx_onenand1_setname("s3c6400-onenand");
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}
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void __init s3c6400_init_clocks(int xtal)
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{
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s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
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s3c64xx_setup_clocks();
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}
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void __init s3c6400_init_irq(void)
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{
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/* VIC0 does not have IRQS 5..7,
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@ -62,13 +62,6 @@ void __init s3c6410_map_io(void)
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s3c_cfcon_setname("s3c64xx-pata");
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}
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void __init s3c6410_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
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s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
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s3c64xx_setup_clocks();
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}
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void __init s3c6410_init_irq(void)
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{
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/* VIC0 is missing IRQ7, VIC1 is fully populated. */
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@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
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obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
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obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
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obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
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ifdef CONFIG_COMMON_CLK
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obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
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endif
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