drm/amdgpu: add AMDGPU_VM_NOALLOC v2
Add the AMDGPU_VM_NOALLOC flag to let userspace control MALL allocation. v2: also add the flag to the allowed flags. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -645,6 +645,8 @@ uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
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pte_flag |= AMDGPU_PTE_WRITEABLE;
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pte_flag |= AMDGPU_PTE_WRITEABLE;
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if (flags & AMDGPU_VM_PAGE_PRT)
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if (flags & AMDGPU_VM_PAGE_PRT)
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pte_flag |= AMDGPU_PTE_PRT;
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pte_flag |= AMDGPU_PTE_PRT;
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if (flags & AMDGPU_VM_PAGE_NOALLOC)
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pte_flag |= AMDGPU_PTE_NOALLOC;
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if (adev->gmc.gmc_funcs->map_mtype)
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if (adev->gmc.gmc_funcs->map_mtype)
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pte_flag |= amdgpu_gmc_map_mtype(adev,
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pte_flag |= amdgpu_gmc_map_mtype(adev,
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@ -658,7 +660,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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{
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{
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const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
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const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
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AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
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AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
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AMDGPU_VM_PAGE_NOALLOC;
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const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
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const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
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AMDGPU_VM_PAGE_PRT;
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AMDGPU_VM_PAGE_PRT;
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@ -613,6 +613,9 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
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*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
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*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
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*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
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*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
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*flags &= ~AMDGPU_PTE_NOALLOC;
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*flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
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if (mapping->flags & AMDGPU_PTE_PRT) {
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if (mapping->flags & AMDGPU_PTE_PRT) {
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*flags |= AMDGPU_PTE_PRT;
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*flags |= AMDGPU_PTE_PRT;
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*flags |= AMDGPU_PTE_SNOOPED;
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*flags |= AMDGPU_PTE_SNOOPED;
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@ -500,6 +500,9 @@ static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
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*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
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*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
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*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
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*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
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*flags &= ~AMDGPU_PTE_NOALLOC;
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*flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
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if (mapping->flags & AMDGPU_PTE_PRT) {
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if (mapping->flags & AMDGPU_PTE_PRT) {
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*flags |= AMDGPU_PTE_PRT;
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*flags |= AMDGPU_PTE_PRT;
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*flags |= AMDGPU_PTE_SNOOPED;
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*flags |= AMDGPU_PTE_SNOOPED;
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@ -533,6 +533,8 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VM_MTYPE_UC (4 << 5)
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#define AMDGPU_VM_MTYPE_UC (4 << 5)
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/* Use Read Write MTYPE instead of default MTYPE */
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/* Use Read Write MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_RW (5 << 5)
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#define AMDGPU_VM_MTYPE_RW (5 << 5)
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/* don't allocate MALL */
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#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)
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struct drm_amdgpu_gem_va {
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struct drm_amdgpu_gem_va {
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/** GEM object handle */
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/** GEM object handle */
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