[PATCH] S2io: Support for bimodal interrupts
Hi, This is a patch to provide bimodal interrupt moderation support for Xframe II adapter. Basically, in this moderation scheme, the adapter raises a traffic interrupt if the no. of packets transmitted and/or received reaches a programmable threshold. Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com> Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
raghavendra.koushik@neterion.com
Jeff Garzik
Родитель
541ae68f6d
Коммит
b6e3f9828b
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@ -297,6 +297,7 @@ static unsigned int mc_pause_threshold_q4q7 = 187;
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static unsigned int shared_splits;
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static unsigned int tmac_util_period = 5;
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static unsigned int rmac_util_period = 5;
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static unsigned int bimodal = 0;
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#ifndef CONFIG_S2IO_NAPI
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static unsigned int indicate_max_pkts;
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#endif
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@ -1306,52 +1307,86 @@ static int init_nic(struct s2io_nic *nic)
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time++;
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}
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if (nic->config.bimodal) {
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int k = 0;
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for (k = 0; k < config->rx_ring_num; k++) {
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val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
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val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
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writeq(val64, &bar0->tti_command_mem);
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/* RTI Initialization */
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if (nic->device_type == XFRAME_II_DEVICE) {
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/*
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* Programmed to generate Apprx 500 Intrs per
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* second
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*/
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int count = (nic->config.bus_speed * 125)/4;
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val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
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* Once the operation completes, the Strobe bit of the command
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* register will be reset. We poll for this particular condition
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* We wait for a maximum of 500ms for the operation to complete,
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* if it's not complete by then we return error.
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*/
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time = 0;
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while (TRUE) {
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val64 = readq(&bar0->tti_command_mem);
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if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
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break;
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}
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if (time > 10) {
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DBG_PRINT(ERR_DBG,
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"%s: TTI init Failed\n",
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dev->name);
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return -1;
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}
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time++;
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msleep(50);
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}
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}
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} else {
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val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
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}
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val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
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RTI_DATA1_MEM_RX_URNG_B(0x10) |
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RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
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writeq(val64, &bar0->rti_data1_mem);
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val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
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RTI_DATA2_MEM_RX_UFC_B(0x2) |
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RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
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writeq(val64, &bar0->rti_data2_mem);
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val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD;
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writeq(val64, &bar0->rti_command_mem);
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/*
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* Once the operation completes, the Strobe bit of the
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* command register will be reset. We poll for this
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* particular condition. We wait for a maximum of 500ms
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* for the operation to complete, if it's not complete
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* by then we return error.
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*/
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time = 0;
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while (TRUE) {
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val64 = readq(&bar0->rti_command_mem);
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if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
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break;
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/* RTI Initialization */
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if (nic->device_type == XFRAME_II_DEVICE) {
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/*
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* Programmed to generate Apprx 500 Intrs per
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* second
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*/
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int count = (nic->config.bus_speed * 125)/4;
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val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
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} else {
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val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
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}
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if (time > 10) {
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DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
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dev->name);
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return -1;
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val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
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RTI_DATA1_MEM_RX_URNG_B(0x10) |
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RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
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writeq(val64, &bar0->rti_data1_mem);
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val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
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RTI_DATA2_MEM_RX_UFC_B(0x2) |
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RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
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writeq(val64, &bar0->rti_data2_mem);
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for (i = 0; i < config->rx_ring_num; i++) {
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val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
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| RTI_CMD_MEM_OFFSET(i);
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writeq(val64, &bar0->rti_command_mem);
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/*
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* Once the operation completes, the Strobe bit of the
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* command register will be reset. We poll for this
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* particular condition. We wait for a maximum of 500ms
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* for the operation to complete, if it's not complete
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* by then we return error.
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*/
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time = 0;
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while (TRUE) {
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val64 = readq(&bar0->rti_command_mem);
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if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
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break;
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}
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if (time > 10) {
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DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
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dev->name);
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return -1;
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}
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time++;
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msleep(50);
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}
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}
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time++;
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msleep(50);
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}
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/*
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@ -1789,6 +1824,8 @@ static int start_nic(struct s2io_nic *nic)
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&bar0->prc_rxd0_n[i]);
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val64 = readq(&bar0->prc_ctrl_n[i]);
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if (nic->config.bimodal)
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val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
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#ifndef CONFIG_2BUFF_MODE
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val64 |= PRC_CTRL_RC_ENABLED;
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#else
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@ -5030,6 +5067,7 @@ module_param(mc_pause_threshold_q4q7, int, 0);
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module_param(shared_splits, int, 0);
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module_param(tmac_util_period, int, 0);
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module_param(rmac_util_period, int, 0);
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module_param(bimodal, bool, 0);
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#ifndef CONFIG_S2IO_NAPI
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module_param(indicate_max_pkts, int, 0);
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#endif
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@ -5397,6 +5435,14 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
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else
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strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
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/* Initialize bimodal Interrupts */
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sp->config.bimodal = bimodal;
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if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
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sp->config.bimodal = 0;
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DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
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dev->name);
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}
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/*
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* Make Link state as off at this point, when the Link change
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* interrupt comes the state will be automatically changed to
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@ -261,8 +261,6 @@ typedef struct stat_block {
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u32 rmac_accepted_ip_oflow;
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u32 reserved_14;
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u32 link_fault_cnt;
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/* Software statistics maintained by driver */
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swStat_t sw_stat;
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} StatInfo_t;
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@ -349,6 +347,7 @@ struct config_param {
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#define MAX_RX_BLOCKS_PER_RING 150
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rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
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u8 bimodal; /*Flag for setting bimodal interrupts*/
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#define HEADER_ETHERNET_II_802_3_SIZE 14
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#define HEADER_802_2_SIZE 3
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