counter: 104-quad-8: Utilize iomap interface
This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Link: https://lore.kernel.org/r/861c003318dce3d2bef4061711643bb04f5ec14f.1652201921.git.william.gray@linaro.org Cc: Syed Nayyar Waris <syednwaris@gmail.com> Suggested-by: David Laight <David.Laight@ACULAB.COM> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Link: https://lore.kernel.org/r/e971b897cacfac4cb2eca478f5533d2875f5cadd.1657813472.git.william.gray@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
William Breathitt Gray
Greg Kroah-Hartman
Родитель
dd4a6bf374
Коммит
b6e9cded90
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@ -63,7 +63,7 @@ struct quad8 {
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unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
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unsigned int index_polarity[QUAD8_NUM_COUNTERS];
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unsigned int cable_fault_enable;
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unsigned int base;
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void __iomem *base;
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};
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#define QUAD8_REG_INTERRUPT_STATUS 0x10
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@ -118,8 +118,8 @@ static int quad8_signal_read(struct counter_device *counter,
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if (signal->id < 16)
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return -EINVAL;
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state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
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& BIT(signal->id - 16);
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state = ioread8(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) &
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BIT(signal->id - 16);
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*level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
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@ -130,14 +130,14 @@ static int quad8_count_read(struct counter_device *counter,
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struct counter_count *count, u64 *val)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int base_offset = priv->base + 2 * count->id;
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void __iomem *const base_offset = priv->base + 2 * count->id;
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unsigned int flags;
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unsigned int borrow;
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unsigned int carry;
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unsigned long irqflags;
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int i;
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flags = inb(base_offset + 1);
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flags = ioread8(base_offset + 1);
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borrow = flags & QUAD8_FLAG_BT;
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carry = !!(flags & QUAD8_FLAG_CT);
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@ -147,11 +147,11 @@ static int quad8_count_read(struct counter_device *counter,
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Reset Byte Pointer; transfer Counter to Output Latch */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
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base_offset + 1);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
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base_offset + 1);
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for (i = 0; i < 3; i++)
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*val |= (unsigned long)inb(base_offset) << (8 * i);
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*val |= (unsigned long)ioread8(base_offset) << (8 * i);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -162,7 +162,7 @@ static int quad8_count_write(struct counter_device *counter,
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struct counter_count *count, u64 val)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int base_offset = priv->base + 2 * count->id;
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void __iomem *const base_offset = priv->base + 2 * count->id;
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unsigned long irqflags;
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int i;
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@ -173,27 +173,27 @@ static int quad8_count_write(struct counter_device *counter,
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Counter can only be set via Preset Register */
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for (i = 0; i < 3; i++)
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outb(val >> (8 * i), base_offset);
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iowrite8(val >> (8 * i), base_offset);
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/* Transfer Preset Register to Counter */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Set Preset Register back to original value */
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val = priv->preset[count->id];
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for (i = 0; i < 3; i++)
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outb(val >> (8 * i), base_offset);
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iowrite8(val >> (8 * i), base_offset);
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/* Reset Borrow, Carry, Compare, and Sign flags */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
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/* Reset Error flag */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -246,7 +246,7 @@ static int quad8_function_write(struct counter_device *counter,
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unsigned int *const quadrature_mode = priv->quadrature_mode + id;
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unsigned int *const scale = priv->quadrature_scale + id;
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unsigned int *const synchronous_mode = priv->synchronous_mode + id;
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const int base_offset = priv->base + 2 * id + 1;
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void __iomem *const base_offset = priv->base + 2 * id + 1;
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unsigned long irqflags;
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unsigned int mode_cfg;
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unsigned int idr_cfg;
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@ -266,7 +266,7 @@ static int quad8_function_write(struct counter_device *counter,
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if (*synchronous_mode) {
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*synchronous_mode = 0;
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/* Disable synchronous function mode */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
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}
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} else {
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*quadrature_mode = 1;
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@ -292,7 +292,7 @@ static int quad8_function_write(struct counter_device *counter,
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}
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -305,10 +305,10 @@ static int quad8_direction_read(struct counter_device *counter,
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{
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const struct quad8 *const priv = counter_priv(counter);
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unsigned int ud_flag;
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const unsigned int flag_addr = priv->base + 2 * count->id + 1;
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void __iomem *const flag_addr = priv->base + 2 * count->id + 1;
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/* U/D flag: nonzero = up, zero = down */
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ud_flag = inb(flag_addr) & QUAD8_FLAG_UD;
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ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD;
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*direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
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COUNTER_COUNT_DIRECTION_BACKWARD;
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@ -402,7 +402,7 @@ static int quad8_events_configure(struct counter_device *counter)
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struct counter_event_node *event_node;
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unsigned int next_irq_trigger;
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unsigned long ior_cfg;
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unsigned long base_offset;
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void __iomem *base_offset;
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spin_lock_irqsave(&priv->lock, irqflags);
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@ -438,13 +438,13 @@ static int quad8_events_configure(struct counter_device *counter)
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priv->preset_enable[event_node->channel] << 1 |
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priv->irq_trigger[event_node->channel] << 3;
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base_offset = priv->base + 2 * event_node->channel + 1;
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
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iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset);
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/* Enable IRQ line */
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irq_enabled |= BIT(event_node->channel);
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}
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outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT);
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iowrite8(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -508,7 +508,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
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{
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struct quad8 *const priv = counter_priv(counter);
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const size_t channel_id = signal->id - 16;
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const int base_offset = priv->base + 2 * channel_id + 1;
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void __iomem *const base_offset = priv->base + 2 * channel_id + 1;
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unsigned long irqflags;
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unsigned int idr_cfg = index_polarity << 1;
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@ -519,7 +519,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
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priv->index_polarity[channel_id] = index_polarity;
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/* Load Index Control configuration to Index Control Register */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -549,7 +549,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
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{
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struct quad8 *const priv = counter_priv(counter);
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const size_t channel_id = signal->id - 16;
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const int base_offset = priv->base + 2 * channel_id + 1;
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void __iomem *const base_offset = priv->base + 2 * channel_id + 1;
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unsigned long irqflags;
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unsigned int idr_cfg = synchronous_mode;
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@ -566,7 +566,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
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priv->synchronous_mode[channel_id] = synchronous_mode;
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/* Load Index Control configuration to Index Control Register */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -614,7 +614,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
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struct quad8 *const priv = counter_priv(counter);
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unsigned int count_mode;
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unsigned int mode_cfg;
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const int base_offset = priv->base + 2 * count->id + 1;
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void __iomem *const base_offset = priv->base + 2 * count->id + 1;
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unsigned long irqflags;
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/* Map Generic Counter count mode to 104-QUAD-8 count mode */
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@ -648,7 +648,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
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mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -669,7 +669,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
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struct counter_count *count, u8 enable)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int base_offset = priv->base + 2 * count->id;
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void __iomem *const base_offset = priv->base + 2 * count->id;
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unsigned long irqflags;
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unsigned int ior_cfg;
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@ -681,7 +681,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
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priv->irq_trigger[count->id] << 3;
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/* Load I/O control configuration */
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
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iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -697,9 +697,9 @@ static int quad8_error_noise_get(struct counter_device *counter,
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struct counter_count *count, u32 *noise_error)
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{
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const struct quad8 *const priv = counter_priv(counter);
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const int base_offset = priv->base + 2 * count->id + 1;
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void __iomem *const base_offset = priv->base + 2 * count->id + 1;
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*noise_error = !!(inb(base_offset) & QUAD8_FLAG_E);
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*noise_error = !!(ioread8(base_offset) & QUAD8_FLAG_E);
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return 0;
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}
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@ -717,17 +717,17 @@ static int quad8_count_preset_read(struct counter_device *counter,
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static void quad8_preset_register_set(struct quad8 *const priv, const int id,
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const unsigned int preset)
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{
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const unsigned int base_offset = priv->base + 2 * id;
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void __iomem *const base_offset = priv->base + 2 * id;
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int i;
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priv->preset[id] = preset;
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Set Preset Register */
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for (i = 0; i < 3; i++)
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outb(preset >> (8 * i), base_offset);
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iowrite8(preset >> (8 * i), base_offset);
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}
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static int quad8_count_preset_write(struct counter_device *counter,
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@ -816,7 +816,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
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u8 preset_enable)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int base_offset = priv->base + 2 * count->id + 1;
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void __iomem *const base_offset = priv->base + 2 * count->id + 1;
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unsigned long irqflags;
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unsigned int ior_cfg;
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@ -831,7 +831,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
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priv->irq_trigger[count->id] << 3;
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/* Load I/O control configuration to Input / Output Control Register */
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
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iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -858,7 +858,7 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter,
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}
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/* Logic 0 = cable fault */
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status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
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status = ioread8(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -899,7 +899,8 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
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/* Enable is active low in Differential Encoder Cable Status register */
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cable_fault_enable = ~priv->cable_fault_enable;
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outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
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iowrite8(cable_fault_enable,
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priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -923,7 +924,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
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{
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struct quad8 *const priv = counter_priv(counter);
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const size_t channel_id = signal->id / 2;
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const int base_offset = priv->base + 2 * channel_id;
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void __iomem *const base_offset = priv->base + 2 * channel_id;
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unsigned long irqflags;
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spin_lock_irqsave(&priv->lock, irqflags);
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@ -931,12 +932,12 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
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priv->fck_prescaler[channel_id] = prescaler;
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Set filter clock factor */
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outb(prescaler, base_offset);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
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base_offset + 1);
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iowrite8(prescaler, base_offset);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
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base_offset + 1);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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@ -1084,12 +1085,12 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
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{
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struct counter_device *counter = private;
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struct quad8 *const priv = counter_priv(counter);
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const unsigned long base = priv->base;
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void __iomem *const base = priv->base;
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unsigned long irq_status;
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unsigned long channel;
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u8 event;
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irq_status = inb(base + QUAD8_REG_INTERRUPT_STATUS);
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irq_status = ioread8(base + QUAD8_REG_INTERRUPT_STATUS);
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if (!irq_status)
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return IRQ_NONE;
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@ -1118,17 +1119,43 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
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}
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/* Clear pending interrupts on device */
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outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP);
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iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP);
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return IRQ_HANDLED;
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}
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static void quad8_init_counter(void __iomem *const base_offset)
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{
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unsigned long i;
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/* Reset Byte Pointer */
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Reset filter clock factor */
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iowrite8(0, base_offset);
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iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
|
||||
base_offset + 1);
|
||||
/* Reset Byte Pointer */
|
||||
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
|
||||
/* Reset Preset Register */
|
||||
for (i = 0; i < 3; i++)
|
||||
iowrite8(0x00, base_offset);
|
||||
/* Reset Borrow, Carry, Compare, and Sign flags */
|
||||
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
|
||||
/* Reset Error flag */
|
||||
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
|
||||
/* Binary encoding; Normal count; non-quadrature mode */
|
||||
iowrite8(QUAD8_CTR_CMR, base_offset + 1);
|
||||
/* Disable A and B inputs; preset on index; FLG1 as Carry */
|
||||
iowrite8(QUAD8_CTR_IOR, base_offset + 1);
|
||||
/* Disable index function; negative index polarity */
|
||||
iowrite8(QUAD8_CTR_IDR, base_offset + 1);
|
||||
}
|
||||
|
||||
static int quad8_probe(struct device *dev, unsigned int id)
|
||||
{
|
||||
struct counter_device *counter;
|
||||
struct quad8 *priv;
|
||||
int i, j;
|
||||
unsigned int base_offset;
|
||||
unsigned long i;
|
||||
int err;
|
||||
|
||||
if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
|
||||
|
|
@ -1142,6 +1169,10 @@ static int quad8_probe(struct device *dev, unsigned int id)
|
|||
return -ENOMEM;
|
||||
priv = counter_priv(counter);
|
||||
|
||||
priv->base = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
|
||||
if (!priv->base)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Initialize Counter device and driver data */
|
||||
counter->name = dev_name(dev);
|
||||
counter->parent = dev;
|
||||
|
|
@ -1150,43 +1181,21 @@ static int quad8_probe(struct device *dev, unsigned int id)
|
|||
counter->num_counts = ARRAY_SIZE(quad8_counts);
|
||||
counter->signals = quad8_signals;
|
||||
counter->num_signals = ARRAY_SIZE(quad8_signals);
|
||||
priv->base = base[id];
|
||||
|
||||
spin_lock_init(&priv->lock);
|
||||
|
||||
/* Reset Index/Interrupt Register */
|
||||
outb(0x00, base[id] + QUAD8_REG_INDEX_INTERRUPT);
|
||||
iowrite8(0x00, priv->base + QUAD8_REG_INDEX_INTERRUPT);
|
||||
/* Reset all counters and disable interrupt function */
|
||||
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
|
||||
iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, priv->base + QUAD8_REG_CHAN_OP);
|
||||
/* Set initial configuration for all counters */
|
||||
for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
|
||||
base_offset = base[id] + 2 * i;
|
||||
/* Reset Byte Pointer */
|
||||
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
|
||||
/* Reset filter clock factor */
|
||||
outb(0, base_offset);
|
||||
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
|
||||
base_offset + 1);
|
||||
/* Reset Byte Pointer */
|
||||
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
|
||||
/* Reset Preset Register */
|
||||
for (j = 0; j < 3; j++)
|
||||
outb(0x00, base_offset);
|
||||
/* Reset Borrow, Carry, Compare, and Sign flags */
|
||||
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
|
||||
/* Reset Error flag */
|
||||
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
|
||||
/* Binary encoding; Normal count; non-quadrature mode */
|
||||
outb(QUAD8_CTR_CMR, base_offset + 1);
|
||||
/* Disable A and B inputs; preset on index; FLG1 as Carry */
|
||||
outb(QUAD8_CTR_IOR, base_offset + 1);
|
||||
/* Disable index function; negative index polarity */
|
||||
outb(QUAD8_CTR_IDR, base_offset + 1);
|
||||
}
|
||||
for (i = 0; i < QUAD8_NUM_COUNTERS; i++)
|
||||
quad8_init_counter(priv->base + 2 * i);
|
||||
/* Disable Differential Encoder Cable Status for all channels */
|
||||
outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS);
|
||||
iowrite8(0xFF, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
|
||||
/* Enable all counters and enable interrupt function */
|
||||
outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base[id] + QUAD8_REG_CHAN_OP);
|
||||
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC,
|
||||
priv->base + QUAD8_REG_CHAN_OP);
|
||||
|
||||
err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
|
||||
IRQF_SHARED, counter->name, counter);
|
||||
|
|
|
|||
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