[PATCH] ARM: Convert ARM timer implementations to use readl/writel
Convert ARMs timer implementations to use readl/writel instead of accessing the registers via a struct. People have recently asked if accessing timers via a structure is the "right way" and its not the Linux way. So fix this code to conform to "The Linux Way"(tm). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Russell King
Russell King
Родитель
6904b2465c
Коммит
b720f73296
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@ -20,6 +20,7 @@
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/hardware/amba.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/arch/cm.h>
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#include <asm/system.h>
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#include <asm/leds.h>
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@ -156,16 +157,6 @@ EXPORT_SYMBOL(cm_control);
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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/*
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* What does it look like?
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*/
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typedef struct TimerStruct {
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unsigned long TimerLoad;
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unsigned long TimerValue;
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unsigned long TimerControl;
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unsigned long TimerClear;
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} TimerStruct_t;
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static unsigned long timer_reload;
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/*
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@ -174,7 +165,6 @@ static unsigned long timer_reload;
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*/
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unsigned long integrator_gettimeoffset(void)
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{
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volatile TimerStruct_t *timer1 = (TimerStruct_t *)TIMER1_VA_BASE;
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unsigned long ticks1, ticks2, status;
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/*
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@ -183,11 +173,11 @@ unsigned long integrator_gettimeoffset(void)
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* an interrupt. We get around this by ensuring that the
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* counter has not reloaded between our two reads.
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*/
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ticks2 = timer1->TimerValue & 0xffff;
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ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
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do {
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ticks1 = ticks2;
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status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS);
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ticks2 = timer1->TimerValue & 0xffff;
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ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
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} while (ticks2 > ticks1);
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/*
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@ -213,20 +203,19 @@ unsigned long integrator_gettimeoffset(void)
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static irqreturn_t
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integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
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write_seqlock(&xtime_lock);
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/*
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* clear the interrupt
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*/
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timer1->TimerClear = 1;
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writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
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/*
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* the clock tick routines are only processed on the
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* primary CPU
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*/
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if (hard_smp_processor_id() == 0) {
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nmi_tick();
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timer_tick(regs);
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#ifdef CONFIG_SMP
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smp_send_timer();
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@ -256,32 +245,29 @@ static struct irqaction integrator_timer_irq = {
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*/
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void __init integrator_time_init(unsigned long reload, unsigned int ctrl)
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{
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volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
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volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
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volatile TimerStruct_t *timer2 = (volatile TimerStruct_t *)TIMER2_VA_BASE;
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unsigned int timer_ctrl = 0x80 | 0x40; /* periodic */
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unsigned int timer_ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
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timer_reload = reload;
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timer_ctrl |= ctrl;
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if (timer_reload > 0x100000) {
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timer_reload >>= 8;
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timer_ctrl |= 0x08; /* /256 */
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timer_ctrl |= TIMER_CTRL_DIV256;
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} else if (timer_reload > 0x010000) {
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timer_reload >>= 4;
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timer_ctrl |= 0x04; /* /16 */
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timer_ctrl |= TIMER_CTRL_DIV16;
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}
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/*
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* Initialise to a known state (all timers off)
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*/
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timer0->TimerControl = 0;
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timer1->TimerControl = 0;
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timer2->TimerControl = 0;
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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timer1->TimerLoad = timer_reload;
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timer1->TimerValue = timer_reload;
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timer1->TimerControl = timer_ctrl;
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writel(timer_reload, TIMER1_VA_BASE + TIMER_LOAD);
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writel(timer_reload, TIMER1_VA_BASE + TIMER_VALUE);
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writel(timer_ctrl, TIMER1_VA_BASE + TIMER_CTRL);
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/*
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* Make irqs happen for the system timer
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@ -33,6 +33,7 @@
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#include <asm/mach-types.h>
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#include <asm/hardware/amba.h>
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#include <asm/hardware/amba_clcd.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/icst307.h>
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#include <asm/mach/arch.h>
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@ -788,38 +789,25 @@ void __init versatile_init(void)
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 8) /* Divide by 256 */
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#define TIMER_CTRL 0x88 /* Enable, Clock / 256 */
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#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
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#define TIMER_CTRL 0x84 /* Enable, Clock / 16 */
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#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TIMER_RELOAD (TIMER_INTERVAL)
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#define TIMER_CTRL 0x80 /* Enable */
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#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
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/*
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* What does it look like?
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*/
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typedef struct TimerStruct {
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unsigned long TimerLoad;
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unsigned long TimerValue;
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unsigned long TimerControl;
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unsigned long TimerClear;
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} TimerStruct_t;
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/*
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* Returns number of ms since last clock interrupt. Note that interrupts
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* will have been disabled by do_gettimeoffset()
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*/
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static unsigned long versatile_gettimeoffset(void)
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{
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volatile TimerStruct_t *timer0 = (TimerStruct_t *)TIMER0_VA_BASE;
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unsigned long ticks1, ticks2, status;
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/*
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@ -828,11 +816,11 @@ static unsigned long versatile_gettimeoffset(void)
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* an interrupt. We get around this by ensuring that the
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* counter has not reloaded between our two reads.
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*/
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ticks2 = timer0->TimerValue & 0xffff;
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ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
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do {
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ticks1 = ticks2;
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status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
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ticks2 = timer0->TimerValue & 0xffff;
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ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
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} while (ticks2 > ticks1);
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/*
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@ -859,12 +847,10 @@ static unsigned long versatile_gettimeoffset(void)
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*/
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static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
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write_seqlock(&xtime_lock);
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// ...clear the interrupt
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timer0->TimerClear = 1;
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writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
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timer_tick(regs);
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@ -884,31 +870,32 @@ static struct irqaction versatile_timer_irq = {
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*/
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static void __init versatile_timer_init(void)
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{
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volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
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volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
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volatile TimerStruct_t *timer2 = (volatile TimerStruct_t *)TIMER2_VA_BASE;
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volatile TimerStruct_t *timer3 = (volatile TimerStruct_t *)TIMER3_VA_BASE;
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u32 val;
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/*
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* set clock frequency:
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* VERSATILE_REFCLK is 32KHz
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* VERSATILE_TIMCLK is 1MHz
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*/
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*(volatile unsigned int *)IO_ADDRESS(VERSATILE_SCTL_BASE) |=
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((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
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(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
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val = readl(IO_ADDRESS(VERSATILE_SCTL_BASE));
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writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
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(VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
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(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
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(VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
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IO_ADDRESS(VERSATILE_SCTL_BASE));
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/*
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* Initialise to a known state (all timers off)
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*/
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timer0->TimerControl = 0;
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timer1->TimerControl = 0;
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timer2->TimerControl = 0;
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timer3->TimerControl = 0;
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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writel(0, TIMER3_VA_BASE + TIMER_CTRL);
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timer0->TimerLoad = TIMER_RELOAD;
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timer0->TimerValue = TIMER_RELOAD;
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timer0->TimerControl = TIMER_CTRL | 0x40 | TIMER_CTRL_IE; /* periodic + IE */
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writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
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writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
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writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
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TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
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/*
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* Make irqs happen for the system timer
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@ -0,0 +1,21 @@
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#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
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#define __ASM_ARM_HARDWARE_ARM_TIMER_H
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#define TIMER_LOAD 0x00
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#define TIMER_VALUE 0x04
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#define TIMER_CTRL 0x08
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#define TIMER_CTRL_ONESHOT (1 << 0)
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#define TIMER_CTRL_32BIT (1 << 1)
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#define TIMER_CTRL_DIV1 (0 << 2)
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#define TIMER_CTRL_DIV16 (1 << 2)
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#define TIMER_CTRL_DIV256 (2 << 2)
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#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
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#define TIMER_CTRL_PERIODIC (1 << 6)
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#define TIMER_CTRL_ENABLE (1 << 7)
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#define TIMER_INTCLR 0x0c
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#define TIMER_RIS 0x10
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#define TIMER_MIS 0x14
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#define TIMER_BGLOAD 0x18
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#endif
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