InfiniBand/RDMA updates for 3.15-rc4:
- cxgb4 hardware driver fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJTYuHPAAoJEENa44ZhAt0hmHQP/2KKs001nv2MvjfUbn/VHxdq 5Hv/zlONa68QGYWxvA//tEvqUlbVr19gkBlbIwJ+SZ75BbsnoeeI27HEEiRzFX5t rQs+KnK7CYifDfzezfU1Ls8xjVhJfqQ09R6gwrcFutgM51bCIOl6AUxKk51MmdV4 d14XqWph8xPt5vs3hH6mzM9e1D9fBDJvkbAreT/sF4/broNFtBaHWe06fp7l7up/ lAG2Ynt6Uhc8HzfOFMY92uFk16QY+yGoUw64M9fYISx1smJUsVvEKyF3j0GJNbVt yR6qlHVMmzsI/dlQcB5x8XK9vX+jWq685C/MZ4ooeZwcVeT2qM2nT/gwVhsDYUNp 2D1vtiHbj8xNB87VdkVy5fQqcR61/gjX73NK/1qh/mul9GsekbTXfxDEcwMQV+Fn FMZNXms3iF35Wy7UkdI6fXgb+3Oq/FSADAyY0ntl9TLXg1Z4qpz6G6UxML6kznEN gNdQZxK+MKA16hPIdfKY8acTluPnG8K7tmy5G3zlVVAbLMvGhAE+M+cZATqRFZlC gddxtXE7j5eSfYwwl+wgbRP09HRmnHInQs2PUI2Vy5L7vIZAuqlQ9GW56FFhnGJh PEgQErUJf0NnnD86y1odxlvbdBTd94iElKhRRxwWEhPSvLb+ZeueDqZeqQUcobYw tXislPDdtLkZmOohOH+i =Y+Sv -----END PGP SIGNATURE----- Merge tag 'rdma-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband Pull infiniband/rdma fixes from Roland Dreier: "cxgb4 hardware driver fixes" * tag 'rdma-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: RDMA/cxgb4: Update Kconfig to include Chelsio T5 adapter RDMA/cxgb4: Only allow kernel db ringing for T4 devs RDMA/cxgb4: Force T5 connections to use TAHOE congestion control RDMA/cxgb4: Fix endpoint mutex deadlocks
This commit is contained in:
Linus Torvalds
Коммит
b7270cce7d
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@ -1,10 +1,10 @@
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config INFINIBAND_CXGB4
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tristate "Chelsio T4 RDMA Driver"
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tristate "Chelsio T4/T5 RDMA Driver"
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depends on CHELSIO_T4 && INET && (IPV6 || IPV6=n)
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select GENERIC_ALLOCATOR
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---help---
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This is an iWARP/RDMA driver for the Chelsio T4 1GbE and
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10GbE adapters.
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This is an iWARP/RDMA driver for the Chelsio T4 and T5
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1GbE, 10GbE adapters and T5 40GbE adapter.
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For general information about Chelsio and our products, visit
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our website at <http://www.chelsio.com>.
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@ -587,6 +587,10 @@ static int send_connect(struct c4iw_ep *ep)
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opt2 |= SACK_EN(1);
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if (wscale && enable_tcp_window_scaling)
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opt2 |= WND_SCALE_EN(1);
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if (is_t5(ep->com.dev->rdev.lldi.adapter_type)) {
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opt2 |= T5_OPT_2_VALID;
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opt2 |= V_CONG_CNTRL(CONG_ALG_TAHOE);
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}
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t4_set_arp_err_handler(skb, NULL, act_open_req_arp_failure);
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if (is_t4(ep->com.dev->rdev.lldi.adapter_type)) {
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@ -996,7 +1000,7 @@ static void close_complete_upcall(struct c4iw_ep *ep, int status)
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static int abort_connection(struct c4iw_ep *ep, struct sk_buff *skb, gfp_t gfp)
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{
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PDBG("%s ep %p tid %u\n", __func__, ep, ep->hwtid);
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state_set(&ep->com, ABORTING);
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__state_set(&ep->com, ABORTING);
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set_bit(ABORT_CONN, &ep->com.history);
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return send_abort(ep, skb, gfp);
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}
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@ -1154,7 +1158,7 @@ static int update_rx_credits(struct c4iw_ep *ep, u32 credits)
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return credits;
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}
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static void process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
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static int process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
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{
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struct mpa_message *mpa;
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struct mpa_v2_conn_params *mpa_v2_params;
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@ -1164,6 +1168,7 @@ static void process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
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struct c4iw_qp_attributes attrs;
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enum c4iw_qp_attr_mask mask;
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int err;
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int disconnect = 0;
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PDBG("%s ep %p tid %u\n", __func__, ep, ep->hwtid);
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@ -1173,7 +1178,7 @@ static void process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
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* will abort the connection.
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*/
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if (stop_ep_timer(ep))
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return;
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return 0;
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/*
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* If we get more than the supported amount of private data
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@ -1195,7 +1200,7 @@ static void process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
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* if we don't even have the mpa message, then bail.
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*/
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if (ep->mpa_pkt_len < sizeof(*mpa))
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return;
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return 0;
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mpa = (struct mpa_message *) ep->mpa_pkt;
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/* Validate MPA header. */
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@ -1235,7 +1240,7 @@ static void process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
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* We'll continue process when more data arrives.
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*/
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if (ep->mpa_pkt_len < (sizeof(*mpa) + plen))
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return;
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return 0;
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if (mpa->flags & MPA_REJECT) {
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err = -ECONNREFUSED;
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@ -1337,9 +1342,11 @@ static void process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
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attrs.layer_etype = LAYER_MPA | DDP_LLP;
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attrs.ecode = MPA_NOMATCH_RTR;
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attrs.next_state = C4IW_QP_STATE_TERMINATE;
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attrs.send_term = 1;
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err = c4iw_modify_qp(ep->com.qp->rhp, ep->com.qp,
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C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
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C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
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err = -ENOMEM;
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disconnect = 1;
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goto out;
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}
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@ -1355,9 +1362,11 @@ static void process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
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attrs.layer_etype = LAYER_MPA | DDP_LLP;
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attrs.ecode = MPA_INSUFF_IRD;
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attrs.next_state = C4IW_QP_STATE_TERMINATE;
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attrs.send_term = 1;
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err = c4iw_modify_qp(ep->com.qp->rhp, ep->com.qp,
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C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
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C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
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err = -ENOMEM;
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disconnect = 1;
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goto out;
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}
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goto out;
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@ -1366,7 +1375,7 @@ err:
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send_abort(ep, skb, GFP_KERNEL);
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out:
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connect_reply_upcall(ep, err);
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return;
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return disconnect;
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}
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static void process_mpa_request(struct c4iw_ep *ep, struct sk_buff *skb)
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@ -1524,6 +1533,7 @@ static int rx_data(struct c4iw_dev *dev, struct sk_buff *skb)
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unsigned int tid = GET_TID(hdr);
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struct tid_info *t = dev->rdev.lldi.tids;
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__u8 status = hdr->status;
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int disconnect = 0;
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ep = lookup_tid(t, tid);
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if (!ep)
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@ -1539,7 +1549,7 @@ static int rx_data(struct c4iw_dev *dev, struct sk_buff *skb)
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switch (ep->com.state) {
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case MPA_REQ_SENT:
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ep->rcv_seq += dlen;
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process_mpa_reply(ep, skb);
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disconnect = process_mpa_reply(ep, skb);
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break;
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case MPA_REQ_WAIT:
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ep->rcv_seq += dlen;
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@ -1555,13 +1565,16 @@ static int rx_data(struct c4iw_dev *dev, struct sk_buff *skb)
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ep->com.state, ep->hwtid, status);
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attrs.next_state = C4IW_QP_STATE_TERMINATE;
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c4iw_modify_qp(ep->com.qp->rhp, ep->com.qp,
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C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
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C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
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disconnect = 1;
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break;
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}
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default:
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break;
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}
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mutex_unlock(&ep->com.mutex);
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if (disconnect)
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c4iw_ep_disconnect(ep, 0, GFP_KERNEL);
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return 0;
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}
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@ -2009,6 +2022,10 @@ static void accept_cr(struct c4iw_ep *ep, struct sk_buff *skb,
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if (tcph->ece && tcph->cwr)
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opt2 |= CCTRL_ECN(1);
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}
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if (is_t5(ep->com.dev->rdev.lldi.adapter_type)) {
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opt2 |= T5_OPT_2_VALID;
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opt2 |= V_CONG_CNTRL(CONG_ALG_TAHOE);
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}
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rpl = cplhdr(skb);
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INIT_TP_WR(rpl, ep->hwtid);
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@ -3482,9 +3499,9 @@ static void process_timeout(struct c4iw_ep *ep)
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__func__, ep, ep->hwtid, ep->com.state);
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abort = 0;
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}
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mutex_unlock(&ep->com.mutex);
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if (abort)
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abort_connection(ep, NULL, GFP_KERNEL);
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mutex_unlock(&ep->com.mutex);
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c4iw_put_ep(&ep->com);
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}
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@ -435,6 +435,7 @@ struct c4iw_qp_attributes {
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u8 ecode;
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u16 sq_db_inc;
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u16 rq_db_inc;
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u8 send_term;
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};
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struct c4iw_qp {
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@ -1388,11 +1388,12 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
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qhp->attr.layer_etype = attrs->layer_etype;
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qhp->attr.ecode = attrs->ecode;
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ep = qhp->ep;
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disconnect = 1;
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c4iw_get_ep(&qhp->ep->com);
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if (!internal)
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if (!internal) {
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c4iw_get_ep(&qhp->ep->com);
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terminate = 1;
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else {
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disconnect = 1;
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} else {
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terminate = qhp->attr.send_term;
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ret = rdma_fini(rhp, qhp, ep);
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if (ret)
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goto err;
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@ -1776,11 +1777,15 @@ int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
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/*
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* Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
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* ringing the queue db when we're in DB_FULL mode.
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* Only allow this on T4 devices.
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*/
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attrs.sq_db_inc = attr->sq_psn;
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attrs.rq_db_inc = attr->rq_psn;
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mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
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mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
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if (is_t5(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
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(mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
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return -EINVAL;
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return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
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}
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@ -836,4 +836,18 @@ struct ulptx_idata {
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#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
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#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
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enum { /* TCP congestion control algorithms */
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CONG_ALG_RENO,
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CONG_ALG_TAHOE,
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CONG_ALG_NEWRENO,
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CONG_ALG_HIGHSPEED
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};
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#define S_CONG_CNTRL 14
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#define M_CONG_CNTRL 0x3
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#define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
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#define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL)
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#define T5_OPT_2_VALID (1 << 31)
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#endif /* _T4FW_RI_API_H_ */
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