phy: qcom-qmp: move PCS V5 registers to separate headers
Move PCS V5 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-17-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Vinod Koul
Родитель
41ad371f02
Коммит
b7a2f88257
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/* Only for QMP V5 PHY - PCS_PCIE registers */
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V5_H_
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/* Only for QMP V5 PHY - PCS_PCIE registers */
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#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
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#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
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#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
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#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
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#endif
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/* Only for QMP V5 PHY - UFS PCS registers */
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_
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#define QCOM_PHY_QMP_PCS_UFS_V5_H_
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/* Only for QMP V5 PHY - UFS PCS registers */
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#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
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#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
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#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
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#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
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#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
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#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
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#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
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#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
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#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
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#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
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#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
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#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
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#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
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#endif
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@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_USB_V5_H_
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#define QCOM_PHY_QMP_PCS_USB_V5_H_
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/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
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#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
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#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
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#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
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#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
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#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
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#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
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#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
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#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
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#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
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#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
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#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
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#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
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#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
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#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
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#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
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#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
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#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
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#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
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#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
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#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
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#endif
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V5_H_
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#define QCOM_PHY_QMP_PCS_V5_H_
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/* Only for QMP V5 PHY - USB/PCIe PCS registers */
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#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
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#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
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#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
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#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
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#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
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#endif
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@ -30,6 +30,11 @@
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#include "phy-qcom-qmp-pcs-usb-v4.h"
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#include "phy-qcom-qmp-pcs-ufs-v4.h"
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#include "phy-qcom-qmp-pcs-v5.h"
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#include "phy-qcom-qmp-pcs-pcie-v5.h"
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#include "phy-qcom-qmp-pcs-usb-v5.h"
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#include "phy-qcom-qmp-pcs-ufs-v5.h"
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/* Only for QMP V3 & V4 PHY - DP COM registers */
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#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
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#define QPHY_V3_DP_COM_SW_RESET 0x04
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@ -334,20 +339,6 @@
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#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
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#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
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/* Only for QMP V5 PHY - USB/PCIe PCS registers */
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#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
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#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
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#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
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#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
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#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
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/* Only for QMP V5 PHY - PCS_PCIE registers */
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#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
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#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
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#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
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#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
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/* Only for QMP V5_20 PHY - PCIe PCS registers */
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#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
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@ -356,48 +347,4 @@
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#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
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#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
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/* Only for QMP V5 PHY - UFS PCS registers */
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#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
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#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
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#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
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#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
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#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
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#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
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#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
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#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
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#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
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#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
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#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
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#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
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#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
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/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
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#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
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#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
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#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
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#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
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#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
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#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
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#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
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#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
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#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
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#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
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#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
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#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
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#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
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#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
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#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
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#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
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#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
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#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
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#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
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#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
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#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
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#endif
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