PCI: versatile: Add DT-based ARM Versatile PB PCIe host driver
This converts the Versatile PCI host code to a platform driver using the commom DT parsing and setup. The driver uses only an empty ARM pci_sys_data struct and does not use pci_common_init_dev init function. The old host code will be removed in a subsequent commit when Versatile is completely converted to DT. I've tested this on QEMU with the sym53c8xx driver in both i/o and memory mapped modes. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> CC: Russell King <linux@arm.linux.org.uk> CC: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rob Herring
Bjorn Helgaas
Родитель
daeea28793
Коммит
b7e78170ef
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@ -7210,6 +7210,14 @@ F: include/linux/pci*
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F: arch/x86/pci/
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F: arch/x86/kernel/quirks.c
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PCI DRIVER FOR ARM VERSATILE PLATFORM
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M: Rob Herring <robh@kernel.org>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/versatile.txt
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F: drivers/pci/host/pci-versatile.c
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PCI DRIVER FOR APPLIEDMICRO XGENE
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M: Tanmay Inamdar <tinamdar@apm.com>
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L: linux-pci@vger.kernel.org
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@ -102,4 +102,8 @@ config PCI_LAYERSCAPE
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help
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Say Y here if you want PCIe controller support on Layerscape SoCs.
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config PCI_VERSATILE
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bool "ARM Versatile PB PCI controller"
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depends on ARCH_VERSATILE
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endmenu
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@ -12,3 +12,4 @@ obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
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@ -0,0 +1,237 @@
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/*
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* Copyright 2004 Koninklijke Philips Electronics NV
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*
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* Conversion to platform driver and DT:
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* Copyright 2014 Linaro Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* 14/04/2005 Initial version, colin.king@philips.com
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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static void __iomem *versatile_pci_base;
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static void __iomem *versatile_cfg_base[2];
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#define PCI_IMAP(m) (versatile_pci_base + ((m) * 4))
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#define PCI_SMAP(m) (versatile_pci_base + 0x14 + ((m) * 4))
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#define PCI_SELFID (versatile_pci_base + 0xc)
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#define VP_PCI_DEVICE_ID 0x030010ee
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#define VP_PCI_CLASS_ID 0x0b400000
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static u32 pci_slot_ignore;
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static int __init versatile_pci_slot_ignore(char *str)
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{
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int retval;
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int slot;
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while ((retval = get_option(&str, &slot))) {
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if ((slot < 0) || (slot > 31))
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pr_err("Illegal slot value: %d\n", slot);
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else
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pci_slot_ignore |= (1 << slot);
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}
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return 1;
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}
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__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
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static void __iomem *versatile_map_bus(struct pci_bus *bus,
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unsigned int devfn, int offset)
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{
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unsigned int busnr = bus->number;
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if (pci_slot_ignore & (1 << PCI_SLOT(devfn)))
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return NULL;
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return versatile_cfg_base[1] + ((busnr << 16) | (devfn << 8) | offset);
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}
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static struct pci_ops pci_versatile_ops = {
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.map_bus = versatile_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write,
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};
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static int versatile_pci_parse_request_of_pci_ranges(struct device *dev,
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struct list_head *res)
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{
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int err, mem = 1, res_valid = 0;
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struct device_node *np = dev->of_node;
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resource_size_t iobase;
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struct pci_host_bridge_window *win;
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err = of_pci_get_host_bridge_resources(np, 0, 0xff, res, &iobase);
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if (err)
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return err;
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list_for_each_entry(win, res, list) {
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struct resource *parent, *res = win->res;
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switch (resource_type(res)) {
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case IORESOURCE_IO:
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parent = &ioport_resource;
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err = pci_remap_iospace(res, iobase);
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if (err) {
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dev_warn(dev, "error %d: failed to map resource %pR\n",
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err, res);
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continue;
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}
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break;
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case IORESOURCE_MEM:
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parent = &iomem_resource;
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res_valid |= !(res->flags & IORESOURCE_PREFETCH);
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writel(res->start >> 28, PCI_IMAP(mem));
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writel(PHYS_OFFSET >> 28, PCI_SMAP(mem));
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mem++;
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break;
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case IORESOURCE_BUS:
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default:
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continue;
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}
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err = devm_request_resource(dev, parent, res);
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if (err)
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goto out_release_res;
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}
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if (!res_valid) {
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dev_err(dev, "non-prefetchable memory resource required\n");
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err = -EINVAL;
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goto out_release_res;
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}
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return 0;
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out_release_res:
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pci_free_resource_list(res);
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return err;
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}
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/* Unused, temporary to satisfy ARM arch code */
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struct pci_sys_data sys;
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static int versatile_pci_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int ret, i, myslot = -1;
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u32 val;
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void __iomem *local_pci_cfg_base;
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struct pci_bus *bus;
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LIST_HEAD(pci_res);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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versatile_pci_base = devm_ioremap_resource(&pdev->dev, res);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res)
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return -ENODEV;
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versatile_cfg_base[0] = devm_ioremap_resource(&pdev->dev, res);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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if (!res)
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return -ENODEV;
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versatile_cfg_base[1] = devm_ioremap_resource(&pdev->dev, res);
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ret = versatile_pci_parse_request_of_pci_ranges(&pdev->dev, &pci_res);
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if (ret)
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return ret;
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/*
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* We need to discover the PCI core first to configure itself
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* before the main PCI probing is performed
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*/
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for (i = 0; i < 32; i++) {
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if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) &&
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(readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) {
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myslot = i;
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break;
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}
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}
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if (myslot == -1) {
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dev_err(&pdev->dev, "Cannot find PCI core!\n");
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return -EIO;
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}
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/*
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* Do not to map Versatile FPGA PCI device into memory space
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*/
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pci_slot_ignore |= (1 << myslot);
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dev_info(&pdev->dev, "PCI core found (slot %d)\n", myslot);
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writel(myslot, PCI_SELFID);
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local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11);
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val = readl(local_pci_cfg_base + PCI_COMMAND);
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val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
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writel(val, local_pci_cfg_base + PCI_COMMAND);
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/*
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* Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
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*/
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writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
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writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
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writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
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/*
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* For many years the kernel and QEMU were symbiotically buggy
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* in that they both assumed the same broken IRQ mapping.
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* QEMU therefore attempts to auto-detect old broken kernels
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* so that they still work on newer QEMU as they did on old
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* QEMU. Since we now use the correct (ie matching-hardware)
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* IRQ mapping we write a definitely different value to a
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* PCI_INTERRUPT_LINE register to tell QEMU that we expect
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* real hardware behaviour and it need not be backwards
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* compatible for us. This write is harmless on real hardware.
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*/
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writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
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pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
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pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC);
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bus = pci_scan_root_bus(&pdev->dev, 0, &pci_versatile_ops, &sys, &pci_res);
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if (!bus)
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return -ENOMEM;
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pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
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pci_assign_unassigned_bus_resources(bus);
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return 0;
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}
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static const struct of_device_id versatile_pci_of_match[] = {
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{ .compatible = "arm,versatile-pci", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, versatile_pci_of_match);
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static struct platform_driver versatile_pci_driver = {
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.driver = {
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.name = "versatile-pci",
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.of_match_table = versatile_pci_of_match,
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},
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.probe = versatile_pci_probe,
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};
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module_platform_driver(versatile_pci_driver);
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MODULE_DESCRIPTION("Versatile PCI driver");
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MODULE_LICENSE("GPL v2");
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