sh-pfc: sh73a0: Add bias (pull-up/down) pinconf support
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Laurent Pinchart
Родитель
55f11f0ec1
Коммит
b8238993ed
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@ -18,10 +18,14 @@
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* along with this program; if not, write to the Free Software
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <mach/sh73a0.h>
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#include <mach/sh73a0.h>
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#include <mach/irqs.h>
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#include <mach/irqs.h>
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#include "core.h"
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#include "sh_pfc.h"
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#include "sh_pfc.h"
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#define CPU_ALL_PORT(fn, pfx, sfx) \
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#define CPU_ALL_PORT(fn, pfx, sfx) \
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@ -1539,8 +1543,300 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
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PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
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};
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};
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#define SH73A0_PIN(pin, cfgs) \
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{ \
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.name = __stringify(PORT##pin), \
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.enum_id = PORT##pin##_DATA, \
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.configs = cfgs, \
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}
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#define __I (SH_PFC_PIN_CFG_INPUT)
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#define __O (SH_PFC_PIN_CFG_OUTPUT)
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#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
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#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
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#define __PU (SH_PFC_PIN_CFG_PULL_UP)
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#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
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#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
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#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
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#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
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#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
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#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
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#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
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#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
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#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
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static struct sh_pfc_pin pinmux_pins[] = {
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static struct sh_pfc_pin pinmux_pins[] = {
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GPIO_PORT_ALL(),
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/* Table 25-1 (I/O and Pull U/D) */
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SH73A0_PIN_I_PD(0),
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SH73A0_PIN_I_PU(1),
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SH73A0_PIN_I_PU(2),
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SH73A0_PIN_I_PU(3),
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SH73A0_PIN_I_PU(4),
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SH73A0_PIN_I_PU(5),
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SH73A0_PIN_I_PU(6),
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SH73A0_PIN_I_PU(7),
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SH73A0_PIN_I_PU(8),
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SH73A0_PIN_I_PD(9),
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SH73A0_PIN_I_PD(10),
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SH73A0_PIN_I_PU_PD(11),
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SH73A0_PIN_IO_PU_PD(12),
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SH73A0_PIN_IO_PU_PD(13),
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SH73A0_PIN_IO_PU_PD(14),
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SH73A0_PIN_IO_PU_PD(15),
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SH73A0_PIN_IO_PD(16),
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SH73A0_PIN_IO_PD(17),
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SH73A0_PIN_IO_PU(18),
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SH73A0_PIN_IO_PU(19),
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SH73A0_PIN_O(20),
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SH73A0_PIN_O(21),
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SH73A0_PIN_O(22),
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SH73A0_PIN_O(23),
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SH73A0_PIN_O(24),
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SH73A0_PIN_I_PD(25),
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SH73A0_PIN_I_PD(26),
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SH73A0_PIN_IO_PU(27),
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SH73A0_PIN_IO_PU(28),
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SH73A0_PIN_IO_PD(29),
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SH73A0_PIN_IO_PD(30),
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SH73A0_PIN_IO_PU(31),
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SH73A0_PIN_IO_PD(32),
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SH73A0_PIN_I_PU_PD(33),
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SH73A0_PIN_IO_PD(34),
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SH73A0_PIN_I_PU_PD(35),
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SH73A0_PIN_IO_PD(36),
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SH73A0_PIN_IO(37),
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SH73A0_PIN_O(38),
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SH73A0_PIN_I_PU(39),
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SH73A0_PIN_I_PU_PD(40),
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SH73A0_PIN_O(41),
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SH73A0_PIN_IO_PD(42),
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SH73A0_PIN_IO_PU_PD(43),
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SH73A0_PIN_IO_PU_PD(44),
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SH73A0_PIN_IO_PD(45),
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SH73A0_PIN_IO_PD(46),
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SH73A0_PIN_IO_PD(47),
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SH73A0_PIN_I_PD(48),
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SH73A0_PIN_IO_PU_PD(49),
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SH73A0_PIN_IO_PD(50),
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SH73A0_PIN_IO_PD(51),
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SH73A0_PIN_O(52),
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SH73A0_PIN_IO_PU_PD(53),
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SH73A0_PIN_IO_PU_PD(54),
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SH73A0_PIN_IO_PD(55),
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SH73A0_PIN_I_PU_PD(56),
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SH73A0_PIN_IO(57),
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SH73A0_PIN_IO(58),
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SH73A0_PIN_IO(59),
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SH73A0_PIN_IO(60),
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SH73A0_PIN_IO(61),
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SH73A0_PIN_IO_PD(62),
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SH73A0_PIN_IO_PD(63),
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SH73A0_PIN_IO_PU_PD(64),
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SH73A0_PIN_IO_PD(65),
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SH73A0_PIN_IO_PU_PD(66),
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SH73A0_PIN_IO_PU_PD(67),
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SH73A0_PIN_IO_PU_PD(68),
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SH73A0_PIN_IO_PU_PD(69),
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SH73A0_PIN_IO_PU_PD(70),
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SH73A0_PIN_IO_PU_PD(71),
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SH73A0_PIN_IO_PU_PD(72),
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SH73A0_PIN_I_PU_PD(73),
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SH73A0_PIN_IO_PU(74),
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SH73A0_PIN_IO_PU(75),
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SH73A0_PIN_IO_PU(76),
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SH73A0_PIN_IO_PU(77),
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SH73A0_PIN_IO_PU(78),
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SH73A0_PIN_IO_PU(79),
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SH73A0_PIN_IO_PU(80),
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SH73A0_PIN_IO_PU(81),
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SH73A0_PIN_IO_PU(82),
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SH73A0_PIN_IO_PU(83),
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SH73A0_PIN_IO_PU(84),
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SH73A0_PIN_IO_PU(85),
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SH73A0_PIN_IO_PU(86),
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SH73A0_PIN_IO_PU(87),
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SH73A0_PIN_IO_PU(88),
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SH73A0_PIN_IO_PU(89),
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SH73A0_PIN_O(90),
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SH73A0_PIN_IO_PU(91),
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SH73A0_PIN_O(92),
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SH73A0_PIN_IO_PU(93),
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SH73A0_PIN_O(94),
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SH73A0_PIN_I_PU_PD(95),
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SH73A0_PIN_IO(96),
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SH73A0_PIN_IO(97),
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SH73A0_PIN_IO(98),
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SH73A0_PIN_I_PU(99),
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SH73A0_PIN_O(100),
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SH73A0_PIN_O(101),
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SH73A0_PIN_I_PU(102),
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SH73A0_PIN_IO_PD(103),
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SH73A0_PIN_I_PU_PD(104),
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SH73A0_PIN_I_PD(105),
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SH73A0_PIN_I_PD(106),
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SH73A0_PIN_I_PU_PD(107),
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SH73A0_PIN_I_PU_PD(108),
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SH73A0_PIN_IO_PD(109),
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SH73A0_PIN_IO_PD(110),
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SH73A0_PIN_IO_PU_PD(111),
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SH73A0_PIN_IO_PU_PD(112),
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SH73A0_PIN_IO_PU_PD(113),
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SH73A0_PIN_IO_PD(114),
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SH73A0_PIN_IO_PU(115),
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SH73A0_PIN_IO_PU(116),
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SH73A0_PIN_IO_PU_PD(117),
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SH73A0_PIN_IO_PU_PD(118),
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SH73A0_PIN_IO_PD(128),
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SH73A0_PIN_IO_PD(129),
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SH73A0_PIN_IO_PU_PD(130),
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SH73A0_PIN_IO_PD(131),
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SH73A0_PIN_IO_PD(132),
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SH73A0_PIN_IO_PD(133),
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SH73A0_PIN_IO_PU_PD(134),
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SH73A0_PIN_IO_PU_PD(135),
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SH73A0_PIN_IO_PU_PD(136),
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SH73A0_PIN_IO_PU_PD(137),
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SH73A0_PIN_IO_PD(138),
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SH73A0_PIN_IO_PD(139),
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SH73A0_PIN_IO_PD(140),
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SH73A0_PIN_IO_PD(141),
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SH73A0_PIN_IO_PD(142),
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SH73A0_PIN_IO_PD(143),
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SH73A0_PIN_IO_PU_PD(144),
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SH73A0_PIN_IO_PD(145),
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SH73A0_PIN_IO_PU_PD(146),
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SH73A0_PIN_IO_PU_PD(147),
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SH73A0_PIN_IO_PU_PD(148),
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SH73A0_PIN_IO_PU_PD(149),
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SH73A0_PIN_I_PU_PD(150),
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SH73A0_PIN_IO_PU_PD(151),
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SH73A0_PIN_IO_PU_PD(152),
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SH73A0_PIN_IO_PD(153),
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SH73A0_PIN_IO_PD(154),
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SH73A0_PIN_I_PU_PD(155),
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SH73A0_PIN_IO_PU_PD(156),
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SH73A0_PIN_I_PD(157),
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SH73A0_PIN_IO_PD(158),
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SH73A0_PIN_IO_PU_PD(159),
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SH73A0_PIN_IO_PU_PD(160),
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SH73A0_PIN_I_PU_PD(161),
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SH73A0_PIN_I_PU_PD(162),
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SH73A0_PIN_IO_PU_PD(163),
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SH73A0_PIN_I_PU_PD(164),
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SH73A0_PIN_IO_PD(192),
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SH73A0_PIN_IO_PU_PD(193),
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SH73A0_PIN_IO_PD(194),
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SH73A0_PIN_IO_PU_PD(195),
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SH73A0_PIN_IO_PD(196),
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SH73A0_PIN_IO_PD(197),
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SH73A0_PIN_IO_PD(198),
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SH73A0_PIN_IO_PD(199),
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SH73A0_PIN_IO_PU_PD(200),
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SH73A0_PIN_IO_PU_PD(201),
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SH73A0_PIN_IO_PU_PD(202),
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SH73A0_PIN_IO_PU_PD(203),
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SH73A0_PIN_IO_PU_PD(204),
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SH73A0_PIN_IO_PU_PD(205),
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SH73A0_PIN_IO_PU_PD(206),
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SH73A0_PIN_IO_PD(207),
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SH73A0_PIN_IO_PD(208),
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SH73A0_PIN_IO_PD(209),
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SH73A0_PIN_IO_PD(210),
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SH73A0_PIN_IO_PD(211),
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SH73A0_PIN_IO_PD(212),
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SH73A0_PIN_IO_PD(213),
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SH73A0_PIN_IO_PU_PD(214),
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SH73A0_PIN_IO_PU_PD(215),
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SH73A0_PIN_IO_PD(216),
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SH73A0_PIN_IO_PD(217),
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SH73A0_PIN_O(218),
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SH73A0_PIN_IO_PD(219),
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SH73A0_PIN_IO_PD(220),
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SH73A0_PIN_IO_PU_PD(221),
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SH73A0_PIN_IO_PU_PD(222),
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SH73A0_PIN_I_PU_PD(223),
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SH73A0_PIN_I_PU_PD(224),
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SH73A0_PIN_IO_PU_PD(225),
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SH73A0_PIN_O(226),
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SH73A0_PIN_IO_PU_PD(227),
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SH73A0_PIN_I_PU_PD(228),
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SH73A0_PIN_I_PD(229),
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|
SH73A0_PIN_IO(230),
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|
SH73A0_PIN_IO_PU_PD(231),
|
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|
SH73A0_PIN_IO_PU_PD(232),
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|
SH73A0_PIN_I_PU_PD(233),
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|
SH73A0_PIN_IO_PU_PD(234),
|
||||||
|
SH73A0_PIN_IO_PU_PD(235),
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||||||
|
SH73A0_PIN_IO_PU_PD(236),
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||||||
|
SH73A0_PIN_IO_PD(237),
|
||||||
|
SH73A0_PIN_IO_PU_PD(238),
|
||||||
|
SH73A0_PIN_IO_PU_PD(239),
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||||||
|
SH73A0_PIN_IO_PU_PD(240),
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||||||
|
SH73A0_PIN_O(241),
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||||||
|
SH73A0_PIN_I_PD(242),
|
||||||
|
SH73A0_PIN_IO_PU_PD(243),
|
||||||
|
SH73A0_PIN_IO_PU_PD(244),
|
||||||
|
SH73A0_PIN_IO_PU_PD(245),
|
||||||
|
SH73A0_PIN_IO_PU_PD(246),
|
||||||
|
SH73A0_PIN_IO_PU_PD(247),
|
||||||
|
SH73A0_PIN_IO_PU_PD(248),
|
||||||
|
SH73A0_PIN_IO_PU_PD(249),
|
||||||
|
SH73A0_PIN_IO_PU_PD(250),
|
||||||
|
SH73A0_PIN_IO_PU_PD(251),
|
||||||
|
SH73A0_PIN_IO_PU_PD(252),
|
||||||
|
SH73A0_PIN_IO_PU_PD(253),
|
||||||
|
SH73A0_PIN_IO_PU_PD(254),
|
||||||
|
SH73A0_PIN_IO_PU_PD(255),
|
||||||
|
SH73A0_PIN_IO_PU_PD(256),
|
||||||
|
SH73A0_PIN_IO_PU_PD(257),
|
||||||
|
SH73A0_PIN_IO_PU_PD(258),
|
||||||
|
SH73A0_PIN_IO_PU_PD(259),
|
||||||
|
SH73A0_PIN_IO_PU_PD(260),
|
||||||
|
SH73A0_PIN_IO_PU_PD(261),
|
||||||
|
SH73A0_PIN_IO_PU_PD(262),
|
||||||
|
SH73A0_PIN_IO_PU_PD(263),
|
||||||
|
SH73A0_PIN_IO_PU_PD(264),
|
||||||
|
SH73A0_PIN_IO_PU_PD(265),
|
||||||
|
SH73A0_PIN_IO_PU_PD(266),
|
||||||
|
SH73A0_PIN_IO_PU_PD(267),
|
||||||
|
SH73A0_PIN_IO_PU_PD(268),
|
||||||
|
SH73A0_PIN_IO_PU_PD(269),
|
||||||
|
SH73A0_PIN_IO_PU_PD(270),
|
||||||
|
SH73A0_PIN_IO_PU_PD(271),
|
||||||
|
SH73A0_PIN_IO_PU_PD(272),
|
||||||
|
SH73A0_PIN_IO_PU_PD(273),
|
||||||
|
SH73A0_PIN_IO_PU_PD(274),
|
||||||
|
SH73A0_PIN_IO_PU_PD(275),
|
||||||
|
SH73A0_PIN_IO_PU_PD(276),
|
||||||
|
SH73A0_PIN_IO_PU_PD(277),
|
||||||
|
SH73A0_PIN_IO_PU_PD(278),
|
||||||
|
SH73A0_PIN_IO_PU_PD(279),
|
||||||
|
SH73A0_PIN_IO_PU_PD(280),
|
||||||
|
SH73A0_PIN_O(281),
|
||||||
|
SH73A0_PIN_O(282),
|
||||||
|
SH73A0_PIN_I_PU(288),
|
||||||
|
SH73A0_PIN_IO_PU_PD(289),
|
||||||
|
SH73A0_PIN_IO_PU_PD(290),
|
||||||
|
SH73A0_PIN_IO_PU_PD(291),
|
||||||
|
SH73A0_PIN_IO_PU_PD(292),
|
||||||
|
SH73A0_PIN_IO_PU_PD(293),
|
||||||
|
SH73A0_PIN_IO_PU_PD(294),
|
||||||
|
SH73A0_PIN_IO_PU_PD(295),
|
||||||
|
SH73A0_PIN_IO_PU_PD(296),
|
||||||
|
SH73A0_PIN_IO_PU_PD(297),
|
||||||
|
SH73A0_PIN_IO_PU_PD(298),
|
||||||
|
SH73A0_PIN_IO_PU_PD(299),
|
||||||
|
SH73A0_PIN_IO_PU_PD(300),
|
||||||
|
SH73A0_PIN_IO_PU_PD(301),
|
||||||
|
SH73A0_PIN_IO_PU_PD(302),
|
||||||
|
SH73A0_PIN_IO_PU_PD(303),
|
||||||
|
SH73A0_PIN_IO_PU_PD(304),
|
||||||
|
SH73A0_PIN_IO_PU_PD(305),
|
||||||
|
SH73A0_PIN_O(306),
|
||||||
|
SH73A0_PIN_O(307),
|
||||||
|
SH73A0_PIN_I_PU(308),
|
||||||
|
SH73A0_PIN_O(309),
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct pinmux_range pinmux_ranges[] = {
|
static const struct pinmux_range pinmux_ranges[] = {
|
||||||
|
|
@ -2779,8 +3075,61 @@ static const struct pinmux_irq pinmux_irqs[] = {
|
||||||
PINMUX_IRQ(EXT_IRQ16L(9), 308),
|
PINMUX_IRQ(EXT_IRQ16L(9), 308),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#define PORTnCR_PULMD_OFF (0 << 6)
|
||||||
|
#define PORTnCR_PULMD_DOWN (2 << 6)
|
||||||
|
#define PORTnCR_PULMD_UP (3 << 6)
|
||||||
|
#define PORTnCR_PULMD_MASK (3 << 6)
|
||||||
|
|
||||||
|
static const unsigned int sh73a0_portcr_offsets[] = {
|
||||||
|
0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
|
||||||
|
0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
|
||||||
|
};
|
||||||
|
|
||||||
|
static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
|
||||||
|
{
|
||||||
|
void __iomem *addr = pfc->window->virt
|
||||||
|
+ sh73a0_portcr_offsets[pin >> 5] + pin;
|
||||||
|
u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
|
||||||
|
|
||||||
|
switch (value) {
|
||||||
|
case PORTnCR_PULMD_UP:
|
||||||
|
return PIN_CONFIG_BIAS_PULL_UP;
|
||||||
|
case PORTnCR_PULMD_DOWN:
|
||||||
|
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||||
|
case PORTnCR_PULMD_OFF:
|
||||||
|
default:
|
||||||
|
return PIN_CONFIG_BIAS_DISABLE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||||
|
unsigned int bias)
|
||||||
|
{
|
||||||
|
void __iomem *addr = pfc->window->virt
|
||||||
|
+ sh73a0_portcr_offsets[pin >> 5] + pin;
|
||||||
|
u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
|
||||||
|
|
||||||
|
switch (bias) {
|
||||||
|
case PIN_CONFIG_BIAS_PULL_UP:
|
||||||
|
value |= PORTnCR_PULMD_UP;
|
||||||
|
break;
|
||||||
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||||
|
value |= PORTnCR_PULMD_DOWN;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
iowrite8(value, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
|
||||||
|
.get_bias = sh73a0_pinmux_get_bias,
|
||||||
|
.set_bias = sh73a0_pinmux_set_bias,
|
||||||
|
};
|
||||||
|
|
||||||
const struct sh_pfc_soc_info sh73a0_pinmux_info = {
|
const struct sh_pfc_soc_info sh73a0_pinmux_info = {
|
||||||
.name = "sh73a0_pfc",
|
.name = "sh73a0_pfc",
|
||||||
|
.ops = &sh73a0_pinmux_ops,
|
||||||
|
|
||||||
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
|
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
|
||||||
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
|
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
|
||||||
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
|
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
|
||||||
|
|
|
||||||
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