clk: samsung: fsd: Add cam_csi block clock information
Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work. Cc: linux-fsd@tesla.com Signed-off-by: Sathyakam M <sathya@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-11-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Alim Akhtar
Krzysztof Kozlowski
Родитель
75c50afaa0
Коммит
b826c3e4de
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@ -1545,6 +1545,210 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
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.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
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};
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/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
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#define PLL_LOCKTIME_PLL_CAM_CSI 0x0
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#define PLL_CON0_PLL_CAM_CSI 0x100
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#define DIV_CAM_CSI0_ACLK 0x1800
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#define DIV_CAM_CSI1_ACLK 0x1804
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#define DIV_CAM_CSI2_ACLK 0x1808
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#define DIV_CAM_CSI_BUSD 0x180c
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#define DIV_CAM_CSI_BUSP 0x1810
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#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
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#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
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#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
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#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
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#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
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#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
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#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
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#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
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#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
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#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
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#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
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#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
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#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
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#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
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#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
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#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
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#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
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#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
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#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
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#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
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#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
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#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
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#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
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#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
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#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
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#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
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#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
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#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
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#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
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#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
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#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
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#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
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#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
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#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
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#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
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static const unsigned long cam_csi_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_CAM_CSI,
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PLL_CON0_PLL_CAM_CSI,
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DIV_CAM_CSI0_ACLK,
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DIV_CAM_CSI1_ACLK,
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DIV_CAM_CSI2_ACLK,
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DIV_CAM_CSI_BUSD,
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DIV_CAM_CSI_BUSP,
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GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
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GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
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GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
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GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
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GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
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GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
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GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
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GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
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GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
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};
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static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
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PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0),
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};
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static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
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PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
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PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
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};
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PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
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static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
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MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
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};
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static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
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DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
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DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
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DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
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DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
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DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
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};
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static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
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GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
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GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
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CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
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GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
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GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
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GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
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GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
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GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
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GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
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GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
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GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
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GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
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GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
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GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
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GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
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GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
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GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
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"dout_cam_csi_busd",
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GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
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CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
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"dout_cam_csi_busp",
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GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
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CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
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GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
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GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
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};
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static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
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.pll_clks = cam_csi_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks),
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.mux_clks = cam_csi_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks),
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.div_clks = cam_csi_div_clks,
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.nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
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.gate_clks = cam_csi_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
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.nr_clk_ids = CAM_CSI_NR_CLK,
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.clk_regs = cam_csi_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
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};
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/**
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* fsd_cmu_probe - Probe function for FSD platform clocks
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* @pdev: Pointer to platform device
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@ -1576,6 +1780,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
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}, {
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.compatible = "tesla,fsd-clock-mfc",
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.data = &mfc_cmu_info,
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}, {
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.compatible = "tesla,fsd-clock-cam_csi",
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.data = &cam_csi_cmu_info,
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}, {
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},
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};
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