clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver
Add an LCC driver for MSM8960/APQ8064 that supports the i2s, slimbus, and pcm clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
This commit is contained in:
Stephen Boyd
Michael Turquette
Родитель
c99e515a92
Коммит
b82875ee07
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@ -54,6 +54,15 @@ config MSM_GCC_8960
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Say Y if you want to use peripheral devices such as UART, SPI,
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i2c, USB, SD/eMMC, SATA, PCIe, etc.
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config MSM_LCC_8960
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tristate "APQ8064/MSM8960 LPASS Clock Controller"
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select MSM_GCC_8960
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depends on COMMON_CLK_QCOM
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help
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Support for the LPASS clock controller on apq8064/msm8960 devices.
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Say Y if you want to use audio devices such as i2s, pcm,
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SLIMBus, etc.
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config MSM_MMCC_8960
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tristate "MSM8960 Multimedia Clock Controller"
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select MSM_GCC_8960
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@ -16,6 +16,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
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obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
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obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
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obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
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obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
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obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
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obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
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obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
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@ -0,0 +1,585 @@
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,lcc-msm8960.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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static struct clk_pll pll4 = {
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.l_reg = 0x4,
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.m_reg = 0x8,
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.n_reg = 0xc,
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.config_reg = 0x14,
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.mode_reg = 0x0,
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.status_reg = 0x18,
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.status_bit = 16,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pll4",
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.parent_names = (const char *[]){ "pxo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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#define P_PXO 0
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#define P_PLL4 1
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static const u8 lcc_pxo_pll4_map[] = {
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[P_PXO] = 0,
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[P_PLL4] = 2,
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};
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static const char *lcc_pxo_pll4[] = {
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"pxo",
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"pll4_vote",
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};
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static struct freq_tbl clk_tbl_aif_osr_492[] = {
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{ 512000, P_PLL4, 4, 1, 240 },
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{ 768000, P_PLL4, 4, 1, 160 },
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{ 1024000, P_PLL4, 4, 1, 120 },
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{ 1536000, P_PLL4, 4, 1, 80 },
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{ 2048000, P_PLL4, 4, 1, 60 },
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{ 3072000, P_PLL4, 4, 1, 40 },
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{ 4096000, P_PLL4, 4, 1, 30 },
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{ 6144000, P_PLL4, 4, 1, 20 },
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{ 8192000, P_PLL4, 4, 1, 15 },
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{ 12288000, P_PLL4, 4, 1, 10 },
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{ 24576000, P_PLL4, 4, 1, 5 },
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{ 27000000, P_PXO, 1, 0, 0 },
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{ }
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};
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static struct freq_tbl clk_tbl_aif_osr_393[] = {
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{ 512000, P_PLL4, 4, 1, 192 },
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{ 768000, P_PLL4, 4, 1, 128 },
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{ 1024000, P_PLL4, 4, 1, 96 },
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{ 1536000, P_PLL4, 4, 1, 64 },
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{ 2048000, P_PLL4, 4, 1, 48 },
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{ 3072000, P_PLL4, 4, 1, 32 },
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{ 4096000, P_PLL4, 4, 1, 24 },
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{ 6144000, P_PLL4, 4, 1, 16 },
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{ 8192000, P_PLL4, 4, 1, 12 },
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{ 12288000, P_PLL4, 4, 1, 8 },
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{ 24576000, P_PLL4, 4, 1, 4 },
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{ 27000000, P_PXO, 1, 0, 0 },
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{ }
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};
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static struct clk_rcg mi2s_osr_src = {
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.ns_reg = 0x48,
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.md_reg = 0x4c,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 24,
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.m_val_shift = 8,
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.width = 8,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_pxo_pll4_map,
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},
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.freq_tbl = clk_tbl_aif_osr_393,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_osr_src",
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.parent_names = lcc_pxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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static const char *lcc_mi2s_parents[] = {
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"mi2s_osr_src",
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};
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static struct clk_branch mi2s_osr_clk = {
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.halt_reg = 0x50,
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.halt_bit = 1,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(17),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_osr_clk",
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.parent_names = lcc_mi2s_parents,
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_div mi2s_div_clk = {
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.reg = 0x48,
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.shift = 10,
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.width = 4,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_div_clk",
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.parent_names = lcc_mi2s_parents,
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_branch mi2s_bit_div_clk = {
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.halt_reg = 0x50,
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.halt_bit = 0,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_bit_div_clk",
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.parent_names = (const char *[]){ "mi2s_div_clk" },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_mux mi2s_bit_clk = {
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.reg = 0x48,
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.shift = 14,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_bit_clk",
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.parent_names = (const char *[]){
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"mi2s_bit_div_clk",
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"mi2s_codec_clk",
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},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
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static struct clk_rcg prefix##_osr_src = { \
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.ns_reg = _ns, \
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.md_reg = _md, \
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.mn = { \
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.mnctr_en_bit = 8, \
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.mnctr_reset_bit = 7, \
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.mnctr_mode_shift = 5, \
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.n_val_shift = 24, \
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.m_val_shift = 8, \
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.width = 8, \
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}, \
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.p = { \
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.pre_div_shift = 3, \
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.pre_div_width = 2, \
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}, \
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.s = { \
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.src_sel_shift = 0, \
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.parent_map = lcc_pxo_pll4_map, \
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}, \
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.freq_tbl = clk_tbl_aif_osr_393, \
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.clkr = { \
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.enable_reg = _ns, \
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.enable_mask = BIT(9), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_osr_src", \
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.parent_names = lcc_pxo_pll4, \
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.num_parents = 2, \
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.ops = &clk_rcg_ops, \
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.flags = CLK_SET_RATE_GATE, \
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}, \
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}, \
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}; \
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\
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static const char *lcc_##prefix##_parents[] = { \
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#prefix "_osr_src", \
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}; \
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\
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static struct clk_branch prefix##_osr_clk = { \
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.halt_reg = hr, \
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.halt_bit = 1, \
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.halt_check = BRANCH_HALT_ENABLE, \
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.clkr = { \
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.enable_reg = _ns, \
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.enable_mask = BIT(21), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_osr_clk", \
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.parent_names = lcc_##prefix##_parents, \
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.num_parents = 1, \
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.ops = &clk_branch_ops, \
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.flags = CLK_SET_RATE_PARENT, \
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}, \
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}, \
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}; \
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\
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static struct clk_regmap_div prefix##_div_clk = { \
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.reg = _ns, \
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.shift = 10, \
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.width = 8, \
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.clkr = { \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_div_clk", \
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.parent_names = lcc_##prefix##_parents, \
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.num_parents = 1, \
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.ops = &clk_regmap_div_ops, \
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}, \
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}, \
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}; \
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\
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static struct clk_branch prefix##_bit_div_clk = { \
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.halt_reg = hr, \
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.halt_bit = 0, \
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.halt_check = BRANCH_HALT_ENABLE, \
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.clkr = { \
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.enable_reg = _ns, \
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.enable_mask = BIT(19), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_bit_div_clk", \
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.parent_names = (const char *[]){ \
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#prefix "_div_clk" \
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}, \
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.num_parents = 1, \
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.ops = &clk_branch_ops, \
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.flags = CLK_SET_RATE_PARENT, \
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}, \
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}, \
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}; \
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\
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static struct clk_regmap_mux prefix##_bit_clk = { \
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.reg = _ns, \
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.shift = 18, \
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.width = 1, \
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.clkr = { \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_bit_clk", \
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.parent_names = (const char *[]){ \
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#prefix "_bit_div_clk", \
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#prefix "_codec_clk", \
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}, \
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.num_parents = 2, \
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.ops = &clk_regmap_mux_closest_ops, \
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.flags = CLK_SET_RATE_PARENT, \
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}, \
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}, \
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}
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CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
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CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
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CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
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CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
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static struct freq_tbl clk_tbl_pcm_492[] = {
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{ 256000, P_PLL4, 4, 1, 480 },
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{ 512000, P_PLL4, 4, 1, 240 },
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{ 768000, P_PLL4, 4, 1, 160 },
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{ 1024000, P_PLL4, 4, 1, 120 },
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{ 1536000, P_PLL4, 4, 1, 80 },
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{ 2048000, P_PLL4, 4, 1, 60 },
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{ 3072000, P_PLL4, 4, 1, 40 },
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{ 4096000, P_PLL4, 4, 1, 30 },
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{ 6144000, P_PLL4, 4, 1, 20 },
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{ 8192000, P_PLL4, 4, 1, 15 },
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{ 12288000, P_PLL4, 4, 1, 10 },
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{ 24576000, P_PLL4, 4, 1, 5 },
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{ 27000000, P_PXO, 1, 0, 0 },
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{ }
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};
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static struct freq_tbl clk_tbl_pcm_393[] = {
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{ 256000, P_PLL4, 4, 1, 384 },
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{ 512000, P_PLL4, 4, 1, 192 },
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{ 768000, P_PLL4, 4, 1, 128 },
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{ 1024000, P_PLL4, 4, 1, 96 },
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{ 1536000, P_PLL4, 4, 1, 64 },
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{ 2048000, P_PLL4, 4, 1, 48 },
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{ 3072000, P_PLL4, 4, 1, 32 },
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{ 4096000, P_PLL4, 4, 1, 24 },
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{ 6144000, P_PLL4, 4, 1, 16 },
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{ 8192000, P_PLL4, 4, 1, 12 },
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{ 12288000, P_PLL4, 4, 1, 8 },
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{ 24576000, P_PLL4, 4, 1, 4 },
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{ 27000000, P_PXO, 1, 0, 0 },
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{ }
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};
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static struct clk_rcg pcm_src = {
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.ns_reg = 0x54,
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.md_reg = 0x58,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 16,
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.m_val_shift = 16,
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.width = 16,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_pxo_pll4_map,
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},
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.freq_tbl = clk_tbl_pcm_393,
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.clkr = {
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.enable_reg = 0x54,
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_src",
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.parent_names = lcc_pxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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static struct clk_branch pcm_clk_out = {
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.halt_reg = 0x5c,
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.halt_bit = 0,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x54,
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk_out",
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.parent_names = (const char *[]){ "pcm_src" },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_mux pcm_clk = {
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.reg = 0x54,
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.shift = 10,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk",
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.parent_names = (const char *[]){
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"pcm_clk_out",
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"pcm_codec_clk",
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},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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||||
},
|
||||
};
|
||||
|
||||
static struct clk_rcg slimbus_src = {
|
||||
.ns_reg = 0xcc,
|
||||
.md_reg = 0xd0,
|
||||
.mn = {
|
||||
.mnctr_en_bit = 8,
|
||||
.mnctr_reset_bit = 7,
|
||||
.mnctr_mode_shift = 5,
|
||||
.n_val_shift = 16,
|
||||
.m_val_shift = 16,
|
||||
.width = 8,
|
||||
},
|
||||
.p = {
|
||||
.pre_div_shift = 3,
|
||||
.pre_div_width = 2,
|
||||
},
|
||||
.s = {
|
||||
.src_sel_shift = 0,
|
||||
.parent_map = lcc_pxo_pll4_map,
|
||||
},
|
||||
.freq_tbl = clk_tbl_aif_osr_393,
|
||||
.clkr = {
|
||||
.enable_reg = 0xcc,
|
||||
.enable_mask = BIT(9),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "slimbus_src",
|
||||
.parent_names = lcc_pxo_pll4,
|
||||
.num_parents = 2,
|
||||
.ops = &clk_rcg_ops,
|
||||
.flags = CLK_SET_RATE_GATE,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const char *lcc_slimbus_parents[] = {
|
||||
"slimbus_src",
|
||||
};
|
||||
|
||||
static struct clk_branch audio_slimbus_clk = {
|
||||
.halt_reg = 0xd4,
|
||||
.halt_bit = 0,
|
||||
.halt_check = BRANCH_HALT_ENABLE,
|
||||
.clkr = {
|
||||
.enable_reg = 0xcc,
|
||||
.enable_mask = BIT(10),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "audio_slimbus_clk",
|
||||
.parent_names = lcc_slimbus_parents,
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch_ops,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch sps_slimbus_clk = {
|
||||
.halt_reg = 0xd4,
|
||||
.halt_bit = 1,
|
||||
.halt_check = BRANCH_HALT_ENABLE,
|
||||
.clkr = {
|
||||
.enable_reg = 0xcc,
|
||||
.enable_mask = BIT(12),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sps_slimbus_clk",
|
||||
.parent_names = lcc_slimbus_parents,
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch_ops,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap *lcc_msm8960_clks[] = {
|
||||
[PLL4] = &pll4.clkr,
|
||||
[MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
|
||||
[MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
|
||||
[MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
|
||||
[MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
|
||||
[MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
|
||||
[PCM_SRC] = &pcm_src.clkr,
|
||||
[PCM_CLK_OUT] = &pcm_clk_out.clkr,
|
||||
[PCM_CLK] = &pcm_clk.clkr,
|
||||
[SLIMBUS_SRC] = &slimbus_src.clkr,
|
||||
[AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
|
||||
[SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
|
||||
[CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
|
||||
[CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
|
||||
[CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
|
||||
[CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
|
||||
[CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
|
||||
[SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
|
||||
[SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
|
||||
[SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
|
||||
[SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
|
||||
[SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
|
||||
[CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
|
||||
[CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
|
||||
[CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
|
||||
[CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
|
||||
[CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
|
||||
[SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
|
||||
[SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
|
||||
[SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
|
||||
[SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
|
||||
[SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct regmap_config lcc_msm8960_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0xfc,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc lcc_msm8960_desc = {
|
||||
.config = &lcc_msm8960_regmap_config,
|
||||
.clks = lcc_msm8960_clks,
|
||||
.num_clks = ARRAY_SIZE(lcc_msm8960_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id lcc_msm8960_match_table[] = {
|
||||
{ .compatible = "qcom,lcc-msm8960" },
|
||||
{ .compatible = "qcom,lcc-apq8064" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
|
||||
|
||||
static int lcc_msm8960_probe(struct platform_device *pdev)
|
||||
{
|
||||
u32 val;
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
/* Use the correct frequency plan depending on speed of PLL4 */
|
||||
val = regmap_read(regmap, 0x4, &val);
|
||||
if (val == 0x12) {
|
||||
slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
|
||||
mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
||||
codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
||||
spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
||||
codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
||||
spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
||||
pcm_src.freq_tbl = clk_tbl_pcm_492;
|
||||
}
|
||||
/* Enable PLL4 source on the LPASS Primary PLL Mux */
|
||||
regmap_write(regmap, 0xc4, 0x1);
|
||||
|
||||
return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
|
||||
}
|
||||
|
||||
static int lcc_msm8960_remove(struct platform_device *pdev)
|
||||
{
|
||||
qcom_cc_remove(pdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver lcc_msm8960_driver = {
|
||||
.probe = lcc_msm8960_probe,
|
||||
.remove = lcc_msm8960_remove,
|
||||
.driver = {
|
||||
.name = "lcc-msm8960",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = lcc_msm8960_match_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(lcc_msm8960_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QCOM LCC MSM8960 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:lcc-msm8960");
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
|
||||
#define _DT_BINDINGS_CLK_LCC_MSM8960_H
|
||||
|
||||
#define PLL4 0
|
||||
#define MI2S_OSR_SRC 1
|
||||
#define MI2S_OSR_CLK 2
|
||||
#define MI2S_DIV_CLK 3
|
||||
#define MI2S_BIT_DIV_CLK 4
|
||||
#define MI2S_BIT_CLK 5
|
||||
#define PCM_SRC 6
|
||||
#define PCM_CLK_OUT 7
|
||||
#define PCM_CLK 8
|
||||
#define SLIMBUS_SRC 9
|
||||
#define AUDIO_SLIMBUS_CLK 10
|
||||
#define SPS_SLIMBUS_CLK 11
|
||||
#define CODEC_I2S_MIC_OSR_SRC 12
|
||||
#define CODEC_I2S_MIC_OSR_CLK 13
|
||||
#define CODEC_I2S_MIC_DIV_CLK 14
|
||||
#define CODEC_I2S_MIC_BIT_DIV_CLK 15
|
||||
#define CODEC_I2S_MIC_BIT_CLK 16
|
||||
#define SPARE_I2S_MIC_OSR_SRC 17
|
||||
#define SPARE_I2S_MIC_OSR_CLK 18
|
||||
#define SPARE_I2S_MIC_DIV_CLK 19
|
||||
#define SPARE_I2S_MIC_BIT_DIV_CLK 20
|
||||
#define SPARE_I2S_MIC_BIT_CLK 21
|
||||
#define CODEC_I2S_SPKR_OSR_SRC 22
|
||||
#define CODEC_I2S_SPKR_OSR_CLK 23
|
||||
#define CODEC_I2S_SPKR_DIV_CLK 24
|
||||
#define CODEC_I2S_SPKR_BIT_DIV_CLK 25
|
||||
#define CODEC_I2S_SPKR_BIT_CLK 26
|
||||
#define SPARE_I2S_SPKR_OSR_SRC 27
|
||||
#define SPARE_I2S_SPKR_OSR_CLK 28
|
||||
#define SPARE_I2S_SPKR_DIV_CLK 29
|
||||
#define SPARE_I2S_SPKR_BIT_DIV_CLK 30
|
||||
#define SPARE_I2S_SPKR_BIT_CLK 31
|
||||
|
||||
#endif
|
||||
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