cpuidle: Invert CPUIDLE_FLAG_TIME_VALID logic
The only place where the time is invalid is when the ACPI_CSTATE_FFH entry method is not set. Otherwise for all the drivers, the time can be correctly measured. Instead of duplicating the CPUIDLE_FLAG_TIME_VALID flag in all the drivers for all the states, just invert the logic by replacing it by the flag CPUIDLE_FLAG_TIME_INVALID, hence we can set this flag only for the acpi idle driver, remove the former flag from all the drivers and invert the logic with this flag in the different governor. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Родитель
206c5f60a3
Коммит
b82b6cca48
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@ -15,7 +15,6 @@ static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
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.exit_latency = 1,\
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.target_residency = 1,\
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.power_usage = p,\
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.flags = CPUIDLE_FLAG_TIME_VALID,\
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.name = "WFI",\
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.desc = "ARM WFI",\
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}
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@ -66,7 +66,6 @@ static struct cpuidle_driver davinci_idle_driver = {
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.enter = davinci_enter_idle,
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.exit_latency = 10,
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.target_residency = 10000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "DDR SR",
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.desc = "WFI and DDR Self Refresh",
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},
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@ -24,7 +24,6 @@ static struct cpuidle_driver imx5_cpuidle_driver = {
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.enter = imx5_cpuidle_enter,
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.exit_latency = 2,
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.target_residency = 1,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "IMX5 SRPG",
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.desc = "CPU state retained,powered off",
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},
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@ -53,8 +53,7 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
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{
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.exit_latency = 50,
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.target_residency = 75,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_TIMER_STOP,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.enter = imx6q_enter_wait,
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.name = "WAIT",
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.desc = "Clock off",
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@ -40,8 +40,7 @@ static struct cpuidle_driver imx6sl_cpuidle_driver = {
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{
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.exit_latency = 50,
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.target_residency = 75,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_TIMER_STOP,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.enter = imx6sl_enter_wait,
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.name = "WAIT",
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.desc = "Clock off",
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@ -265,7 +265,6 @@ static struct cpuidle_driver omap3_idle_driver = {
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.enter = omap3_enter_idle_bm,
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.exit_latency = 2 + 2,
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.target_residency = 5,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C1",
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.desc = "MPU ON + CORE ON",
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},
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@ -273,7 +272,6 @@ static struct cpuidle_driver omap3_idle_driver = {
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.enter = omap3_enter_idle_bm,
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.exit_latency = 10 + 10,
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.target_residency = 30,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C2",
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.desc = "MPU ON + CORE ON",
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},
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@ -281,7 +279,6 @@ static struct cpuidle_driver omap3_idle_driver = {
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.enter = omap3_enter_idle_bm,
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.exit_latency = 50 + 50,
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.target_residency = 300,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C3",
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.desc = "MPU RET + CORE ON",
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},
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@ -289,7 +286,6 @@ static struct cpuidle_driver omap3_idle_driver = {
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.enter = omap3_enter_idle_bm,
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.exit_latency = 1500 + 1800,
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.target_residency = 4000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C4",
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.desc = "MPU OFF + CORE ON",
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},
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@ -297,7 +293,6 @@ static struct cpuidle_driver omap3_idle_driver = {
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.enter = omap3_enter_idle_bm,
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.exit_latency = 2500 + 7500,
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.target_residency = 12000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C5",
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.desc = "MPU RET + CORE RET",
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},
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@ -305,7 +300,6 @@ static struct cpuidle_driver omap3_idle_driver = {
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.enter = omap3_enter_idle_bm,
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.exit_latency = 3000 + 8500,
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.target_residency = 15000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C6",
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.desc = "MPU OFF + CORE RET",
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},
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@ -313,7 +307,6 @@ static struct cpuidle_driver omap3_idle_driver = {
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.enter = omap3_enter_idle_bm,
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.exit_latency = 10000 + 30000,
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.target_residency = 30000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C7",
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.desc = "MPU OFF + CORE OFF",
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},
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@ -196,7 +196,6 @@ static struct cpuidle_driver omap4_idle_driver = {
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/* C1 - CPU0 ON + CPU1 ON + MPU ON */
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.exit_latency = 2 + 2,
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.target_residency = 5,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = omap_enter_idle_simple,
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.name = "C1",
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.desc = "CPUx ON, MPUSS ON"
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@ -205,7 +204,7 @@ static struct cpuidle_driver omap4_idle_driver = {
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/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
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.exit_latency = 328 + 440,
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.target_residency = 960,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
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.flags = CPUIDLE_FLAG_COUPLED,
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.enter = omap_enter_idle_coupled,
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.name = "C2",
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.desc = "CPUx OFF, MPUSS CSWR",
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@ -214,7 +213,7 @@ static struct cpuidle_driver omap4_idle_driver = {
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/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
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.exit_latency = 460 + 518,
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.target_residency = 1100,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
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.flags = CPUIDLE_FLAG_COUPLED,
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.enter = omap_enter_idle_coupled,
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.name = "C3",
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.desc = "CPUx OFF, MPUSS OSWR",
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@ -48,7 +48,6 @@ static struct cpuidle_driver s3c64xx_cpuidle_driver = {
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.enter = s3c64xx_enter_idle,
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.exit_latency = 1,
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.target_residency = 1,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "IDLE",
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.desc = "System active, ARM gated",
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},
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@ -423,7 +423,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
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.desc = "Core Standby Mode",
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.exit_latency = 10,
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.target_residency = 20 + 10,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = sh7372_enter_core_standby,
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},
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.states[2] = {
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@ -431,7 +430,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
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.desc = "A3SM PLL ON",
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.exit_latency = 20,
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.target_residency = 30 + 20,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = sh7372_enter_a3sm_pll_on,
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},
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.states[3] = {
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@ -439,7 +437,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
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.desc = "A3SM PLL OFF",
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.exit_latency = 120,
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.target_residency = 30 + 120,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = sh7372_enter_a3sm_pll_off,
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},
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.states[4] = {
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@ -447,7 +444,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
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.desc = "A4S PLL OFF",
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.exit_latency = 240,
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.target_residency = 30 + 240,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = sh7372_enter_a4s,
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.disabled = true,
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},
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@ -75,7 +75,6 @@ static struct cpuidle_driver tegra_idle_driver = {
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.exit_latency = 500,
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.target_residency = 1000,
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.power_usage = 0,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "powered-down",
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.desc = "CPU power gated",
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},
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@ -59,8 +59,7 @@ static struct cpuidle_driver tegra_idle_driver = {
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.exit_latency = 5000,
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.target_residency = 10000,
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.power_usage = 0,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_COUPLED,
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.flags = CPUIDLE_FLAG_COUPLED,
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.name = "powered-down",
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.desc = "CPU power gated",
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},
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@ -56,7 +56,6 @@ static struct cpuidle_driver tegra_idle_driver = {
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.exit_latency = 2000,
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.target_residency = 2200,
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.power_usage = 0,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "powered-down",
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.desc = "CPU power gated",
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},
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@ -22,7 +22,6 @@ extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
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.exit_latency = 1,\
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.target_residency = 1,\
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.power_usage = UINT_MAX,\
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.flags = CPUIDLE_FLAG_TIME_VALID,\
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.name = "wait",\
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.desc = "MIPS wait",\
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}
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@ -59,7 +59,6 @@ static struct cpuidle_driver cpuidle_driver = {
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.exit_latency = 1,
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.target_residency = 1 * 2,
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.power_usage = 3,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = cpuidle_sleep_enter,
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.name = "C1",
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.desc = "SuperH Sleep Mode",
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@ -68,7 +67,6 @@ static struct cpuidle_driver cpuidle_driver = {
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.exit_latency = 100,
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.target_residency = 1 * 2,
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.power_usage = 1,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = cpuidle_sleep_enter,
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.name = "C2",
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.desc = "SuperH Sleep Mode [SF]",
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@ -78,7 +76,6 @@ static struct cpuidle_driver cpuidle_driver = {
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.exit_latency = 2300,
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.target_residency = 1 * 2,
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.power_usage = 1,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.enter = cpuidle_sleep_enter,
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.name = "C3",
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.desc = "SuperH Mobile Standby Mode [SF]",
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@ -378,7 +378,6 @@ static struct cpuidle_driver apm_idle_driver = {
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{ /* entry 1 is for APM idle */
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.name = "APM",
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.desc = "APM idle",
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 250, /* WAG */
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.target_residency = 500, /* WAG */
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.enter = &apm_cpu_idle
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@ -985,8 +985,8 @@ static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr)
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state->flags = 0;
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switch (cx->type) {
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case ACPI_STATE_C1:
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if (cx->entry_method == ACPI_CSTATE_FFH)
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state->flags |= CPUIDLE_FLAG_TIME_VALID;
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if (cx->entry_method != ACPI_CSTATE_FFH)
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state->flags |= CPUIDLE_FLAG_TIME_INVALID;
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state->enter = acpi_idle_enter_c1;
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state->enter_dead = acpi_idle_play_dead;
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@ -994,14 +994,12 @@ static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr)
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break;
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case ACPI_STATE_C2:
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state->flags |= CPUIDLE_FLAG_TIME_VALID;
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state->enter = acpi_idle_enter_simple;
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state->enter_dead = acpi_idle_play_dead;
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drv->safe_state_index = count;
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break;
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case ACPI_STATE_C3:
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state->flags |= CPUIDLE_FLAG_TIME_VALID;
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state->enter = pr->flags.bm_check ?
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acpi_idle_enter_bm :
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acpi_idle_enter_simple;
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@ -73,7 +73,6 @@ static struct cpuidle_driver arm64_idle_driver = {
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.exit_latency = 1,
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.target_residency = 1,
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.power_usage = UINT_MAX,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "WFI",
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.desc = "ARM64 WFI",
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}
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@ -43,7 +43,6 @@ static struct cpuidle_driver at91_idle_driver = {
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.enter = at91_enter_idle,
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.exit_latency = 10,
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.target_residency = 10000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "RAM_SR",
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.desc = "WFI and DDR Self Refresh",
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},
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@ -67,8 +67,7 @@ static struct cpuidle_driver bl_idle_little_driver = {
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.enter = bl_enter_powerdown,
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.exit_latency = 700,
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.target_residency = 2500,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_TIMER_STOP,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.name = "C1",
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.desc = "ARM little-cluster power down",
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},
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@ -89,8 +88,7 @@ static struct cpuidle_driver bl_idle_big_driver = {
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.enter = bl_enter_powerdown,
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.exit_latency = 500,
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.target_residency = 2000,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_TIMER_STOP,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.name = "C1",
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.desc = "ARM big-cluster power down",
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},
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@ -55,7 +55,6 @@ static struct cpuidle_driver calxeda_idle_driver = {
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{
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.name = "PG",
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.desc = "Power Gate",
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 30,
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.power_usage = 50,
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.target_residency = 200,
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@ -79,7 +79,6 @@ static struct cpuidle_driver cps_driver = {
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.enter = cps_nc_enter,
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.exit_latency = 200,
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.target_residency = 450,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "nc-wait",
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.desc = "non-coherent MIPS wait",
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},
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@ -87,8 +86,7 @@ static struct cpuidle_driver cps_driver = {
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.enter = cps_nc_enter,
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.exit_latency = 300,
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.target_residency = 700,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_TIMER_STOP,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.name = "clock-gated",
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.desc = "core clock gated",
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},
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@ -96,8 +94,7 @@ static struct cpuidle_driver cps_driver = {
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.enter = cps_nc_enter,
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.exit_latency = 600,
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.target_residency = 1000,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_TIMER_STOP,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.name = "power-gated",
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.desc = "core power gated",
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},
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@ -47,7 +47,6 @@ static struct cpuidle_driver exynos_idle_driver = {
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.enter = exynos_enter_lowpower,
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.exit_latency = 300,
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.target_residency = 100000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C1",
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.desc = "ARM power down",
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},
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@ -47,7 +47,6 @@ static struct cpuidle_driver kirkwood_idle_driver = {
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.enter = kirkwood_enter_idle,
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.exit_latency = 10,
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.target_residency = 100000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "DDR SR",
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.desc = "WFI and DDR Self Refresh",
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},
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@ -53,7 +53,6 @@ static struct cpuidle_driver armadaxp_idle_driver = {
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.exit_latency = 10,
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.power_usage = 50,
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.target_residency = 100,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "MV CPU IDLE",
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.desc = "CPU power down",
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},
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@ -62,8 +61,7 @@ static struct cpuidle_driver armadaxp_idle_driver = {
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.exit_latency = 100,
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.power_usage = 5,
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.target_residency = 1000,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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MVEBU_V7_FLAG_DEEP_IDLE,
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.flags = MVEBU_V7_FLAG_DEEP_IDLE,
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.name = "MV CPU DEEP IDLE",
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.desc = "CPU and L2 Fabric power down",
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},
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@ -78,8 +76,7 @@ static struct cpuidle_driver armada370_idle_driver = {
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.exit_latency = 100,
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.power_usage = 5,
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.target_residency = 1000,
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.flags = (CPUIDLE_FLAG_TIME_VALID |
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MVEBU_V7_FLAG_DEEP_IDLE),
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.flags = MVEBU_V7_FLAG_DEEP_IDLE,
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.name = "Deep Idle",
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.desc = "CPU and L2 Fabric power down",
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},
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@ -94,7 +91,6 @@ static struct cpuidle_driver armada38x_idle_driver = {
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.exit_latency = 10,
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.power_usage = 5,
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.target_residency = 100,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.name = "Idle",
|
||||
.desc = "CPU and SCU power down",
|
||||
},
|
||||
|
|
|
@ -93,7 +93,6 @@ static struct cpuidle_state powernv_states[MAX_POWERNV_IDLE_STATES] = {
|
|||
{ /* Snooze */
|
||||
.name = "snooze",
|
||||
.desc = "snooze",
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.exit_latency = 0,
|
||||
.target_residency = 0,
|
||||
.enter = &snooze_loop },
|
||||
|
@ -202,7 +201,7 @@ static int powernv_add_idle_states(void)
|
|||
/* Add NAP state */
|
||||
strcpy(powernv_states[nr_idle_states].name, "Nap");
|
||||
strcpy(powernv_states[nr_idle_states].desc, "Nap");
|
||||
powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIME_VALID;
|
||||
powernv_states[nr_idle_states].flags = 0;
|
||||
powernv_states[nr_idle_states].exit_latency =
|
||||
((unsigned int)latency_ns) / 1000;
|
||||
powernv_states[nr_idle_states].target_residency =
|
||||
|
@ -215,8 +214,7 @@ static int powernv_add_idle_states(void)
|
|||
/* Add FASTSLEEP state */
|
||||
strcpy(powernv_states[nr_idle_states].name, "FastSleep");
|
||||
strcpy(powernv_states[nr_idle_states].desc, "FastSleep");
|
||||
powernv_states[nr_idle_states].flags =
|
||||
CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TIMER_STOP;
|
||||
powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIMER_STOP;
|
||||
powernv_states[nr_idle_states].exit_latency =
|
||||
((unsigned int)latency_ns) / 1000;
|
||||
powernv_states[nr_idle_states].target_residency =
|
||||
|
|
|
@ -142,14 +142,12 @@ static struct cpuidle_state dedicated_states[] = {
|
|||
{ /* Snooze */
|
||||
.name = "snooze",
|
||||
.desc = "snooze",
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.exit_latency = 0,
|
||||
.target_residency = 0,
|
||||
.enter = &snooze_loop },
|
||||
{ /* CEDE */
|
||||
.name = "CEDE",
|
||||
.desc = "CEDE",
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.exit_latency = 10,
|
||||
.target_residency = 100,
|
||||
.enter = &dedicated_cede_loop },
|
||||
|
@ -162,7 +160,6 @@ static struct cpuidle_state shared_states[] = {
|
|||
{ /* Shared Cede */
|
||||
.name = "Shared Cede",
|
||||
.desc = "Shared Cede",
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.exit_latency = 0,
|
||||
.target_residency = 0,
|
||||
.enter = &shared_cede_loop },
|
||||
|
|
|
@ -101,8 +101,7 @@ static struct cpuidle_driver ux500_idle_driver = {
|
|||
.enter = ux500_enter_idle,
|
||||
.exit_latency = 70,
|
||||
.target_residency = 260,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID |
|
||||
CPUIDLE_FLAG_TIMER_STOP,
|
||||
.flags = CPUIDLE_FLAG_TIMER_STOP,
|
||||
.name = "ApIdle",
|
||||
.desc = "ARM Retention",
|
||||
},
|
||||
|
|
|
@ -52,7 +52,6 @@ static struct cpuidle_driver zynq_idle_driver = {
|
|||
.enter = zynq_enter_idle,
|
||||
.exit_latency = 10,
|
||||
.target_residency = 10000,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.name = "RAM_SR",
|
||||
.desc = "WFI and RAM Self Refresh",
|
||||
},
|
||||
|
|
|
@ -201,7 +201,6 @@ static void poll_idle_init(struct cpuidle_driver *drv)
|
|||
state->exit_latency = 0;
|
||||
state->target_residency = 0;
|
||||
state->power_usage = -1;
|
||||
state->flags = CPUIDLE_FLAG_TIME_VALID;
|
||||
state->enter = poll_idle;
|
||||
state->disabled = false;
|
||||
}
|
||||
|
|
|
@ -73,7 +73,7 @@ static int init_state_node(struct cpuidle_state *idle_state,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
idle_state->flags = CPUIDLE_FLAG_TIME_VALID;
|
||||
idle_state->flags = 0;
|
||||
if (of_property_read_bool(state_node, "local-timer-stop"))
|
||||
idle_state->flags |= CPUIDLE_FLAG_TIMER_STOP;
|
||||
/*
|
||||
|
|
|
@ -79,7 +79,7 @@ static int ladder_select_state(struct cpuidle_driver *drv,
|
|||
|
||||
last_state = &ldev->states[last_idx];
|
||||
|
||||
if (drv->states[last_idx].flags & CPUIDLE_FLAG_TIME_VALID) {
|
||||
if (!(drv->states[last_idx].flags & CPUIDLE_FLAG_TIME_INVALID)) {
|
||||
last_residency = cpuidle_get_last_residency(dev) - \
|
||||
drv->states[last_idx].exit_latency;
|
||||
}
|
||||
|
|
|
@ -405,7 +405,7 @@ static void menu_update(struct cpuidle_driver *drv, struct cpuidle_device *dev)
|
|||
* the measured amount of time is less than the exit latency,
|
||||
* assume the state was never reached and the exit latency is 0.
|
||||
*/
|
||||
if (unlikely(!(target->flags & CPUIDLE_FLAG_TIME_VALID))) {
|
||||
if (unlikely(target->flags & CPUIDLE_FLAG_TIME_INVALID)) {
|
||||
/* Use timer value as is */
|
||||
measured_us = data->next_timer_us;
|
||||
|
||||
|
|
|
@ -128,28 +128,28 @@ static struct cpuidle_state nehalem_cstates[] = {
|
|||
{
|
||||
.name = "C1-NHM",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 3,
|
||||
.target_residency = 6,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-NHM",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 20,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C3-NHM",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 20,
|
||||
.target_residency = 80,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-NHM",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 200,
|
||||
.target_residency = 800,
|
||||
.enter = &intel_idle },
|
||||
|
@ -161,35 +161,35 @@ static struct cpuidle_state snb_cstates[] = {
|
|||
{
|
||||
.name = "C1-SNB",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 2,
|
||||
.target_residency = 2,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-SNB",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 20,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C3-SNB",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 80,
|
||||
.target_residency = 211,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-SNB",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 104,
|
||||
.target_residency = 345,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C7-SNB",
|
||||
.desc = "MWAIT 0x30",
|
||||
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 109,
|
||||
.target_residency = 345,
|
||||
.enter = &intel_idle },
|
||||
|
@ -201,42 +201,42 @@ static struct cpuidle_state byt_cstates[] = {
|
|||
{
|
||||
.name = "C1-BYT",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 1,
|
||||
.target_residency = 1,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-BYT",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 15,
|
||||
.target_residency = 30,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6N-BYT",
|
||||
.desc = "MWAIT 0x58",
|
||||
.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 40,
|
||||
.target_residency = 275,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6S-BYT",
|
||||
.desc = "MWAIT 0x52",
|
||||
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 140,
|
||||
.target_residency = 560,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C7-BYT",
|
||||
.desc = "MWAIT 0x60",
|
||||
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 1200,
|
||||
.target_residency = 1500,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C7S-BYT",
|
||||
.desc = "MWAIT 0x64",
|
||||
.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 10000,
|
||||
.target_residency = 20000,
|
||||
.enter = &intel_idle },
|
||||
|
@ -248,35 +248,35 @@ static struct cpuidle_state ivb_cstates[] = {
|
|||
{
|
||||
.name = "C1-IVB",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 1,
|
||||
.target_residency = 1,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-IVB",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 20,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C3-IVB",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 59,
|
||||
.target_residency = 156,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-IVB",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 80,
|
||||
.target_residency = 300,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C7-IVB",
|
||||
.desc = "MWAIT 0x30",
|
||||
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 87,
|
||||
.target_residency = 300,
|
||||
.enter = &intel_idle },
|
||||
|
@ -288,28 +288,28 @@ static struct cpuidle_state ivt_cstates[] = {
|
|||
{
|
||||
.name = "C1-IVT",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 1,
|
||||
.target_residency = 1,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-IVT",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 80,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C3-IVT",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 59,
|
||||
.target_residency = 156,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-IVT",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 82,
|
||||
.target_residency = 300,
|
||||
.enter = &intel_idle },
|
||||
|
@ -321,28 +321,28 @@ static struct cpuidle_state ivt_cstates_4s[] = {
|
|||
{
|
||||
.name = "C1-IVT-4S",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 1,
|
||||
.target_residency = 1,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-IVT-4S",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 250,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C3-IVT-4S",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 59,
|
||||
.target_residency = 300,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-IVT-4S",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 84,
|
||||
.target_residency = 400,
|
||||
.enter = &intel_idle },
|
||||
|
@ -354,28 +354,28 @@ static struct cpuidle_state ivt_cstates_8s[] = {
|
|||
{
|
||||
.name = "C1-IVT-8S",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 1,
|
||||
.target_residency = 1,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-IVT-8S",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 500,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C3-IVT-8S",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 59,
|
||||
.target_residency = 600,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-IVT-8S",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 88,
|
||||
.target_residency = 700,
|
||||
.enter = &intel_idle },
|
||||
|
@ -387,56 +387,56 @@ static struct cpuidle_state hsw_cstates[] = {
|
|||
{
|
||||
.name = "C1-HSW",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 2,
|
||||
.target_residency = 2,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-HSW",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 20,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C3-HSW",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 33,
|
||||
.target_residency = 100,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-HSW",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 133,
|
||||
.target_residency = 400,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C7s-HSW",
|
||||
.desc = "MWAIT 0x32",
|
||||
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 166,
|
||||
.target_residency = 500,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C8-HSW",
|
||||
.desc = "MWAIT 0x40",
|
||||
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 300,
|
||||
.target_residency = 900,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C9-HSW",
|
||||
.desc = "MWAIT 0x50",
|
||||
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 600,
|
||||
.target_residency = 1800,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C10-HSW",
|
||||
.desc = "MWAIT 0x60",
|
||||
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 2600,
|
||||
.target_residency = 7700,
|
||||
.enter = &intel_idle },
|
||||
|
@ -447,56 +447,56 @@ static struct cpuidle_state bdw_cstates[] = {
|
|||
{
|
||||
.name = "C1-BDW",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 2,
|
||||
.target_residency = 2,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C1E-BDW",
|
||||
.desc = "MWAIT 0x01",
|
||||
.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x01),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 20,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C3-BDW",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 40,
|
||||
.target_residency = 100,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-BDW",
|
||||
.desc = "MWAIT 0x20",
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 133,
|
||||
.target_residency = 400,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C7s-BDW",
|
||||
.desc = "MWAIT 0x32",
|
||||
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 166,
|
||||
.target_residency = 500,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C8-BDW",
|
||||
.desc = "MWAIT 0x40",
|
||||
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 300,
|
||||
.target_residency = 900,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C9-BDW",
|
||||
.desc = "MWAIT 0x50",
|
||||
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 600,
|
||||
.target_residency = 1800,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C10-BDW",
|
||||
.desc = "MWAIT 0x60",
|
||||
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 2600,
|
||||
.target_residency = 7700,
|
||||
.enter = &intel_idle },
|
||||
|
@ -508,28 +508,28 @@ static struct cpuidle_state atom_cstates[] = {
|
|||
{
|
||||
.name = "C1E-ATM",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 10,
|
||||
.target_residency = 20,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C2-ATM",
|
||||
.desc = "MWAIT 0x10",
|
||||
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x10),
|
||||
.exit_latency = 20,
|
||||
.target_residency = 80,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C4-ATM",
|
||||
.desc = "MWAIT 0x30",
|
||||
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 100,
|
||||
.target_residency = 400,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-ATM",
|
||||
.desc = "MWAIT 0x52",
|
||||
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 140,
|
||||
.target_residency = 560,
|
||||
.enter = &intel_idle },
|
||||
|
@ -540,14 +540,14 @@ static struct cpuidle_state avn_cstates[] = {
|
|||
{
|
||||
.name = "C1-AVN",
|
||||
.desc = "MWAIT 0x00",
|
||||
.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
|
||||
.flags = MWAIT2flg(0x00),
|
||||
.exit_latency = 2,
|
||||
.target_residency = 2,
|
||||
.enter = &intel_idle },
|
||||
{
|
||||
.name = "C6-AVN",
|
||||
.desc = "MWAIT 0x51",
|
||||
.flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 15,
|
||||
.target_residency = 45,
|
||||
.enter = &intel_idle },
|
||||
|
|
|
@ -53,7 +53,7 @@ struct cpuidle_state {
|
|||
};
|
||||
|
||||
/* Idle State Flags */
|
||||
#define CPUIDLE_FLAG_TIME_VALID (0x01) /* is residency time measurable? */
|
||||
#define CPUIDLE_FLAG_TIME_INVALID (0x01) /* is residency time measurable? */
|
||||
#define CPUIDLE_FLAG_COUPLED (0x02) /* state applies to multiple cpus */
|
||||
#define CPUIDLE_FLAG_TIMER_STOP (0x04) /* timer is stopped on this state */
|
||||
|
||||
|
@ -90,7 +90,7 @@ DECLARE_PER_CPU(struct cpuidle_device, cpuidle_dev);
|
|||
* cpuidle_get_last_residency - retrieves the last state's residency time
|
||||
* @dev: the target CPU
|
||||
*
|
||||
* NOTE: this value is invalid if CPUIDLE_FLAG_TIME_VALID isn't set
|
||||
* NOTE: this value is invalid if CPUIDLE_FLAG_TIME_INVALID is set
|
||||
*/
|
||||
static inline int cpuidle_get_last_residency(struct cpuidle_device *dev)
|
||||
{
|
||||
|
|
Загрузка…
Ссылка в новой задаче