dt-bindings: Changes for v5.17-rc1
This contains a bunch of json-schema conversions for various Tegra- related DT bindings and additions for new SoC and board support. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmG8sRoTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoUpLD/9aTWMH3DhMh2uKpOOt8TOdNiZXLqec GLXFoA3jHNHxEcwOXU6or8Hg4ipZnYgN2tspu2qpI+OvgwsoZcJqu8WAfH+fS2vv 950OmjAdKBTQhiOO1eSo86Kq00orE6TdMQ3NfTUqEKKcjbiAruy+ojuDfFRoutP+ UCe7Vl8CMi++MFmvyKBLu2GoDKb2JoKtoabiCxNwchZH3acgWFMfxeLBWNBj6HqH W7h+uld9MTg1rEZ7P7ZGspiXh9Nzt8e3e2un7j24L0qDI+s8Ur4XOf+Fms4aAMXc Pbme+q4DaA4xcFXVd5kyAKK1f6kYNVNZBHjKMVuPR4zjK4vADAZ2SZ0hFc3pE7hB rZtjwp4TphuwGrwNoXE4koi04GZStwnvp/Wr4BlCSyycY2H1UxMHHgMDWLA4WVVw JM+9uvjvCe0oE7x6+l4usWMVJrQljWH3IU5w4SXyzowYu5cvbWFhqRieFcg8iDbF CnGJGorq6bKJExiIyWtiRR4+m1TGsBq2cNUb1A0qgUTrMq6O2R4AiqSe45wDYSlQ z1zON1LILctiQfyCM2vsDLOe4AEyitzQkRPS9zo7Jn6dPnf9k3knpTDdyDS7vU2A juR3JOTdHuZ6jNBu5ykJbr3EN54D9nXHEGEl5ToHkahXEpJIC5haQOkRYU+OxER0 C+gWIEJcroJkjA== =aSMg -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAlSQACgkQmmx57+YA GNkY/g//Wc6o+0wNZ8DBGSvI/3spHcNdSeIFwprmMJyBd1ho30kDL+jBW+5bYekT 5X7GC7E/GkbxfvePQkZtS5+qFFdOV5qtQdjLEf2bQc/RuErnwnLttLBTFQpuBNHh VFjB+KHkEGtGFjjJ6CCnz57M5m+4NBWpIBwtubEygWhopCAb6as/dvi3F6Gso4lq xUhRe7Gx7LiJeqJhQqhGTgLo50oBQOHbXsIKEMuwXDMuhsQnpWVq3srJPr6pfgZi Q4cgE7GTKCe2TE7wDk9wKB5ptK6hntXswN51tFEGZk/5PNjot+64LzIRQ47CjpGm nisGWyT86ksaVZnXZlRvynbedWasrXITL76ccadbF4vqZGe9G07kw5N+i/t05DeN TkvXSBe+4e6q6zAOzrUUCP59R7X+sgC8phYj8al8We7i+Prn5IX+a4Glm4wiOMVv n9j9yRr/YPDrLVDjmqIhESzSmq5IZucbuqi7CW+TeaKrILlMaYcWuxXdAd8H9Ite krT4RxSkM+DJCW0OGIpYH9EtynHpf1HGhlP05wmrSa+quWa8h7WBCS2D9lFk4RU3 1cqV1qHLqL+HctxP0LGS2ajT1sUwkgoshijNlknmlwQW+Wzqu56J1H/+toLrH1XK 20ZALOao6CN344n2A//XVOk0udBShg93KmvTLhv2HQ4SIK5Jlwg= =acJz -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.17-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.17-rc1 This contains a bunch of json-schema conversions for various Tegra- related DT bindings and additions for new SoC and board support. * tag 'tegra-for-5.17-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits) media: dt: bindings: tegra-vde: Document OPP and power domain media: dt: bindings: tegra-vde: Convert to schema dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D dt-bindings: host1x: Document OPP and power domain properties dt-bindings: clock: tegra-car: Document new clock sub-nodes dt-bindings: ARM: tegra: Document Pegatron Chagall dt-bindings: ARM: tegra: Document ASUS Transformers dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties dt-bindings: serial: Document Tegra234 TCU dt-bindings: serial: tegra-tcu: Convert to json-schema dt-bindings: thermal: tegra186-bpmp: Convert to json-schema dt-bindings: firmware: tegra: Convert to json-schema dt-bindings: tegra: pmc: Convert to json-schema dt-bindings: serial: 8250: Document Tegra234 UART dt-bindings: mmc: tegra: Document Tegra234 SDHCI dt-bindings: fuse: tegra: Document Tegra234 FUSE dt-bindings: fuse: tegra: Convert to json-schema dt-bindings: rtc: tegra: Document Tegra234 RTC dt-bindings: rtc: tegra: Convert to json-schema dt-bindings: mailbox: tegra: Document Tegra234 HSP ... Link: https://lore.kernel.org/r/20211217162253.1801077-3-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
b87cd3759d
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|
@ -36,6 +36,9 @@ properties:
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|||
- toradex,colibri_t20-iris
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- const: toradex,colibri_t20
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- const: nvidia,tegra20
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- items:
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- const: asus,tf101
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- const: nvidia,tegra20
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- items:
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- const: acer,picasso
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- const: nvidia,tegra20
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@ -49,6 +52,18 @@ properties:
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- nvidia,cardhu-a04
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- const: nvidia,cardhu
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- const: nvidia,tegra30
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- items:
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- const: asus,tf201
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- const: nvidia,tegra30
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- items:
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- const: asus,tf300t
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- const: nvidia,tegra30
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- items:
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- const: asus,tf300tg
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- const: nvidia,tegra30
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- items:
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- const: asus,tf700t
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- const: nvidia,tegra30
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- items:
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- const: toradex,apalis_t30-eval
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- const: toradex,apalis_t30
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@ -74,8 +89,12 @@ properties:
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- items:
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- const: ouya,ouya
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- const: nvidia,tegra30
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- items:
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- const: pegatron,chagall
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- const: nvidia,tegra30
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- items:
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- enum:
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- asus,tf701t
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- nvidia,dalmore
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- nvidia,roth
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- nvidia,tn7
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@ -108,14 +127,17 @@ properties:
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- nvidia,p2571
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- nvidia,p2894-0050-a08
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- const: nvidia,tegra210
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- items:
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- enum:
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- nvidia,p2771-0000
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- nvidia,p3509-0000+p3636-0001
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- description: Jetson TX2 Developer Kit
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items:
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- const: nvidia,p2771-0000
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- const: nvidia,tegra186
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- items:
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- enum:
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- nvidia,p2972-0000
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- description: Jetson TX2 NX Developer Kit
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items:
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- const: nvidia,p3509-0000+p3636-0001
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- const: nvidia,tegra186
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- description: Jetson AGX Xavier Developer Kit
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items:
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- const: nvidia,p2972-0000
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- const: nvidia,tegra194
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- description: Jetson Xavier NX
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items:
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@ -134,8 +156,16 @@ properties:
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- const: nvidia,p3509-0000+p3668-0001
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- const: nvidia,tegra194
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- items:
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- enum:
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- nvidia,tegra234-vdk
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- const: nvidia,tegra234-vdk
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- const: nvidia,tegra234
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- description: Jetson AGX Orin
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items:
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- const: nvidia,p3701-0000
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- const: nvidia,tegra234
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- description: Jetson AGX Orin Developer Kit
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items:
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- const: nvidia,p3737-0000+p3701-0000
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- const: nvidia,p3701-0000
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- const: nvidia,tegra234
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additionalProperties: true
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@ -1,133 +0,0 @@
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NVIDIA Tegra Power Management Controller (PMC)
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Required properties:
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- compatible: Should contain one of the following:
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- "nvidia,tegra186-pmc": for Tegra186
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- "nvidia,tegra194-pmc": for Tegra194
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- "nvidia,tegra234-pmc": for Tegra234
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- reg: Must contain an (offset, length) pair of the register set for each
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entry in reg-names.
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- reg-names: Must include the following entries:
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- "pmc"
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- "wake"
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- "aotag"
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- "scratch"
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- "misc" (Only for Tegra194 and later)
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Optional properties:
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- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source. The value must be 2.
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Example:
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SoC DTSI:
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pmc@c3600000 {
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compatible = "nvidia,tegra186-pmc";
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reg = <0 0x0c360000 0 0x10000>,
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<0 0x0c370000 0 0x10000>,
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<0 0x0c380000 0 0x10000>,
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<0 0x0c390000 0 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch";
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};
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Board DTS:
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pmc@c360000 {
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nvidia,invert-interrupt;
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};
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== Pad Control ==
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On Tegra SoCs a pad is a set of pins which are configured as a group.
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The pin grouping is a fixed attribute of the hardware. The PMC can be
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used to set pad power state and signaling voltage. A pad can be either
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in active or power down mode. The support for power state and signaling
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voltage configuration varies depending on the pad in question. 3.3 V and
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1.8 V signaling voltages are supported on pins where software
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controllable signaling voltage switching is available.
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Pad configurations are described with pin configuration nodes which
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are placed under the pmc node and they are referred to by the pinctrl
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client properties. For more information see
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Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
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The following pads are present on Tegra186:
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csia csib dsi mipi-bias
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pex-clk-bias pex-clk3 pex-clk2 pex-clk1
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usb0 usb1 usb2 usb-bias
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uart audio hsic dbg
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hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
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sdmmc4 cam dsib dsic
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dsid csic csid csie
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dsif spi ufs dmic-hv
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edp sdmmc1-hv sdmmc3-hv conn
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audio-hv ao-hv
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Required pin configuration properties:
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- pins: A list of strings, each of which contains the name of a pad
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to be configured.
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Optional pin configuration properties:
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- low-power-enable: Configure the pad into power down mode
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- low-power-disable: Configure the pad into active mode
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- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
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TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
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The values are defined in
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include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
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Note: The power state can be configured on all of the above pads except
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for ao-hv. Following pads have software configurable signaling
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voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
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ao-hv.
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Pad configuration state example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra186-pmc";
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reg = <0 0x0c360000 0 0x10000>,
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<0 0x0c370000 0 0x10000>,
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<0 0x0c380000 0 0x10000>,
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<0 0x0c390000 0 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch";
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...
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sdmmc1_3v3: sdmmc1-3v3 {
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pins = "sdmmc1-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc1_1v8: sdmmc1-1v8 {
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pins = "sdmmc1-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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hdmi_off: hdmi-off {
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pins = "hdmi";
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low-power-enable;
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}
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hdmi_on: hdmi-on {
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pins = "hdmi";
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low-power-disable;
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}
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};
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Pinctrl client example:
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sdmmc1: sdhci@3400000 {
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...
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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};
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...
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sor0: sor@15540000 {
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...
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pinctrl-0 = <&hdmi_off>;
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pinctrl-1 = <&hdmi_on>;
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pinctrl-names = "hdmi-on", "hdmi-off";
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};
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@ -0,0 +1,198 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra Power Management Controller (PMC)
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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enum:
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- nvidia,tegra186-pmc
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- nvidia,tegra194-pmc
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- nvidia,tegra234-pmc
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reg:
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minItems: 4
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maxItems: 5
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reg-names:
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minItems: 4
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items:
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- const: pmc
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- const: wake
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- const: aotag
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- const: scratch
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- const: misc
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interrupt-controller: true
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"#interrupt-cells":
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description: Specifies the number of cells needed to encode an
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interrupt source. The value must be 2.
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const: 2
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nvidia,invert-interrupt:
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description: If present, inverts the PMU interrupt signal.
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$ref: /schemas/types.yaml#/definitions/flag
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if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra186-pmc
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then:
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properties:
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reg:
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maxItems: 4
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reg-names:
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maxItems: 4
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else:
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properties:
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reg:
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minItems: 5
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reg-names:
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minItems: 5
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patternProperties:
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"^[a-z0-9]+-[a-z0-9]+$":
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if:
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type: object
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then:
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description: |
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||||
These are pad configuration nodes. On Tegra SoCs a pad is a set of
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pins which are configured as a group. The pin grouping is a fixed
|
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attribute of the hardware. The PMC can be used to set pad power
|
||||
state and signaling voltage. A pad can be either in active or
|
||||
power down mode. The support for power state and signaling voltage
|
||||
configuration varies depending on the pad in question. 3.3 V and
|
||||
1.8 V signaling voltages are supported on pins where software
|
||||
controllable signaling voltage switching is available.
|
||||
|
||||
Pad configurations are described with pin configuration nodes
|
||||
which are placed under the pmc node and they are referred to by
|
||||
the pinctrl client properties. For more information see
|
||||
|
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Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
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The following pads are present on Tegra186:
|
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csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
|
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pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
|
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hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
|
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dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
|
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sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
|
||||
|
||||
The following pads are present on Tegra194:
|
||||
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csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
|
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pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
|
||||
pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
|
||||
soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
|
||||
hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
|
||||
pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
|
||||
spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
|
||||
audio-hv, ao-hv
|
||||
|
||||
properties:
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Must contain the name of the pad(s) to be
|
||||
configured.
|
||||
|
||||
low-power-enable:
|
||||
description: Configure the pad into power down mode.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
low-power-disable:
|
||||
description: Configure the pad into active mode.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
power-source:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
|
||||
voltages.
|
||||
|
||||
The values are defined in
|
||||
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
|
||||
|
||||
The power state can be configured on all of the above pads
|
||||
except for ao-hv. Following pads have software configurable
|
||||
signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
|
||||
audio-hv, ao-hv.
|
||||
|
||||
phandle: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
dependencies:
|
||||
interrupt-controller: ['#interrupt-cells']
|
||||
"#interrupt-cells":
|
||||
required:
|
||||
- interrupt-controller
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
pmc@c3600000 {
|
||||
compatible = "nvidia,tegra186-pmc";
|
||||
reg = <0x0c360000 0x10000>,
|
||||
<0x0c370000 0x10000>,
|
||||
<0x0c380000 0x10000>,
|
||||
<0x0c390000 0x10000>;
|
||||
reg-names = "pmc", "wake", "aotag", "scratch";
|
||||
nvidia,invert-interrupt;
|
||||
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1: mmc@3400000 {
|
||||
compatible = "nvidia,tegra186-sdhci";
|
||||
reg = <0x03400000 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
|
||||
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_SDMMC1>;
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
};
|
||||
|
|
@ -42,6 +42,36 @@ properties:
|
|||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^(sclk)|(pll-[cem])$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-sclk
|
||||
- nvidia,tegra30-sclk
|
||||
- nvidia,tegra30-pllc
|
||||
- nvidia,tegra30-plle
|
||||
- nvidia,tegra30-pllm
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: node's clock
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: phandle to the core SoC power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- operating-points-v2
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -59,6 +89,13 @@ examples:
|
|||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
sclk {
|
||||
compatible = "nvidia,tegra20-sclk";
|
||||
operating-points-v2 = <&opp_table>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_SCLK>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
};
|
||||
|
||||
usb-controller@c5004000 {
|
||||
|
|
|
|||
|
|
@ -19,6 +19,19 @@ Required properties:
|
|||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- host1x
|
||||
- mc
|
||||
|
||||
Optional properties:
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
For each opp entry in 'operating-points-v2' table of host1x and its modules:
|
||||
- opp-supported-hw: One bitfield indicating:
|
||||
On Tegra20: SoC process ID mask
|
||||
On Tegra30+: SoC speedo ID mask
|
||||
|
||||
A bitwise AND is performed against the value and if any bit
|
||||
matches, the OPP gets enabled.
|
||||
|
||||
Each host1x client module having to perform DMA through the Memory Controller
|
||||
should have the interconnect endpoints set to the Memory Client and External
|
||||
|
|
@ -45,6 +58,8 @@ of the following host1x client modules:
|
|||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to MPE power domain.
|
||||
|
||||
- vi: video input
|
||||
|
||||
|
|
@ -128,6 +143,8 @@ of the following host1x client modules:
|
|||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to VENC power domain.
|
||||
|
||||
- epp: encoder pre-processor
|
||||
|
||||
|
|
@ -147,6 +164,8 @@ of the following host1x client modules:
|
|||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
- isp: image signal processor
|
||||
|
||||
|
|
@ -166,6 +185,7 @@ of the following host1x client modules:
|
|||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- power-domains: Phandle to VENC or core power domain.
|
||||
|
||||
- gr2d: 2D graphics engine
|
||||
|
||||
|
|
@ -179,12 +199,15 @@ of the following host1x client modules:
|
|||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- 2d
|
||||
- mc
|
||||
|
||||
Optional properties:
|
||||
- interconnects: Must contain entry for the GR2D memory clients.
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
- gr3d: 3D graphics engine
|
||||
|
||||
|
|
@ -203,12 +226,16 @@ of the following host1x client modules:
|
|||
- reset-names: Must include the following entries:
|
||||
- 3d
|
||||
- 3d2 (Only required on SoCs with two 3D clocks)
|
||||
- mc
|
||||
- mc2 (Only required on SoCs with two 3D clocks)
|
||||
|
||||
Optional properties:
|
||||
- interconnects: Must contain entry for the GR3D memory clients.
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandles to 3D or core power domain.
|
||||
|
||||
- dc: display controller
|
||||
|
||||
|
|
@ -241,6 +268,8 @@ of the following host1x client modules:
|
|||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to core power domain.
|
||||
|
||||
- hdmi: High Definition Multimedia Interface
|
||||
|
||||
|
|
@ -267,6 +296,7 @@ of the following host1x client modules:
|
|||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
|
||||
- nvidia,edid: supplies a binary EDID blob
|
||||
- nvidia,panel: phandle of a display panel
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
|
||||
- tvo: TV encoder output
|
||||
|
||||
|
|
@ -277,6 +307,10 @@ of the following host1x client modules:
|
|||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
||||
Optional properties:
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to core power domain.
|
||||
|
||||
- dsi: display serial interface
|
||||
|
||||
Required properties:
|
||||
|
|
@ -305,6 +339,7 @@ of the following host1x client modules:
|
|||
- nvidia,panel: phandle of a display panel
|
||||
- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
|
||||
up with in order to support up to 8 data lanes
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
|
||||
- sor: serial output resource
|
||||
|
||||
|
|
@ -408,6 +443,8 @@ Example:
|
|||
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
|
||||
resets = <&tegra_car 28>;
|
||||
reset-names = "host1x";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -421,6 +458,8 @@ Example:
|
|||
clocks = <&tegra_car TEGRA20_CLK_MPE>;
|
||||
resets = <&tegra_car 60>;
|
||||
reset-names = "mpe";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
vi@54080000 {
|
||||
|
|
@ -429,6 +468,7 @@ Example:
|
|||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
|
||||
clocks = <&tegra_car TEGRA210_CLK_VI>;
|
||||
power-domains = <&pd_venc>;
|
||||
|
|
@ -510,6 +550,8 @@ Example:
|
|||
clocks = <&tegra_car TEGRA20_CLK_EPP>;
|
||||
resets = <&tegra_car 19>;
|
||||
reset-names = "epp";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
isp {
|
||||
|
|
@ -528,6 +570,8 @@ Example:
|
|||
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
|
||||
resets = <&tegra_car 21>;
|
||||
reset-names = "2d";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
gr3d {
|
||||
|
|
@ -536,6 +580,8 @@ Example:
|
|||
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
|
||||
resets = <&tegra_car 24>;
|
||||
reset-names = "3d";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
dc@54200000 {
|
||||
|
|
@ -547,6 +593,8 @@ Example:
|
|||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 27>;
|
||||
reset-names = "dc";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
|
||||
<&mc TEGRA20_MC_DISPLAY0B &emc>,
|
||||
|
|
@ -571,6 +619,8 @@ Example:
|
|||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 26>;
|
||||
reset-names = "dc";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
|
||||
<&mc TEGRA20_MC_DISPLAY0BB &emc>,
|
||||
|
|
@ -596,6 +646,7 @@ Example:
|
|||
resets = <&tegra_car 51>;
|
||||
reset-names = "hdmi";
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
|
||||
tvo {
|
||||
|
|
@ -604,6 +655,7 @@ Example:
|
|||
interrupts = <0 76 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_TVO>;
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
|
||||
dsi {
|
||||
|
|
@ -615,6 +667,7 @@ Example:
|
|||
resets = <&tegra_car 48>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,107 +0,0 @@
|
|||
NVIDIA Tegra Boot and Power Management Processor (BPMP)
|
||||
|
||||
The BPMP is a specific processor in Tegra chip, which is designed for
|
||||
booting process handling and offloading the power management, clock
|
||||
management, and reset control tasks from the CPU. The binding document
|
||||
defines the resources that would be used by the BPMP firmware driver,
|
||||
which can create the interprocessor communication (IPC) between the CPU
|
||||
and BPMP.
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
Array of strings
|
||||
One of:
|
||||
- "nvidia,tegra186-bpmp"
|
||||
- mboxes : The phandle of mailbox controller and the mailbox specifier.
|
||||
- shmem : List of the phandle of the TX and RX shared memory area that
|
||||
the IPC between CPU and BPMP is based on.
|
||||
- #clock-cells : Should be 1.
|
||||
- #power-domain-cells : Should be 1.
|
||||
- #reset-cells : Should be 1.
|
||||
|
||||
This node is a mailbox consumer. See the following files for details of
|
||||
the mailbox subsystem, and the specifiers implemented by the relevant
|
||||
provider(s):
|
||||
|
||||
- .../mailbox/mailbox.txt
|
||||
- .../mailbox/nvidia,tegra186-hsp.txt
|
||||
|
||||
This node is a clock, power domain, and reset provider. See the following
|
||||
files for general documentation of those features, and the specifiers
|
||||
implemented by this node:
|
||||
|
||||
- .../clock/clock-bindings.txt
|
||||
- <dt-bindings/clock/tegra186-clock.h>
|
||||
- ../power/power-domain.yaml
|
||||
- <dt-bindings/power/tegra186-powergate.h>
|
||||
- .../reset/reset.txt
|
||||
- <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
The BPMP implements some services which must be represented by separate nodes.
|
||||
For example, it can provide access to certain I2C controllers, and the I2C
|
||||
bindings represent each I2C controller as a device tree node. Such nodes should
|
||||
be nested directly inside the main BPMP node.
|
||||
|
||||
Software can determine whether a child node of the BPMP node represents a device
|
||||
by checking for a compatible property. Any node with a compatible property
|
||||
represents a device that can be instantiated. Nodes without a compatible
|
||||
property may be used to provide configuration information regarding the BPMP
|
||||
itself, although no such configuration nodes are currently defined by this
|
||||
binding.
|
||||
|
||||
The BPMP firmware defines no single global name-/numbering-space for such
|
||||
services. Put another way, the numbering scheme for I2C buses is distinct from
|
||||
the numbering scheme for any other service the BPMP may provide (e.g. a future
|
||||
hypothetical SPI bus service). As such, child device nodes will have no reg
|
||||
property, and the BPMP node will have no #address-cells or #size-cells property.
|
||||
|
||||
The shared memory bindings for BPMP
|
||||
-----------------------------------
|
||||
|
||||
The shared memory area for the IPC TX and RX between CPU and BPMP are
|
||||
predefined and work on top of sysram, which is an SRAM inside the chip.
|
||||
|
||||
See ".../sram/sram.txt" for the bindings.
|
||||
|
||||
Example:
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
...
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
sysram@30000000 {
|
||||
compatible = "nvidia,tegra186-sysram", "mmio-sram";
|
||||
reg = <0x0 0x30000000 0x0 0x50000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
|
||||
|
||||
cpu_bpmp_tx: shmem@4e000 {
|
||||
compatible = "nvidia,tegra186-bpmp-shmem";
|
||||
reg = <0x0 0x4e000 0x0 0x1000>;
|
||||
label = "cpu-bpmp-tx";
|
||||
pool;
|
||||
};
|
||||
|
||||
cpu_bpmp_rx: shmem@4f000 {
|
||||
compatible = "nvidia,tegra186-bpmp-shmem";
|
||||
reg = <0x0 0x4f000 0x0 0x1000>;
|
||||
label = "cpu-bpmp-rx";
|
||||
pool;
|
||||
};
|
||||
};
|
||||
|
||||
bpmp {
|
||||
compatible = "nvidia,tegra186-bpmp";
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
|
||||
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
i2c {
|
||||
compatible = "...";
|
||||
...
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
The BPMP is a specific processor in Tegra chip, which is designed for
|
||||
booting process handling and offloading the power management, clock
|
||||
management, and reset control tasks from the CPU. The binding document
|
||||
defines the resources that would be used by the BPMP firmware driver,
|
||||
which can create the interprocessor communication (IPC) between the
|
||||
CPU and BPMP.
|
||||
|
||||
This node is a mailbox consumer. See the following files for details
|
||||
of the mailbox subsystem, and the specifiers implemented by the
|
||||
relevant provider(s):
|
||||
|
||||
- .../mailbox/mailbox.txt
|
||||
- .../mailbox/nvidia,tegra186-hsp.yaml
|
||||
|
||||
This node is a clock, power domain, and reset provider. See the
|
||||
following files for general documentation of those features, and the
|
||||
specifiers implemented by this node:
|
||||
|
||||
- .../clock/clock-bindings.txt
|
||||
- <dt-bindings/clock/tegra186-clock.h>
|
||||
- ../power/power-domain.yaml
|
||||
- <dt-bindings/power/tegra186-powergate.h>
|
||||
- .../reset/reset.txt
|
||||
- <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
The BPMP implements some services which must be represented by
|
||||
separate nodes. For example, it can provide access to certain I2C
|
||||
controllers, and the I2C bindings represent each I2C controller as a
|
||||
device tree node. Such nodes should be nested directly inside the main
|
||||
BPMP node.
|
||||
|
||||
Software can determine whether a child node of the BPMP node
|
||||
represents a device by checking for a compatible property. Any node
|
||||
with a compatible property represents a device that can be
|
||||
instantiated. Nodes without a compatible property may be used to
|
||||
provide configuration information regarding the BPMP itself, although
|
||||
no such configuration nodes are currently defined by this binding.
|
||||
|
||||
The BPMP firmware defines no single global name-/numbering-space for
|
||||
such services. Put another way, the numbering scheme for I2C buses is
|
||||
distinct from the numbering scheme for any other service the BPMP may
|
||||
provide (e.g. a future hypothetical SPI bus service). As such, child
|
||||
device nodes will have no reg property, and the BPMP node will have no
|
||||
"#address-cells" or "#size-cells" property.
|
||||
|
||||
The shared memory area for the IPC TX and RX between CPU and BPMP are
|
||||
predefined and work on top of sysram, which is an SRAM inside the
|
||||
chip. See ".../sram/sram.yaml" for the bindings.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra194-bpmp
|
||||
- nvidia,tegra234-bpmp
|
||||
- const: nvidia,tegra186-bpmp
|
||||
- const: nvidia,tegra186-bpmp
|
||||
|
||||
mboxes:
|
||||
description: A phandle and channel specifier for the mailbox used to
|
||||
communicate with the BPMP.
|
||||
maxItems: 1
|
||||
|
||||
shmem:
|
||||
description: List of the phandle to the TX and RX shared memory area
|
||||
that the IPC between CPU and BPMP is based on.
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
- description: DMA read client
|
||||
- description: DMA write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: read
|
||||
- const: write
|
||||
- const: dma-mem # dma-read
|
||||
- const: dma-write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
i2c:
|
||||
type: object
|
||||
|
||||
thermal:
|
||||
type: object
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mboxes
|
||||
- shmem
|
||||
- "#clock-cells"
|
||||
- "#power-domain-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
compatible = "nvidia,tegra186-hsp";
|
||||
reg = <0x03c00000 0xa0000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "doorbell";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
sram@30000000 {
|
||||
compatible = "nvidia,tegra186-sysram", "mmio-sram";
|
||||
reg = <0x30000000 0x50000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x30000000 0x50000>;
|
||||
|
||||
cpu_bpmp_tx: sram@4e000 {
|
||||
reg = <0x4e000 0x1000>;
|
||||
label = "cpu-bpmp-tx";
|
||||
pool;
|
||||
};
|
||||
|
||||
cpu_bpmp_rx: sram@4f000 {
|
||||
reg = <0x4f000 0x1000>;
|
||||
label = "cpu-bpmp-rx";
|
||||
pool;
|
||||
};
|
||||
};
|
||||
|
||||
bpmp {
|
||||
compatible = "nvidia,tegra186-bpmp";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
|
||||
interconnect-names = "read", "write", "dma-mem", "dma-write";
|
||||
iommus = <&smmu TEGRA186_SID_BPMP>;
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
|
||||
TEGRA_HSP_DB_MASTER_BPMP>;
|
||||
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
i2c {
|
||||
compatible = "nvidia,tegra186-bpmp-i2c";
|
||||
nvidia,bpmp-bus-id = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
thermal {
|
||||
compatible = "nvidia,tegra186-bpmp-thermal";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
|
||||
|
||||
Required properties:
|
||||
- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
|
||||
must contain "nvidia,tegra30-efuse". For Tegra114, must contain
|
||||
"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
|
||||
For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
|
||||
For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
|
||||
"nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
|
||||
For Tegra234 must contain "nvidia,tegra234-efuse".
|
||||
Details:
|
||||
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
|
||||
due to a hardware bug. Tegra20 also lacks certain information which is
|
||||
available in later generations such as fab code, lot code, wafer id,..
|
||||
nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
|
||||
The differences between these SoCs are the size of the efuse array,
|
||||
the location of the spare (OEM programmable) bits and the location of
|
||||
the speedo data.
|
||||
- reg: Should contain 1 entry: the entry gives the physical address and length
|
||||
of the fuse registers.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- fuse
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- fuse
|
||||
|
||||
Example:
|
||||
|
||||
fuse@7000f800 {
|
||||
compatible = "nvidia,tegra20-efuse";
|
||||
reg = <0x7000f800 0x400>,
|
||||
<0x70000000 0x400>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra FUSE block
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- nvidia,tegra20-efuse
|
||||
- nvidia,tegra30-efuse
|
||||
- nvidia,tegra114-efuse
|
||||
- nvidia,tegra124-efuse
|
||||
- nvidia,tegra210-efuse
|
||||
- nvidia,tegra186-efuse
|
||||
- nvidia,tegra194-efuse
|
||||
- nvidia,tegra234-efuse
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra132-efuse
|
||||
- const: nvidia,tegra124-efuse
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fuse
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: fuse
|
||||
|
||||
operating-points-v2:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: phandle to the core power domain
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra20-efuse
|
||||
- nvidia,tegra30-efuse
|
||||
- nvidia,tegra114-efuse
|
||||
- nvidia,tegra124-efuse
|
||||
- nvidia,tegra132-efuse
|
||||
- nvidia,tegra210-efuse
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
|
||||
fuse@7000f800 {
|
||||
compatible = "nvidia,tegra20-efuse";
|
||||
reg = <0x7000f800 0x400>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra NVENC
|
||||
|
||||
description: |
|
||||
NVENC is the hardware video encoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically
|
||||
programmed through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvenc@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvenc
|
||||
- nvidia,tegra186-nvenc
|
||||
- nvidia,tegra194-nvenc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvenc
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvenc
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
interconnect-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
nvidia,host1x-class:
|
||||
description: |
|
||||
Host1x class of the engine, used to specify the targeted engine
|
||||
when programming the engine through Host1x channels or when
|
||||
configuring engine-specific behavior in Host1x.
|
||||
default: 0x21
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvenc
|
||||
- nvidia,tegra186-nvenc
|
||||
then:
|
||||
properties:
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA write memory client
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-nvenc
|
||||
then:
|
||||
properties:
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA read 2 memory client
|
||||
- description: DMA write memory client
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: read-1
|
||||
- const: write
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
nvenc@154c0000 {
|
||||
compatible = "nvidia,tegra186-nvenc";
|
||||
reg = <0x154c0000 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVENC>;
|
||||
clock-names = "nvenc";
|
||||
resets = <&bpmp TEGRA186_RESET_NVENC>;
|
||||
reset-names = "nvenc";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_NVENC>;
|
||||
};
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra NVJPG
|
||||
|
||||
description: |
|
||||
NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically programmed
|
||||
through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvjpg@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvjpg
|
||||
- nvidia,tegra186-nvjpg
|
||||
- nvidia,tegra194-nvjpg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvjpg
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvjpg
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA write memory client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
nvjpg@15380000 {
|
||||
compatible = "nvidia,tegra186-nvjpg";
|
||||
reg = <0x15380000 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
|
||||
clock-names = "nvjpg";
|
||||
resets = <&bpmp TEGRA186_RESET_NVJPG>;
|
||||
reset-names = "nvjpg";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_NVJPG>;
|
||||
};
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
NVIDIA Tegra Hardware Synchronization Primitives (HSP)
|
||||
|
||||
The HSP modules are used for the processors to share resources and communicate
|
||||
together. It provides a set of hardware synchronization primitives for
|
||||
interprocessor communication. So the interprocessor communication (IPC)
|
||||
protocols can use hardware synchronization primitives, when operating between
|
||||
two processors not in an SMP relationship.
|
||||
|
||||
The features that HSP supported are shared mailboxes, shared semaphores,
|
||||
arbitrated semaphores and doorbells.
|
||||
|
||||
Required properties:
|
||||
- name : Should be hsp
|
||||
- compatible
|
||||
Array of strings.
|
||||
one of:
|
||||
- "nvidia,tegra186-hsp"
|
||||
- "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
|
||||
- reg : Offset and length of the register set for the device.
|
||||
- interrupt-names
|
||||
Array of strings.
|
||||
Contains a list of names for the interrupts described by the interrupt
|
||||
property. May contain the following entries, in any order:
|
||||
- "doorbell"
|
||||
- "sharedN", where 'N' is a number from zero up to the number of
|
||||
external interrupts supported by the HSP instance minus one.
|
||||
Users of this binding MUST look up entries in the interrupt property
|
||||
by name, using this interrupt-names property to do so.
|
||||
- interrupts
|
||||
Array of interrupt specifiers.
|
||||
Must contain one entry per entry in the interrupt-names property,
|
||||
in a matching order.
|
||||
- #mbox-cells : Should be 2.
|
||||
|
||||
The mbox specifier of the "mboxes" property in the client node should contain
|
||||
two cells. The first cell determines the HSP type and the second cell is used
|
||||
to identify the mailbox that the client is going to use.
|
||||
|
||||
For doorbells, the second cell specifies the index of the doorbell to use.
|
||||
|
||||
For shared mailboxes, the second cell is composed of two fields:
|
||||
- bits 31..24:
|
||||
A bit mask of flags that further specify how the shared mailbox will be
|
||||
used. Valid flags are:
|
||||
- bit 31:
|
||||
Defines the direction of the mailbox. If set, the mailbox will be used
|
||||
as a producer (i.e. used to send data). If cleared, the mailbox is the
|
||||
consumer of data sent by a producer.
|
||||
|
||||
- bits 23.. 0:
|
||||
The index of the shared mailbox to use. The number of available mailboxes
|
||||
may vary by instance of the HSP block and SoC generation.
|
||||
|
||||
The following file contains definitions that can be used to construct mailbox
|
||||
specifiers:
|
||||
|
||||
<dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
Example:
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
compatible = "nvidia,tegra186-hsp";
|
||||
reg = <0x0 0x03c00000 0x0 0xa0000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "doorbell";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
client {
|
||||
...
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;
|
||||
};
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
The HSP modules are used for the processors to share resources and
|
||||
communicate together. It provides a set of hardware synchronization
|
||||
primitives for interprocessor communication. So the interprocessor
|
||||
communication (IPC) protocols can use hardware synchronization
|
||||
primitives, when operating between two processors not in an SMP
|
||||
relationship.
|
||||
|
||||
The features that HSP supported are shared mailboxes, shared
|
||||
semaphores, arbitrated semaphores and doorbells.
|
||||
|
||||
The mbox specifier of the "mboxes" property in the client node should
|
||||
contain two cells. The first cell determines the HSP type and the
|
||||
second cell is used to identify the mailbox that the client is going
|
||||
to use.
|
||||
|
||||
For doorbells, the second cell specifies the index of the doorbell to
|
||||
use.
|
||||
|
||||
For shared mailboxes, the second cell is composed of two fields:
|
||||
- bits 31..24:
|
||||
A bit mask of flags that further specify how the shared mailbox
|
||||
will be used. Valid flags are:
|
||||
- bit 31:
|
||||
Defines the direction of the mailbox. If set, the mailbox
|
||||
will be used as a producer (i.e. used to send data). If
|
||||
cleared, the mailbox is the consumer of data sent by a
|
||||
producer.
|
||||
|
||||
- bits 23..0:
|
||||
The index of the shared mailbox to use. The number of available
|
||||
mailboxes may vary by instance of the HSP block and SoC
|
||||
generation.
|
||||
|
||||
The following file contains definitions that can be used to
|
||||
construct mailbox specifiers:
|
||||
|
||||
<dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^hsp@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra186-hsp
|
||||
- const: nvidia,tegra194-hsp
|
||||
- items:
|
||||
- const: nvidia,tegra234-hsp
|
||||
- const: nvidia,tegra194-hsp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
oneOf:
|
||||
# shared interrupts are optional
|
||||
- items:
|
||||
- const: doorbell
|
||||
|
||||
- items:
|
||||
- const: doorbell
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
|
||||
- items:
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
|
||||
"#mbox-cells":
|
||||
const: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
compatible = "nvidia,tegra186-hsp";
|
||||
reg = <0x03c00000 0xa0000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "doorbell";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
client {
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
|
||||
};
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
NVIDIA Tegra Video Decoder Engine
|
||||
|
||||
Required properties:
|
||||
- compatible : Must contain one of the following values:
|
||||
- "nvidia,tegra20-vde"
|
||||
- "nvidia,tegra30-vde"
|
||||
- "nvidia,tegra114-vde"
|
||||
- "nvidia,tegra124-vde"
|
||||
- "nvidia,tegra132-vde"
|
||||
- reg : Must contain an entry for each entry in reg-names.
|
||||
- reg-names : Must include the following entries:
|
||||
- sxe
|
||||
- bsev
|
||||
- mbe
|
||||
- ppe
|
||||
- mce
|
||||
- tfe
|
||||
- ppb
|
||||
- vdma
|
||||
- frameid
|
||||
- iram : Must contain phandle to the mmio-sram device node that represents
|
||||
IRAM region used by VDE.
|
||||
- interrupts : Must contain an entry for each entry in interrupt-names.
|
||||
- interrupt-names : Must include the following entries:
|
||||
- sync-token
|
||||
- bsev
|
||||
- sxe
|
||||
- clocks : Must include the following entries:
|
||||
- vde
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
- reset-names : Should include the following entries:
|
||||
- vde
|
||||
|
||||
Optional properties:
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
- reset-names : Must include the following entries:
|
||||
- mc
|
||||
- iommus: Must contain phandle to the IOMMU device node.
|
||||
|
||||
Example:
|
||||
|
||||
video-codec@6001a000 {
|
||||
compatible = "nvidia,tegra20-vde";
|
||||
reg = <0x6001a000 0x1000 /* Syntax Engine */
|
||||
0x6001b000 0x1000 /* Video Bitstream Engine */
|
||||
0x6001c000 0x100 /* Macroblock Engine */
|
||||
0x6001c200 0x100 /* Post-processing Engine */
|
||||
0x6001c400 0x100 /* Motion Compensation Engine */
|
||||
0x6001c600 0x100 /* Transform Engine */
|
||||
0x6001c800 0x100 /* Pixel prediction block */
|
||||
0x6001ca00 0x100 /* Video DMA */
|
||||
0x6001d800 0x300 /* Video frame controls */>;
|
||||
reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
|
||||
"tfe", "ppb", "vdma", "frameid";
|
||||
iram = <&vde_pool>; /* IRAM region */
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
|
||||
interrupt-names = "sync-token", "bsev", "sxe";
|
||||
clocks = <&tegra_car TEGRA20_CLK_VDE>;
|
||||
reset-names = "vde", "mc";
|
||||
resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
|
||||
iommus = <&mc TEGRA_SWGROUP_VDE>;
|
||||
};
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Video Decoder Engine
|
||||
|
||||
maintainers:
|
||||
- Dmitry Osipenko <digetx@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra132-vde
|
||||
- nvidia,tegra124-vde
|
||||
- nvidia,tegra114-vde
|
||||
- items:
|
||||
- const: nvidia,tegra30-vde
|
||||
- const: nvidia,tegra20-vde
|
||||
- items:
|
||||
- const: nvidia,tegra20-vde
|
||||
|
||||
reg:
|
||||
maxItems: 9
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: sxe
|
||||
- const: bsev
|
||||
- const: mbe
|
||||
- const: ppe
|
||||
- const: mce
|
||||
- const: tfe
|
||||
- const: ppb
|
||||
- const: vdma
|
||||
- const: frameid
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: vde
|
||||
- const: mc
|
||||
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: sync-token
|
||||
- const: bsev
|
||||
- const: sxe
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
iram:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle of the SRAM MMIO node.
|
||||
|
||||
operating-points-v2:
|
||||
description:
|
||||
Should contain freqs and voltages and opp-supported-hw property,
|
||||
which is a bitfield indicating SoC speedo or process ID mask.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle to the SoC core power domain.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- resets
|
||||
- reset-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
video-codec@6001a000 {
|
||||
compatible = "nvidia,tegra20-vde";
|
||||
reg = <0x6001a000 0x1000>, /* Syntax Engine */
|
||||
<0x6001b000 0x1000>, /* Video Bitstream Engine */
|
||||
<0x6001c000 0x100>, /* Macroblock Engine */
|
||||
<0x6001c200 0x100>, /* Post-processing Engine */
|
||||
<0x6001c400 0x100>, /* Motion Compensation Engine */
|
||||
<0x6001c600 0x100>, /* Transform Engine */
|
||||
<0x6001c800 0x100>, /* Pixel prediction block */
|
||||
<0x6001ca00 0x100>, /* Video DMA */
|
||||
<0x6001d800 0x300>; /* Video frame controls */
|
||||
reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
|
||||
"tfe", "ppb", "vdma", "frameid";
|
||||
iram = <&iram>; /* IRAM MMIO region */
|
||||
interrupts = <0 9 4>, /* Sync token */
|
||||
<0 10 4>, /* BSE-V */
|
||||
<0 12 4>; /* SXE */
|
||||
interrupt-names = "sync-token", "bsev", "sxe";
|
||||
clocks = <&clk 61>;
|
||||
reset-names = "vde", "mc";
|
||||
resets = <&rst 61>, <&mem 13>;
|
||||
iommus = <&mem 15>;
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
|
@ -31,12 +31,15 @@ properties:
|
|||
- enum:
|
||||
- nvidia,tegra186-mc
|
||||
- nvidia,tegra194-mc
|
||||
- nvidia,tegra234-mc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: MC general interrupt
|
||||
|
||||
"#address-cells":
|
||||
const: 2
|
||||
|
|
@ -48,6 +51,9 @@ properties:
|
|||
|
||||
dma-ranges: true
|
||||
|
||||
"#interconnect-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^external-memory-controller@[0-9a-f]+$":
|
||||
description:
|
||||
|
|
@ -63,12 +69,15 @@ patternProperties:
|
|||
- enum:
|
||||
- nvidia,tegra186-emc
|
||||
- nvidia,tegra194-emc
|
||||
- nvidia,tegra234-emc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: EMC general interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -78,11 +87,83 @@ patternProperties:
|
|||
items:
|
||||
- const: emc
|
||||
|
||||
"#interconnect-cells":
|
||||
const: 0
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle of the node representing the BPMP
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra186-emc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra194-emc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra234-emc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#interconnect-cells"
|
||||
- nvidia,bpmp
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra186-mc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra194-mc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra234-mc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -90,8 +171,6 @@ required:
|
|||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
|
|
@ -124,12 +203,9 @@ examples:
|
|||
clocks = <&bpmp TEGRA186_CLK_EMC>;
|
||||
clock-names = "emc";
|
||||
|
||||
#interconnect-cells = <0>;
|
||||
|
||||
nvidia,bpmp = <&bpmp>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
bpmp: bpmp {
|
||||
compatible = "nvidia,tegra186-bpmp";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,14 +0,0 @@
|
|||
NVIDIA Tegra186 (and later) MISC register block
|
||||
|
||||
The MISC register block found on Tegra186 and later SoCs contains registers
|
||||
that can be used to identify a given chip and various strapping options.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be:
|
||||
- Tegra186: "nvidia,tegra186-misc"
|
||||
- Tegra194: "nvidia,tegra194-misc"
|
||||
- Tegra234: "nvidia,tegra234-misc"
|
||||
- reg: Should contain 2 entries: The first entry gives the physical address
|
||||
and length of the register region which contains revision and debug
|
||||
features. The second entry specifies the physical address and length
|
||||
of the register region indicating the strapping options.
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra186 (and later) MISC register block
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: The MISC register block found on Tegra186 and later SoCs contains
|
||||
registers that can be used to identify a given chip and various strapping
|
||||
options.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra186-misc
|
||||
- nvidia,tegra194-misc
|
||||
- nvidia,tegra234-misc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: physical address and length of the registers which
|
||||
contain revision and debug features
|
||||
- description: physical address and length of the registers which
|
||||
indicate strapping options
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
misc@100000 {
|
||||
compatible = "nvidia,tegra186-misc";
|
||||
reg = <0x00100000 0xf000>,
|
||||
<0x0010f000 0x1000>;
|
||||
};
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
NVIDIA Tegra APBMISC block
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be:
|
||||
- Tegra20: "nvidia,tegra20-apbmisc"
|
||||
- Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- reg: Should contain 2 entries: the first entry gives the physical address
|
||||
and length of the registers which contain revision and debug features.
|
||||
The second entry gives the physical address and length of the
|
||||
registers indicating the strapping options.
|
||||
|
||||
Optional properties:
|
||||
- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra APBMISC block
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra210-apbmisc
|
||||
- nvidia,tegra124-apbmisc
|
||||
- nvidia,tegra114-apbmisc
|
||||
- nvidia,tegra30-apbmisc
|
||||
- const: nvidia,tegra20-apbmisc
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra20-apbmisc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: physical address and length of the registers which
|
||||
contain revision and debug features
|
||||
- description: physical address and length of the registers which
|
||||
indicate strapping options
|
||||
|
||||
nvidia,long-ram-code:
|
||||
description: If present, the RAM code is long (4 bit). If not, short
|
||||
(2 bit).
|
||||
type: boolean
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
apbmisc@70000800 {
|
||||
compatible = "nvidia,tegra20-apbmisc";
|
||||
reg = <0x70000800 0x64>, /* Chip revision */
|
||||
<0x70000008 0x04>; /* Strapping options */
|
||||
};
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
* NVIDIA Tegra Secure Digital Host Controller
|
||||
|
||||
This controller on Tegra family SoCs provides an interface for MMC, SD,
|
||||
and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the sdhci-tegra driver.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of:
|
||||
- "nvidia,tegra20-sdhci": for Tegra20
|
||||
- "nvidia,tegra30-sdhci": for Tegra30
|
||||
- "nvidia,tegra114-sdhci": for Tegra114
|
||||
- "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
|
||||
- "nvidia,tegra210-sdhci": for Tegra210
|
||||
- "nvidia,tegra186-sdhci": for Tegra186
|
||||
- "nvidia,tegra194-sdhci": for Tegra194
|
||||
- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
|
||||
One for the module clock and one for the timeout clock.
|
||||
For all other Tegra devices, must contain a single entry for
|
||||
the module clock. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
|
||||
strings 'sdhci' and 'tmclk' to represent the module and
|
||||
the timeout clocks, respectively.
|
||||
For all other Tegra devices must contain the string 'sdhci'
|
||||
to represent the module clock.
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
- sdhci
|
||||
|
||||
Optional properties:
|
||||
- power-gpios : Specify GPIOs for power control
|
||||
|
||||
Example:
|
||||
|
||||
sdhci@c8000200 {
|
||||
compatible = "nvidia,tegra20-sdhci";
|
||||
reg = <0xc8000200 0x200>;
|
||||
interrupts = <47>;
|
||||
clocks = <&tegra_car 14>;
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
Optional properties for Tegra210, Tegra186 and Tegra194:
|
||||
- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
|
||||
configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
|
||||
for controllers supporting multiple voltage levels. The order of names
|
||||
should correspond to the pin configuration states in pinctrl-0 and
|
||||
pinctrl-1.
|
||||
- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
|
||||
Tegra210 where pad config registers are in the pinmux register domain
|
||||
for pull-up-strength and pull-down-strength values configuration when
|
||||
using pads at 3V3 and 1V8 levels.
|
||||
- nvidia,only-1-8-v : The presence of this property indicates that the
|
||||
controller operates at a 1.8 V fixed I/O voltage.
|
||||
- nvidia,pad-autocal-pull-up-offset-3v3,
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
|
||||
calibration offsets for 3.3 V signaling modes.
|
||||
- nvidia,pad-autocal-pull-up-offset-1v8,
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
|
||||
calibration offsets for 1.8 V signaling modes.
|
||||
- nvidia,pad-autocal-pull-up-offset-3v3-timeout,
|
||||
nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
|
||||
strength used as a fallback in case the automatic calibration times
|
||||
out on a 3.3 V signaling mode.
|
||||
- nvidia,pad-autocal-pull-up-offset-1v8-timeout,
|
||||
nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
|
||||
strength used as a fallback in case the automatic calibration times
|
||||
out on a 1.8 V signaling mode.
|
||||
- nvidia,pad-autocal-pull-up-offset-sdr104,
|
||||
nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
|
||||
calibration offsets for SDR104 mode.
|
||||
- nvidia,pad-autocal-pull-up-offset-hs400,
|
||||
nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
|
||||
calibration offsets for HS400 mode.
|
||||
- nvidia,default-tap : Specify the default inbound sampling clock
|
||||
trimmer value for non-tunable modes.
|
||||
- nvidia,default-trim : Specify the default outbound clock trimmer
|
||||
value.
|
||||
- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
|
||||
|
||||
Notes on the pad calibration pull up and pulldown offset values:
|
||||
- The property values are drive codes which are programmed into the
|
||||
PD_OFFSET and PU_OFFSET sections of the
|
||||
SDHCI_TEGRA_AUTO_CAL_CONFIG register.
|
||||
- A higher value corresponds to higher drive strength. Please refer
|
||||
to the reference manual of the SoC for correct values.
|
||||
- The SDR104 and HS400 timing specific values are used in
|
||||
corresponding modes if specified.
|
||||
|
||||
Notes on tap and trim values:
|
||||
- The values are used for compensating trace length differences
|
||||
by adjusting the sampling point.
|
||||
- The values are programmed to the Vendor Clock Control Register.
|
||||
Please refer to the reference manual of the SoC for correct
|
||||
values.
|
||||
- The DQS trim values are only used on controllers which support
|
||||
HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
|
||||
HS400.
|
||||
|
||||
Example:
|
||||
sdhci@700b0000 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,317 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Secure Digital Host Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
This controller on Tegra family SoCs provides an interface for MMC, SD, and
|
||||
SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described by
|
||||
mmc-controller.yaml and the properties for the Tegra SDHCI controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- nvidia,tegra20-sdhci
|
||||
- nvidia,tegra30-sdhci
|
||||
- nvidia,tegra114-sdhci
|
||||
- nvidia,tegra124-sdhci
|
||||
- nvidia,tegra210-sdhci
|
||||
- nvidia,tegra186-sdhci
|
||||
- nvidia,tegra194-sdhci
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra132-sdhci
|
||||
- const: nvidia,tegra124-sdhci
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra194-sdhci
|
||||
- nvidia,tegra234-sdhci
|
||||
- const: nvidia,tegra186-sdhci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
assigned-clocks: true
|
||||
assigned-clock-parents: true
|
||||
assigned-clock-rates: true
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: sdhci
|
||||
|
||||
power-gpios:
|
||||
description: specify GPIOs for power control
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: phandle to the core power domain
|
||||
|
||||
nvidia,default-tap:
|
||||
description: Specify the default inbound sampling clock trimmer value for
|
||||
non-tunable modes.
|
||||
|
||||
The values are used for compensating trace length differences by
|
||||
adjusting the sampling point. The values are programmed to the Vendor
|
||||
Clock Control Register. Please refer to the reference manual of the SoC
|
||||
for correct values.
|
||||
|
||||
The DQS trim values are only used on controllers which support HS400
|
||||
timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,default-trim:
|
||||
description: Specify the default outbound clock trimmer value.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,dqs-trim:
|
||||
description: Specify DQS trim value for HS400 timing.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-1v8:
|
||||
description: Specify drive strength calibration offsets for 1.8 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-1v8-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 1.8 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-3v3:
|
||||
description: Specify drive strength calibration offsets for 3.3 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-3v3-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 3.3 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-sdr104:
|
||||
description: Specify drive strength calibration offsets for SDR104 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-hs400:
|
||||
description: Specify drive strength calibration offsets for HS400 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-1v8:
|
||||
description: Specify drive strength calibration offsets for 1.8 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-1v8-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 1.8 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-3v3:
|
||||
description: Specify drive strength calibration offsets for 3.3 V
|
||||
signaling modes.
|
||||
|
||||
The property values are drive codes which are programmed into the
|
||||
PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
|
||||
register. A higher value corresponds to higher drive strength. Please
|
||||
refer to the reference manual of the SoC for correct values. The SDR104
|
||||
and HS400 timing specific values are used in corresponding modes if
|
||||
specified.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-3v3-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 3.3 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-sdr104:
|
||||
description: Specify drive strength calibration offsets for SDR104 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-hs400:
|
||||
description: Specify drive strength calibration offsets for HS400 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,only-1-8v:
|
||||
description: The presence of this property indicates that the controller
|
||||
operates at a 1.8 V fixed I/O voltage.
|
||||
$ref: "/schemas/types.yaml#/definitions/flag"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra20-sdhci
|
||||
- nvidia,tegra30-sdhci
|
||||
- nvidia,tegra114-sdhci
|
||||
- nvidia,tegra124-sdhci
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
- description: timeout clock
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: sdhci
|
||||
- const: tmclk
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra210-sdhci
|
||||
then:
|
||||
properties:
|
||||
pinctrl-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: sdmmc-3v3
|
||||
description: pad configuration for 3.3 V
|
||||
- const: sdmmc-1v8
|
||||
description: pad configuration for 1.8 V
|
||||
- const: sdmmc-3v3-drv
|
||||
description: pull-up/down configuration for 3.3 V
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
- items:
|
||||
- const: sdmmc-3v3-drv
|
||||
description: pull-up/down configuration for 3.3 V
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
- items:
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
required:
|
||||
- clock-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra186-sdhci
|
||||
- nvidia,tegra194-sdhci
|
||||
then:
|
||||
properties:
|
||||
pinctrl-names:
|
||||
items:
|
||||
- const: sdmmc-3v3
|
||||
description: pad configuration for 3.3 V
|
||||
- const: sdmmc-1v8
|
||||
description: pad configuration for 1.8 V
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mmc@c8000200 {
|
||||
compatible = "nvidia,tegra20-sdhci";
|
||||
reg = <0xc8000200 0x200>;
|
||||
interrupts = <47>;
|
||||
clocks = <&tegra_car 14>;
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mmc@700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x700b0000 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
|
||||
"sdmmc-3v3-drv", "sdmmc-1v8-drv";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
pinctrl-2 = <&sdmmc1_3v3_drv>;
|
||||
pinctrl-3 = <&sdmmc1_1v8_drv>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
nvidia,default-tap = <0x2>;
|
||||
nvidia,default-trim = <0x4>;
|
||||
assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_C4>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
|
||||
assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
|
||||
};
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
NVIDIA Tegra20 real-time clock
|
||||
|
||||
The Tegra RTC maintains seconds and milliseconds counters, and five alarm
|
||||
registers. The alarms and other interrupts may wake the system from low-power
|
||||
state.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
|
||||
must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
|
||||
can be tegra30, tegra114, tegra124, or tegra132.
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A single interrupt specifier.
|
||||
- clocks : Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
||||
Example:
|
||||
|
||||
timer {
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra real-time clock
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
The Tegra RTC maintains seconds and milliseconds counters, and five
|
||||
alarm registers. The alarms and other interrupts may wake the system
|
||||
from low-power state.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra20-rtc
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra30-rtc
|
||||
- nvidia,tegra114-rtc
|
||||
- nvidia,tegra124-rtc
|
||||
- nvidia,tegra210-rtc
|
||||
- nvidia,tegra186-rtc
|
||||
- nvidia,tegra194-rtc
|
||||
- nvidia,tegra234-rtc
|
||||
- const: nvidia,tegra20-rtc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: rtc
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
timer@7000e000 {
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
|
@ -113,9 +113,10 @@ properties:
|
|||
- nvidia,tegra30-uart
|
||||
- nvidia,tegra114-uart
|
||||
- nvidia,tegra124-uart
|
||||
- nvidia,tegra210-uart
|
||||
- nvidia,tegra186-uart
|
||||
- nvidia,tegra194-uart
|
||||
- nvidia,tegra210-uart
|
||||
- nvidia,tegra234-uart
|
||||
- const: nvidia,tegra20-uart
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -1,35 +0,0 @@
|
|||
NVIDIA Tegra Combined UART (TCU)
|
||||
|
||||
The TCU is a system for sharing a hardware UART instance among multiple
|
||||
systems within the Tegra SoC. It is implemented through a mailbox-
|
||||
based protocol where each "virtual UART" has a pair of mailboxes, one
|
||||
for transmitting and one for receiving, that is used to communicate
|
||||
with the hardware implementing the TCU.
|
||||
|
||||
Required properties:
|
||||
- name : Should be tcu
|
||||
- compatible
|
||||
Array of strings
|
||||
One of:
|
||||
- "nvidia,tegra194-tcu"
|
||||
- mbox-names:
|
||||
"rx" - Mailbox for receiving data from hardware UART
|
||||
"tx" - Mailbox for transmitting data to hardware UART
|
||||
- mboxes: Mailboxes corresponding to the mbox-names.
|
||||
|
||||
This node is a mailbox consumer. See the following files for details of
|
||||
the mailbox subsystem, and the specifiers implemented by the relevant
|
||||
provider(s):
|
||||
|
||||
- .../mailbox/mailbox.txt
|
||||
- .../mailbox/nvidia,tegra186-hsp.txt
|
||||
|
||||
Example bindings:
|
||||
-----------------
|
||||
|
||||
tcu: tcu {
|
||||
compatible = "nvidia,tegra194-tcu";
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
|
||||
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
|
||||
mbox-names = "rx", "tx";
|
||||
};
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Combined UART (TCU)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jonathan Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description:
|
||||
The TCU is a system for sharing a hardware UART instance among multiple
|
||||
systems within the Tegra SoC. It is implemented through a mailbox-
|
||||
based protocol where each "virtual UART" has a pair of mailboxes, one
|
||||
for transmitting and one for receiving, that is used to communicate
|
||||
with the hardware implementing the TCU.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^serial(@.*)?$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra194-tcu
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra234-tcu
|
||||
- const: nvidia,tegra194-tcu
|
||||
|
||||
mbox-names:
|
||||
items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
mboxes:
|
||||
description: |
|
||||
List of phandles to mailbox channels used for receiving and
|
||||
transmitting data from and to the hardware UART.
|
||||
items:
|
||||
- description: mailbox for receiving data from hardware UART
|
||||
- description: mailbox for transmitting data to hardware UART
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mbox-names
|
||||
- mboxes
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
tcu: serial {
|
||||
compatible = "nvidia,tegra194-tcu";
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
|
||||
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
|
||||
mbox-names = "rx", "tx";
|
||||
};
|
||||
|
|
@ -31,6 +31,9 @@ properties:
|
|||
- amlogic,meson-gxbb-sram
|
||||
- arm,juno-sram-ns
|
||||
- atmel,sama5d2-securam
|
||||
- nvidia,tegra186-sysram
|
||||
- nvidia,tegra194-sysram
|
||||
- nvidia,tegra234-sysram
|
||||
- qcom,rpm-msg-ram
|
||||
- rockchip,rk3288-pmu-sram
|
||||
|
||||
|
|
|
|||
|
|
@ -1,33 +0,0 @@
|
|||
NVIDIA Tegra186 BPMP thermal sensor
|
||||
|
||||
In Tegra186, the BPMP (Boot and Power Management Processor) implements an
|
||||
interface that is used to read system temperatures, including CPU cluster
|
||||
and GPU temperatures. This binding describes the thermal sensor that is
|
||||
exposed by BPMP.
|
||||
|
||||
The BPMP thermal node must be located directly inside the main BPMP node. See
|
||||
../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
|
||||
|
||||
This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the
|
||||
core thermal binding.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Array of strings.
|
||||
One of:
|
||||
- "nvidia,tegra186-bpmp-thermal"
|
||||
- "nvidia,tegra194-bpmp-thermal"
|
||||
- #thermal-sensor-cells: Cell for sensor index.
|
||||
Single-cell integer.
|
||||
Must be <1>.
|
||||
|
||||
Example:
|
||||
|
||||
bpmp {
|
||||
...
|
||||
|
||||
bpmp_thermal: thermal {
|
||||
compatible = "nvidia,tegra186-bpmp-thermal";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra186 (and later) BPMP thermal sensor
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
In Tegra186, the BPMP (Boot and Power Management Processor) implements
|
||||
an interface that is used to read system temperatures, including CPU
|
||||
cluster and GPU temperatures. This binding describes the thermal
|
||||
sensor that is exposed by BPMP.
|
||||
|
||||
The BPMP thermal node must be located directly inside the main BPMP
|
||||
node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the
|
||||
BPMP binding.
|
||||
|
||||
This node represents a thermal sensor. See
|
||||
|
||||
Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
|
||||
|
||||
for details of the core thermal binding.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra186-bpmp-thermal
|
||||
- nvidia,tegra194-bpmp-thermal
|
||||
|
||||
'#thermal-sensor-cells':
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Number of cells needed in the phandle specifier to
|
||||
identify a given sensor. Must be 1 and the single cell specifies
|
||||
the sensor index.
|
||||
const: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -59,6 +59,19 @@ properties:
|
|||
- const: fs_src
|
||||
- const: hs_src
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: XUSBB(device) power-domain
|
||||
|
|
|
|||
|
|
@ -4,11 +4,31 @@
|
|||
#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
|
||||
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @defgroup bpmp_clock_ids Clock ID's
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief controls the EMC clock frequency.
|
||||
* @details Doing a clk_set_rate on this clock will select the
|
||||
* appropriate clock source, program the source rate and execute a
|
||||
* specific sequence to switch to the new clock source for both memory
|
||||
* controllers. This can be used to control the balance between memory
|
||||
* throughput and memory controller power.
|
||||
*/
|
||||
#define TEGRA234_CLK_EMC 31U
|
||||
/** @brief output of gate CLK_ENB_FUSE */
|
||||
#define TEGRA234_CLK_FUSE 40
|
||||
#define TEGRA234_CLK_FUSE 40U
|
||||
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
|
||||
#define TEGRA234_CLK_SDMMC4 123
|
||||
#define TEGRA234_CLK_SDMMC4 123U
|
||||
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
|
||||
#define TEGRA234_CLK_UARTA 155
|
||||
#define TEGRA234_CLK_UARTA 155U
|
||||
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
|
||||
#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
|
||||
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
|
||||
#define TEGRA234_CLK_PLLC4 237U
|
||||
/** @brief 32K input clock provided by PMIC */
|
||||
#define TEGRA234_CLK_CLK_32K 289U
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
|
||||
#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
|
||||
#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
|
||||
|
||||
/* special clients */
|
||||
#define TEGRA234_SID_INVALID 0x00
|
||||
#define TEGRA234_SID_PASSTHROUGH 0x7f
|
||||
|
||||
|
||||
/* NISO1 stream IDs */
|
||||
#define TEGRA234_SID_SDMMC4 0x02
|
||||
#define TEGRA234_SID_BPMP 0x10
|
||||
|
||||
/*
|
||||
* memory client IDs
|
||||
*/
|
||||
|
||||
/* sdmmcd memory read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
|
||||
/* sdmmcd memory write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
|
||||
/* BPMP read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
|
||||
/* BPMP write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
|
||||
/* BPMPDMA read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
|
||||
/* BPMPDMA write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
|
||||
|
||||
#endif
|
||||
|
|
@ -4,7 +4,15 @@
|
|||
#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
|
||||
#define DT_BINDINGS_RESET_TEGRA234_RESET_H
|
||||
|
||||
#define TEGRA234_RESET_SDMMC4 85
|
||||
#define TEGRA234_RESET_UARTA 100
|
||||
/**
|
||||
* @file
|
||||
* @defgroup bpmp_reset_ids Reset ID's
|
||||
* @brief Identifiers for Resets controllable by firmware
|
||||
* @{
|
||||
*/
|
||||
#define TEGRA234_RESET_SDMMC4 85U
|
||||
#define TEGRA234_RESET_UARTA 100U
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
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