ARM: dts: omap3: add minimal l4 bus layout with control module support
This patch creates an l4_core interconnect for OMAP3, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM node as the clock provider. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tero Kristo
Родитель
72b10ac00e
Коммит
b8845074cf
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@ -5,6 +5,7 @@ These bindings describe the OMAP SoCs L4 interconnect bus.
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Required properties:
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- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
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Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
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Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
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- ranges : contains the IO map range for the bus
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Examples:
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@ -17,7 +17,7 @@ Required properties:
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"ti,omap2-scm"
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"ti,omap3-prm"
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"ti,omap3-cm"
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"ti,omap3-scrm"
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"ti,omap3-scm"
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"ti,omap4-cm1"
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"ti,omap4-prm"
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"ti,omap4-cm2"
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@ -31,7 +31,7 @@
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status = "disabled";
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reg = <0x5c000000 0x30000>;
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interrupts = <67 68 69 70>;
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syscon = <&omap3_scm_general>;
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syscon = <&scm_conf>;
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ti,davinci-ctrl-reg-offset = <0x10000>;
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ti,davinci-ctrl-mod-reg-offset = <0>;
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ti,davinci-ctrl-ram-offset = <0x20000>;
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@ -7,7 +7,7 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&scrm_clocks {
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&scm_clocks {
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emac_ick: emac_ick {
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#clock-cells = <0>;
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compatible = "ti,am35xx-gate-clock";
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@ -87,6 +87,60 @@
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ranges;
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ti,hwmods = "l3_main";
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l4_core: l4@48000000 {
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compatible = "ti,omap3-l4-core", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x48000000 0x1000000>;
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scm: scm@2000 {
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compatible = "ti,omap3-scm", "simple-bus";
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reg = <0x2000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2000 0x2000>;
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omap3_pmx_core: pinmux@30 {
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compatible = "ti,omap3-padconf",
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"pinctrl-single";
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reg = <0x30 0x238>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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scm_conf: scm_conf@270 {
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compatible = "syscon";
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reg = <0x270 0x330>;
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#address-cells = <1>;
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#size-cells = <1>;
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scm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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scm_clockdomains: clockdomains {
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};
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omap3_pmx_wkup: pinmux@a00 {
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compatible = "ti,omap3-padconf",
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"pinctrl-single";
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reg = <0xa00 0x5c>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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};
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};
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aes: aes@480c5000 {
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compatible = "ti,omap3-aes";
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ti,hwmods = "aes";
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@ -121,19 +175,6 @@
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};
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};
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scrm: scrm@48002000 {
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compatible = "ti,omap3-scrm";
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reg = <0x48002000 0x2000>;
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scrm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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scrm_clockdomains: clockdomains {
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};
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};
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counter32k: counter@48320000 {
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compatible = "ti,omap-counter32k";
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reg = <0x48320000 0x20>;
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@ -159,37 +200,10 @@
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#dma-requests = <96>;
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};
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omap3_pmx_core: pinmux@48002030 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x48002030 0x0238>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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omap3_pmx_wkup: pinmux@48002a00 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x48002a00 0x5c>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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omap3_scm_general: tisyscon@48002270 {
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compatible = "syscon";
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reg = <0x48002270 0x2f0>;
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};
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pbias_regulator: pbias_regulator {
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compatible = "ti,pbias-omap";
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reg = <0x2b0 0x4>;
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syscon = <&omap3_scm_general>;
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syscon = <&scm_conf>;
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pbias_mmc_reg: pbias_mmc_omap2430 {
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regulator-name = "pbias_mmc_omap2430";
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regulator-min-microvolt = <1800000>;
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@ -79,13 +79,14 @@
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clock-div = <1>;
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};
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};
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&scrm_clocks {
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&scm_clocks {
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mcbsp5_mux_fck: mcbsp5_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&core_96m_fck>, <&mcbsp_clks>;
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ti,bit-shift = <4>;
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reg = <0x02d8>;
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reg = <0x68>;
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};
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mcbsp5_fck: mcbsp5_fck {
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@ -99,7 +100,7 @@
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compatible = "ti,composite-mux-clock";
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clocks = <&core_96m_fck>, <&mcbsp_clks>;
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ti,bit-shift = <2>;
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reg = <0x0274>;
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reg = <0x04>;
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};
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mcbsp1_fck: mcbsp1_fck {
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@ -113,7 +114,7 @@
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compatible = "ti,composite-mux-clock";
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clocks = <&per_96m_fck>, <&mcbsp_clks>;
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ti,bit-shift = <6>;
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reg = <0x0274>;
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reg = <0x04>;
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};
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mcbsp2_fck: mcbsp2_fck {
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@ -126,7 +127,7 @@
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&per_96m_fck>, <&mcbsp_clks>;
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reg = <0x02d8>;
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reg = <0x68>;
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};
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mcbsp3_fck: mcbsp3_fck {
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@ -140,7 +141,7 @@
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compatible = "ti,composite-mux-clock";
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clocks = <&per_96m_fck>, <&mcbsp_clks>;
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ti,bit-shift = <2>;
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reg = <0x02d8>;
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reg = <0x68>;
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};
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mcbsp4_fck: mcbsp4_fck {
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@ -670,7 +670,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = {
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{ .compatible = "ti,am3-scrm", .data = &ctrl_data },
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{ .compatible = "ti,am4-scrm", .data = &ctrl_data },
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{ .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
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{ .compatible = "ti,omap3-scrm", .data = &ctrl_data },
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{ .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
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{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
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{ }
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};
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