drm/amd/pp: Refine get_gpu_power for VI
pkgpwr is the average gpu power of 100ms. it is calculated by firmware in real time. 1. we can send smu message PPSMC_MSG_GetCurrPkgPwr to read currentpkgpwr directly. 2. On Fiji/tonga/bonaire/hawwii, without PPSMC_MSG_GetCurrPkgPwr support. Send PPSMC_MSG_PmStatusLogStart/Sample to let smu write currentpkgpwr to ixSMU_PM_STATUS_94. driver can read pkgpwr from ixSMU_PM_STATUS_94. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3359,30 +3359,33 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
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static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
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static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
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struct pp_gpu_power *query)
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struct pp_gpu_power *query)
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{
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{
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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int i;
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PPSMC_MSG_PmStatusLogStart),
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"Failed to start pm status log!",
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return -1);
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msleep_interruptible(20);
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if (!query)
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return -EINVAL;
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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PPSMC_MSG_PmStatusLogSample),
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"Failed to sample pm status log!",
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return -1);
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query->vddc_power = cgs_read_ind_register(hwmgr->device,
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memset(query, 0, sizeof *query);
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CGS_IND_REG__SMC,
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ixSMU_PM_STATUS_40);
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smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
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query->vddci_power = cgs_read_ind_register(hwmgr->device,
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query->average_gpu_power = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
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CGS_IND_REG__SMC,
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ixSMU_PM_STATUS_49);
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if (query->average_gpu_power != 0)
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query->max_gpu_power = cgs_read_ind_register(hwmgr->device,
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return 0;
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CGS_IND_REG__SMC,
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ixSMU_PM_STATUS_94);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
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query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
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CGS_IND_REG__SMC,
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ixSMU_PM_STATUS_94, 0);
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ixSMU_PM_STATUS_95);
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for (i = 0; i < 20; i++) {
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mdelay(1);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
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query->average_gpu_power = cgs_read_ind_register(hwmgr->device,
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CGS_IND_REG__SMC,
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ixSMU_PM_STATUS_94);
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if (query->average_gpu_power != 0)
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break;
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}
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return 0;
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return 0;
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}
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}
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@ -171,8 +171,10 @@ int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
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ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
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if (ret != 1)
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if (ret == 0xFE)
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pr_info("\n failed to send pre message %x ret is %d \n", msg, ret);
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pr_debug("last message was not supported\n");
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else if (ret != 1)
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pr_info("\n last message was failed ret is %d\n", ret);
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cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
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cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
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@ -180,7 +182,9 @@ int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
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ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
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if (ret != 1)
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if (ret == 0xFE)
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pr_debug("message %x was not supported\n", msg);
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else if (ret != 1)
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pr_info("\n failed to send message %x ret is %d \n", msg, ret);
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pr_info("\n failed to send message %x ret is %d \n", msg, ret);
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return 0;
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return 0;
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