usb: gadget: r8a66597-udc: add support for SUDMAC
SH7757 has a USB function with internal DMA controller (SUDMAC). This patch supports the SUDMAC. The SUDMAC is incompatible with general-purpose DMAC. So, it doesn't use dmaengine. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Yoshihiro Shimoda
Felipe Balbi
Родитель
12158f4280
Коммит
b8a56e17e1
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@ -18,13 +18,14 @@
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include "r8a66597-udc.h"
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#define DRIVER_VERSION "2009-08-18"
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#define DRIVER_VERSION "2011-09-26"
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static const char udc_name[] = "r8a66597_udc";
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static const char *r8a66597_ep_name[] = {
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@ -184,6 +185,54 @@ static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
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}
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}
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static void control_reg_sqset(struct r8a66597 *r8a66597, u16 pipenum)
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{
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unsigned long offset;
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pipe_stop(r8a66597, pipenum);
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if (pipenum == 0) {
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r8a66597_bset(r8a66597, SQSET, DCPCTR);
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} else if (pipenum < R8A66597_MAX_NUM_PIPE) {
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offset = get_pipectr_addr(pipenum);
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r8a66597_bset(r8a66597, SQSET, offset);
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} else {
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dev_err(r8a66597_to_dev(r8a66597),
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"unexpect pipe num(%d)\n", pipenum);
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}
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}
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static u16 control_reg_sqmon(struct r8a66597 *r8a66597, u16 pipenum)
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{
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unsigned long offset;
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if (pipenum == 0) {
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return r8a66597_read(r8a66597, DCPCTR) & SQMON;
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} else if (pipenum < R8A66597_MAX_NUM_PIPE) {
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offset = get_pipectr_addr(pipenum);
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return r8a66597_read(r8a66597, offset) & SQMON;
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} else {
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dev_err(r8a66597_to_dev(r8a66597),
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"unexpect pipe num(%d)\n", pipenum);
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}
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return 0;
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}
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static u16 save_usb_toggle(struct r8a66597 *r8a66597, u16 pipenum)
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{
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return control_reg_sqmon(r8a66597, pipenum);
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}
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static void restore_usb_toggle(struct r8a66597 *r8a66597, u16 pipenum,
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u16 toggle)
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{
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if (toggle)
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control_reg_sqset(r8a66597, pipenum);
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else
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control_reg_sqclr(r8a66597, pipenum);
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}
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static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
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{
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u16 tmp;
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@ -220,18 +269,51 @@ static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
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return MBW_16;
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}
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static void r8a66597_change_curpipe(struct r8a66597 *r8a66597, u16 pipenum,
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u16 isel, u16 fifosel)
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{
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u16 tmp, mask, loop;
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int i = 0;
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if (!pipenum) {
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mask = ISEL | CURPIPE;
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loop = isel;
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} else {
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mask = CURPIPE;
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loop = pipenum;
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}
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r8a66597_mdfy(r8a66597, loop, mask, fifosel);
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do {
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tmp = r8a66597_read(r8a66597, fifosel);
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if (i++ > 1000000) {
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dev_err(r8a66597_to_dev(r8a66597),
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"r8a66597: register%x, loop %x "
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"is timeout\n", fifosel, loop);
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break;
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}
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ndelay(1);
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} while ((tmp & mask) != loop);
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}
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static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
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{
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struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
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if (ep->use_dma)
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return;
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r8a66597_bclr(r8a66597, DREQE, ep->fifosel);
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r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
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ndelay(450);
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r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
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if (r8a66597_is_sudmac(r8a66597) && ep->use_dma)
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r8a66597_bclr(r8a66597, mbw_value(r8a66597), ep->fifosel);
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else
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r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
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if (ep->use_dma)
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r8a66597_bset(r8a66597, DREQE, ep->fifosel);
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}
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static int pipe_buffer_setting(struct r8a66597 *r8a66597,
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@ -336,9 +418,15 @@ static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
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ep->fifoaddr = CFIFO;
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ep->fifosel = CFIFOSEL;
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ep->fifoctr = CFIFOCTR;
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ep->fifotrn = 0;
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ep->pipectr = get_pipectr_addr(pipenum);
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if (is_bulk_pipe(pipenum) || is_isoc_pipe(pipenum)) {
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ep->pipetre = get_pipetre_addr(pipenum);
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ep->pipetrn = get_pipetrn_addr(pipenum);
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} else {
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ep->pipetre = 0;
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ep->pipetrn = 0;
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}
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ep->pipenum = pipenum;
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ep->ep.maxpacket = usb_endpoint_maxp(desc);
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r8a66597->pipenum2ep[pipenum] = ep;
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@ -498,6 +586,124 @@ static void start_ep0_write(struct r8a66597_ep *ep,
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}
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}
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static void disable_fifosel(struct r8a66597 *r8a66597, u16 pipenum,
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u16 fifosel)
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{
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u16 tmp;
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tmp = r8a66597_read(r8a66597, fifosel) & CURPIPE;
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if (tmp == pipenum)
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r8a66597_change_curpipe(r8a66597, 0, 0, fifosel);
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}
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static void change_bfre_mode(struct r8a66597 *r8a66597, u16 pipenum,
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int enable)
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{
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struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
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u16 tmp, toggle;
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/* check current BFRE bit */
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r8a66597_write(r8a66597, pipenum, PIPESEL);
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tmp = r8a66597_read(r8a66597, PIPECFG) & R8A66597_BFRE;
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if ((enable && tmp) || (!enable && !tmp))
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return;
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/* change BFRE bit */
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pipe_stop(r8a66597, pipenum);
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disable_fifosel(r8a66597, pipenum, CFIFOSEL);
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disable_fifosel(r8a66597, pipenum, D0FIFOSEL);
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disable_fifosel(r8a66597, pipenum, D1FIFOSEL);
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toggle = save_usb_toggle(r8a66597, pipenum);
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r8a66597_write(r8a66597, pipenum, PIPESEL);
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if (enable)
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r8a66597_bset(r8a66597, R8A66597_BFRE, PIPECFG);
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else
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r8a66597_bclr(r8a66597, R8A66597_BFRE, PIPECFG);
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/* initialize for internal BFRE flag */
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r8a66597_bset(r8a66597, ACLRM, ep->pipectr);
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r8a66597_bclr(r8a66597, ACLRM, ep->pipectr);
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restore_usb_toggle(r8a66597, pipenum, toggle);
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}
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static int sudmac_alloc_channel(struct r8a66597 *r8a66597,
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struct r8a66597_ep *ep,
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struct r8a66597_request *req)
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{
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struct r8a66597_dma *dma;
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if (!r8a66597_is_sudmac(r8a66597))
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return -ENODEV;
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/* Check transfer type */
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if (!is_bulk_pipe(ep->pipenum))
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return -EIO;
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if (r8a66597->dma.used)
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return -EBUSY;
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/* set SUDMAC parameters */
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dma = &r8a66597->dma;
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dma->used = 1;
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if (ep->desc->bEndpointAddress & USB_DIR_IN) {
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dma->dir = 1;
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} else {
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dma->dir = 0;
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change_bfre_mode(r8a66597, ep->pipenum, 1);
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}
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/* set r8a66597_ep paramters */
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ep->use_dma = 1;
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ep->dma = dma;
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ep->fifoaddr = D0FIFO;
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ep->fifosel = D0FIFOSEL;
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ep->fifoctr = D0FIFOCTR;
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/* dma mapping */
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req->req.dma = dma_map_single(r8a66597_to_dev(ep->r8a66597),
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req->req.buf, req->req.length,
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dma->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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return 0;
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}
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static void sudmac_free_channel(struct r8a66597 *r8a66597,
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struct r8a66597_ep *ep,
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struct r8a66597_request *req)
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{
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if (!r8a66597_is_sudmac(r8a66597))
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return;
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dma_unmap_single(r8a66597_to_dev(ep->r8a66597),
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req->req.dma, req->req.length,
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ep->dma->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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r8a66597_bclr(r8a66597, DREQE, ep->fifosel);
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r8a66597_change_curpipe(r8a66597, 0, 0, ep->fifosel);
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ep->dma->used = 0;
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ep->use_dma = 0;
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ep->fifoaddr = CFIFO;
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ep->fifosel = CFIFOSEL;
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ep->fifoctr = CFIFOCTR;
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}
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static void sudmac_start(struct r8a66597 *r8a66597, struct r8a66597_ep *ep,
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struct r8a66597_request *req)
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{
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BUG_ON(req->req.length == 0);
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r8a66597_sudmac_write(r8a66597, LBA_WAIT, CH0CFG);
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r8a66597_sudmac_write(r8a66597, req->req.dma, CH0BA);
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r8a66597_sudmac_write(r8a66597, req->req.length, CH0BBC);
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r8a66597_sudmac_write(r8a66597, CH0ENDE, DINTCTRL);
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r8a66597_sudmac_write(r8a66597, DEN, CH0DEN);
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}
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static void start_packet_write(struct r8a66597_ep *ep,
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struct r8a66597_request *req)
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{
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@ -508,11 +714,29 @@ static void start_packet_write(struct r8a66597_ep *ep,
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disable_irq_empty(r8a66597, ep->pipenum);
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pipe_start(r8a66597, ep->pipenum);
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tmp = r8a66597_read(r8a66597, ep->fifoctr);
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if (unlikely((tmp & FRDY) == 0))
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pipe_irq_enable(r8a66597, ep->pipenum);
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else
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irq_packet_write(ep, req);
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if (req->req.length == 0) {
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transfer_complete(ep, req, 0);
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} else {
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r8a66597_write(r8a66597, ~(1 << ep->pipenum), BRDYSTS);
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if (sudmac_alloc_channel(r8a66597, ep, req) < 0) {
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/* PIO mode */
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pipe_change(r8a66597, ep->pipenum);
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disable_irq_empty(r8a66597, ep->pipenum);
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pipe_start(r8a66597, ep->pipenum);
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tmp = r8a66597_read(r8a66597, ep->fifoctr);
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if (unlikely((tmp & FRDY) == 0))
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pipe_irq_enable(r8a66597, ep->pipenum);
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else
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irq_packet_write(ep, req);
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} else {
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/* DMA mode */
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pipe_change(r8a66597, ep->pipenum);
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disable_irq_nrdy(r8a66597, ep->pipenum);
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pipe_start(r8a66597, ep->pipenum);
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enable_irq_nrdy(r8a66597, ep->pipenum);
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sudmac_start(r8a66597, ep, req);
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}
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}
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}
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static void start_packet_read(struct r8a66597_ep *ep,
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@ -527,17 +751,26 @@ static void start_packet_read(struct r8a66597_ep *ep,
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pipe_start(r8a66597, pipenum);
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pipe_irq_enable(r8a66597, pipenum);
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} else {
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if (ep->use_dma) {
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r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
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pipe_change(r8a66597, pipenum);
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r8a66597_bset(r8a66597, TRENB, ep->fifosel);
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pipe_stop(r8a66597, pipenum);
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if (ep->pipetre) {
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enable_irq_nrdy(r8a66597, pipenum);
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r8a66597_write(r8a66597, TRCLR, ep->pipetre);
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r8a66597_write(r8a66597,
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(req->req.length + ep->ep.maxpacket - 1)
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/ ep->ep.maxpacket,
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ep->fifotrn);
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DIV_ROUND_UP(req->req.length, ep->ep.maxpacket),
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ep->pipetrn);
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r8a66597_bset(r8a66597, TRENB, ep->pipetre);
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}
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if (sudmac_alloc_channel(r8a66597, ep, req) < 0) {
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/* PIO mode */
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change_bfre_mode(r8a66597, ep->pipenum, 0);
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pipe_start(r8a66597, pipenum); /* trigger once */
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pipe_irq_enable(r8a66597, pipenum);
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} else {
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pipe_change(r8a66597, pipenum);
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sudmac_start(r8a66597, ep, req);
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pipe_start(r8a66597, pipenum); /* trigger once */
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}
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pipe_start(r8a66597, pipenum); /* trigger once */
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pipe_irq_enable(r8a66597, pipenum);
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}
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}
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@ -694,6 +927,9 @@ __acquires(r8a66597->lock)
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if (!list_empty(&ep->queue))
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restart = 1;
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if (ep->use_dma)
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sudmac_free_channel(ep->r8a66597, ep, req);
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spin_unlock(&ep->r8a66597->lock);
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req->req.complete(&ep->ep, &req->req);
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spin_lock(&ep->r8a66597->lock);
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@ -1170,6 +1406,65 @@ __acquires(r8a66597->lock)
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}
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}
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static void sudmac_finish(struct r8a66597 *r8a66597, struct r8a66597_ep *ep)
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{
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u16 pipenum;
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struct r8a66597_request *req;
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u32 len;
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int i = 0;
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pipenum = ep->pipenum;
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pipe_change(r8a66597, pipenum);
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while (!(r8a66597_read(r8a66597, ep->fifoctr) & FRDY)) {
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udelay(1);
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if (unlikely(i++ >= 10000)) { /* timeout = 10 msec */
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dev_err(r8a66597_to_dev(r8a66597),
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"%s: FRDY was not set (%d)\n",
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__func__, pipenum);
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return;
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}
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}
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r8a66597_bset(r8a66597, BCLR, ep->fifoctr);
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req = get_request_from_ep(ep);
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/* prepare parameters */
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len = r8a66597_sudmac_read(r8a66597, CH0CBC);
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req->req.actual += len;
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/* clear */
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r8a66597_sudmac_write(r8a66597, CH0STCLR, DSTSCLR);
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/* check transfer finish */
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if ((!req->req.zero && (req->req.actual == req->req.length))
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|| (len % ep->ep.maxpacket)) {
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if (ep->dma->dir) {
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disable_irq_ready(r8a66597, pipenum);
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enable_irq_empty(r8a66597, pipenum);
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} else {
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/* Clear the interrupt flag for next transfer */
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r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
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transfer_complete(ep, req, 0);
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}
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}
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}
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static void r8a66597_sudmac_irq(struct r8a66597 *r8a66597)
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{
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u32 irqsts;
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struct r8a66597_ep *ep;
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u16 pipenum;
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irqsts = r8a66597_sudmac_read(r8a66597, DINTSTS);
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if (irqsts & CH0ENDS) {
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r8a66597_sudmac_write(r8a66597, CH0ENDC, DINTSTSCLR);
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pipenum = (r8a66597_read(r8a66597, D0FIFOSEL) & CURPIPE);
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ep = r8a66597->pipenum2ep[pipenum];
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sudmac_finish(r8a66597, ep);
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}
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}
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static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
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{
|
||||
struct r8a66597 *r8a66597 = _r8a66597;
|
||||
|
|
@ -1180,6 +1475,9 @@ static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
|
|||
u16 savepipe;
|
||||
u16 mask0;
|
||||
|
||||
if (r8a66597_is_sudmac(r8a66597))
|
||||
r8a66597_sudmac_irq(r8a66597);
|
||||
|
||||
spin_lock(&r8a66597->lock);
|
||||
|
||||
intsts0 = r8a66597_read(r8a66597, INTSTS0);
|
||||
|
|
@ -1556,6 +1854,8 @@ static int __exit r8a66597_remove(struct platform_device *pdev)
|
|||
usb_del_gadget_udc(&r8a66597->gadget);
|
||||
del_timer_sync(&r8a66597->timer);
|
||||
iounmap(r8a66597->reg);
|
||||
if (r8a66597->pdata->sudmac)
|
||||
iounmap(r8a66597->sudmac_reg);
|
||||
free_irq(platform_get_irq(pdev, 0), r8a66597);
|
||||
r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
|
|
@ -1572,6 +1872,26 @@ static void nop_completion(struct usb_ep *ep, struct usb_request *r)
|
|||
{
|
||||
}
|
||||
|
||||
static int __init r8a66597_sudmac_ioremap(struct r8a66597 *r8a66597,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sudmac");
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "platform_get_resource error(sudmac).\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
r8a66597->sudmac_reg = ioremap(res->start, resource_size(res));
|
||||
if (r8a66597->sudmac_reg == NULL) {
|
||||
dev_err(&pdev->dev, "ioremap error(sudmac).\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init r8a66597_probe(struct platform_device *pdev)
|
||||
{
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
|
|
@ -1649,6 +1969,11 @@ static int __init r8a66597_probe(struct platform_device *pdev)
|
|||
clk_enable(r8a66597->clk);
|
||||
}
|
||||
#endif
|
||||
if (r8a66597->pdata->sudmac) {
|
||||
ret = r8a66597_sudmac_ioremap(r8a66597, pdev);
|
||||
if (ret < 0)
|
||||
goto clean_up2;
|
||||
}
|
||||
|
||||
disable_controller(r8a66597); /* make sure controller is disabled */
|
||||
|
||||
|
|
@ -1681,7 +2006,6 @@ static int __init r8a66597_probe(struct platform_device *pdev)
|
|||
r8a66597->ep[0].fifoaddr = CFIFO;
|
||||
r8a66597->ep[0].fifosel = CFIFOSEL;
|
||||
r8a66597->ep[0].fifoctr = CFIFOCTR;
|
||||
r8a66597->ep[0].fifotrn = 0;
|
||||
r8a66597->ep[0].pipectr = get_pipectr_addr(0);
|
||||
r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
|
||||
r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
|
||||
|
|
@ -1714,6 +2038,8 @@ clean_up2:
|
|||
#endif
|
||||
clean_up:
|
||||
if (r8a66597) {
|
||||
if (r8a66597->sudmac_reg)
|
||||
iounmap(r8a66597->sudmac_reg);
|
||||
if (r8a66597->ep0_req)
|
||||
r8a66597_free_request(&r8a66597->ep[0].ep,
|
||||
r8a66597->ep0_req);
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@
|
|||
((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
|
||||
(pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
|
||||
|
||||
#define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac)
|
||||
struct r8a66597_pipe_info {
|
||||
u16 pipe;
|
||||
u16 epnum;
|
||||
|
|
@ -60,6 +61,7 @@ struct r8a66597_request {
|
|||
struct r8a66597_ep {
|
||||
struct usb_ep ep;
|
||||
struct r8a66597 *r8a66597;
|
||||
struct r8a66597_dma *dma;
|
||||
|
||||
struct list_head queue;
|
||||
unsigned busy:1;
|
||||
|
|
@ -75,13 +77,20 @@ struct r8a66597_ep {
|
|||
unsigned char fifoaddr;
|
||||
unsigned char fifosel;
|
||||
unsigned char fifoctr;
|
||||
unsigned char fifotrn;
|
||||
unsigned char pipectr;
|
||||
unsigned char pipetre;
|
||||
unsigned char pipetrn;
|
||||
};
|
||||
|
||||
struct r8a66597_dma {
|
||||
unsigned used:1;
|
||||
unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */
|
||||
};
|
||||
|
||||
struct r8a66597 {
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
void __iomem *sudmac_reg;
|
||||
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
struct clk *clk;
|
||||
|
|
@ -94,6 +103,7 @@ struct r8a66597 {
|
|||
struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
|
||||
struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
|
||||
struct r8a66597_ep *epaddr2ep[16];
|
||||
struct r8a66597_dma dma;
|
||||
|
||||
struct timer_list timer;
|
||||
struct usb_request *ep0_req; /* for internal request */
|
||||
|
|
@ -251,7 +261,21 @@ static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
|
|||
return clock;
|
||||
}
|
||||
|
||||
static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597,
|
||||
unsigned long offset)
|
||||
{
|
||||
return ioread32(r8a66597->sudmac_reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val,
|
||||
unsigned long offset)
|
||||
{
|
||||
iowrite32(val, r8a66597->sudmac_reg + offset);
|
||||
}
|
||||
|
||||
#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
|
||||
#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
|
||||
#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
|
||||
|
||||
#define enable_irq_ready(r8a66597, pipenum) \
|
||||
enable_pipe_irq(r8a66597, pipenum, BRDYENB)
|
||||
|
|
|
|||
|
|
@ -48,6 +48,9 @@ struct r8a66597_platdata {
|
|||
|
||||
/* (external controller only) set one = WR0_N shorted to WR1_N */
|
||||
unsigned wr0_shorted_to_wr1:1;
|
||||
|
||||
/* set one = using SUDMAC */
|
||||
unsigned sudmac:1;
|
||||
};
|
||||
|
||||
/* Register definitions */
|
||||
|
|
@ -417,5 +420,62 @@ struct r8a66597_platdata {
|
|||
#define USBSPD 0x00C0
|
||||
#define RTPORT 0x0001
|
||||
|
||||
/* SUDMAC registers */
|
||||
#define CH0CFG 0x00
|
||||
#define CH1CFG 0x04
|
||||
#define CH0BA 0x10
|
||||
#define CH1BA 0x14
|
||||
#define CH0BBC 0x18
|
||||
#define CH1BBC 0x1C
|
||||
#define CH0CA 0x20
|
||||
#define CH1CA 0x24
|
||||
#define CH0CBC 0x28
|
||||
#define CH1CBC 0x2C
|
||||
#define CH0DEN 0x30
|
||||
#define CH1DEN 0x34
|
||||
#define DSTSCLR 0x38
|
||||
#define DBUFCTRL 0x3C
|
||||
#define DINTCTRL 0x40
|
||||
#define DINTSTS 0x44
|
||||
#define DINTSTSCLR 0x48
|
||||
#define CH0SHCTRL 0x50
|
||||
#define CH1SHCTRL 0x54
|
||||
|
||||
/* SUDMAC Configuration Registers */
|
||||
#define SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
|
||||
#define RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */
|
||||
#define LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
|
||||
|
||||
/* DMA Enable Registers */
|
||||
#define DEN 0x0001 /* b1: DMA Transfer Enable */
|
||||
|
||||
/* DMA Status Clear Register */
|
||||
#define CH1STCLR 0x0002 /* b2: Ch1 DMA Status Clear */
|
||||
#define CH0STCLR 0x0001 /* b1: Ch0 DMA Status Clear */
|
||||
|
||||
/* DMA Buffer Control Register */
|
||||
#define CH1BUFW 0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */
|
||||
#define CH0BUFW 0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */
|
||||
#define CH1BUFS 0x0002 /* b2: Ch1 DMA Buffer Data Status */
|
||||
#define CH0BUFS 0x0001 /* b1: Ch0 DMA Buffer Data Status */
|
||||
|
||||
/* DMA Interrupt Control Register */
|
||||
#define CH1ERRE 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */
|
||||
#define CH0ERRE 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */
|
||||
#define CH1ENDE 0x0002 /* b2: Ch1 DMA Transfer End Int Enable */
|
||||
#define CH0ENDE 0x0001 /* b1: Ch0 DMA Transfer End Int Enable */
|
||||
|
||||
/* DMA Interrupt Status Register */
|
||||
#define CH1ERRS 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Status */
|
||||
#define CH0ERRS 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Status */
|
||||
#define CH1ENDS 0x0002 /* b2: Ch1 DMA Transfer End Int Status */
|
||||
#define CH0ENDS 0x0001 /* b1: Ch0 DMA Transfer End Int Status */
|
||||
|
||||
/* DMA Interrupt Status Clear Register */
|
||||
#define CH1ERRC 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Stat Clear */
|
||||
#define CH0ERRC 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Stat Clear */
|
||||
#define CH1ENDC 0x0002 /* b2: Ch1 DMA Transfer End Int Stat Clear */
|
||||
#define CH0ENDC 0x0001 /* b1: Ch0 DMA Transfer End Int Stat Clear */
|
||||
|
||||
#endif /* __LINUX_USB_R8A66597_H */
|
||||
|
||||
|
|
|
|||
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