dt-bindings: i3c: Describe Silvaco master binding
Silvaco provide a dual-role I3C master. Description is rather simple: it needs a register mapping, three clocks and an interrupt. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210121101808.14654-5-miquel.raynal@bootlin.com
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Silvaco I3C master
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maintainers:
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- Conor Culhane <conor.culhane@silvaco.com>
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allOf:
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- $ref: "i3c.yaml#"
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properties:
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compatible:
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const: silvaco,i3c-master-v1
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: system clock
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- description: bus clock
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- description: other (slower) events clock
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clock-names:
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items:
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- const: pclk
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- const: fast_clk
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- const: slow_clk
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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additionalProperties: true
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examples:
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- |
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i3c-master@a0000000 {
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compatible = "silvaco,i3c-master";
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clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
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clock-names = "pclk", "fast_clk", "slow_clk";
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interrupt-parent = <&gic>;
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interrupts = <0 89 4>;
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reg = <0xa0000000 0x1000>;
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#address-cells = <3>;
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#size-cells = <0>;
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};
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