Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Mainly Intel regression fixes and quirks, along with a simple one liner to fix rendernodes ioctl access (off by default, but testers want to test it)" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm: allow DRM_IOCTL_VERSION on render-nodes drm/i915: Fix the PPT fdi lane bifurcate state handling on ivb drm/i915: No LVDS hardware on Intel D410PT and D425KT drm/i915/dp: workaround BIOS eDP bpp clamping issue drm/i915: Add HSW CRT output readout support drm/i915: Add support for pipe_bpp readout
This commit is contained in:
Linus Torvalds
Коммит
b8cab70665
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@ -61,7 +61,7 @@ static int drm_version(struct drm_device *dev, void *data,
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/** Ioctl table */
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static const struct drm_ioctl_desc drm_ioctls[] = {
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DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, DRM_UNLOCKED|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, 0),
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DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, 0),
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DRM_IOCTL_DEF(DRM_IOCTL_IRQ_BUSID, drm_irq_by_busid, DRM_MASTER|DRM_ROOT_ONLY),
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@ -83,8 +83,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
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return true;
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}
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static void intel_crt_get_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crt *crt = intel_encoder_to_crt(encoder);
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@ -102,7 +101,27 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
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else
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flags |= DRM_MODE_FLAG_NVSYNC;
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pipe_config->adjusted_mode.flags |= flags;
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return flags;
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}
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static void intel_crt_get_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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{
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struct drm_device *dev = encoder->base.dev;
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pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
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}
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static void hsw_crt_get_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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{
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intel_ddi_get_config(encoder, pipe_config);
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pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
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DRM_MODE_FLAG_NHSYNC |
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DRM_MODE_FLAG_PVSYNC |
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DRM_MODE_FLAG_NVSYNC);
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pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
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}
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/* Note: The caller is required to filter out dpms modes not supported by the
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@ -799,7 +818,10 @@ void intel_crt_init(struct drm_device *dev)
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crt->base.mode_set = intel_crt_mode_set;
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crt->base.disable = intel_disable_crt;
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crt->base.enable = intel_enable_crt;
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crt->base.get_config = intel_crt_get_config;
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if (IS_HASWELL(dev))
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crt->base.get_config = hsw_crt_get_config;
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else
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crt->base.get_config = intel_crt_get_config;
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if (I915_HAS_HOTPLUG(dev))
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crt->base.hpd_pin = HPD_CRT;
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if (HAS_DDI(dev))
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@ -1249,8 +1249,8 @@ static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
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intel_dp_check_link_status(intel_dp);
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}
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static void intel_ddi_get_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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void intel_ddi_get_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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@ -1268,6 +1268,23 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
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flags |= DRM_MODE_FLAG_NVSYNC;
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pipe_config->adjusted_mode.flags |= flags;
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switch (temp & TRANS_DDI_BPC_MASK) {
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case TRANS_DDI_BPC_6:
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pipe_config->pipe_bpp = 18;
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break;
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case TRANS_DDI_BPC_8:
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pipe_config->pipe_bpp = 24;
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break;
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case TRANS_DDI_BPC_10:
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pipe_config->pipe_bpp = 30;
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break;
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case TRANS_DDI_BPC_12:
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pipe_config->pipe_bpp = 36;
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break;
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default:
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break;
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}
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}
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static void intel_ddi_destroy(struct drm_encoder *encoder)
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@ -2327,9 +2327,10 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
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FDI_FE_ERRC_ENABLE);
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}
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static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
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static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
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{
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return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
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return crtc->base.enabled && crtc->active &&
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crtc->config.has_pch_encoder;
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}
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static void ivb_modeset_global_resources(struct drm_device *dev)
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@ -2979,6 +2980,48 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
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I915_READ(VSYNCSHIFT(cpu_transcoder)));
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}
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static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t temp;
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temp = I915_READ(SOUTH_CHICKEN1);
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if (temp & FDI_BC_BIFURCATION_SELECT)
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return;
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WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
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WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
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temp |= FDI_BC_BIFURCATION_SELECT;
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DRM_DEBUG_KMS("enabling fdi C rx\n");
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I915_WRITE(SOUTH_CHICKEN1, temp);
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POSTING_READ(SOUTH_CHICKEN1);
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}
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static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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switch (intel_crtc->pipe) {
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case PIPE_A:
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break;
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case PIPE_B:
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if (intel_crtc->config.fdi_lanes > 2)
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WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
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else
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cpt_enable_fdi_bc_bifurcation(dev);
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break;
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case PIPE_C:
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cpt_enable_fdi_bc_bifurcation(dev);
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break;
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default:
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BUG();
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}
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}
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/*
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* Enable PCH resources required for PCH ports:
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* - PCH PLLs
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@ -2997,6 +3040,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
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assert_pch_transcoder_disabled(dev_priv, pipe);
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if (IS_IVYBRIDGE(dev))
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ivybridge_update_fdi_bc_bifurcation(intel_crtc);
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/* Write the TU size bits before fdi link training, so that error
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* detection works. */
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I915_WRITE(FDI_RX_TUSIZE1(pipe),
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@ -4983,6 +5029,22 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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if (!(tmp & PIPECONF_ENABLE))
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return false;
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if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
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switch (tmp & PIPECONF_BPC_MASK) {
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case PIPECONF_6BPC:
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pipe_config->pipe_bpp = 18;
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break;
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case PIPECONF_8BPC:
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pipe_config->pipe_bpp = 24;
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break;
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case PIPECONF_10BPC:
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pipe_config->pipe_bpp = 30;
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break;
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default:
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break;
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}
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}
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intel_get_pipe_timings(crtc, pipe_config);
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i9xx_get_pfit_config(crtc, pipe_config);
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@ -5576,48 +5638,6 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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return true;
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}
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static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t temp;
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temp = I915_READ(SOUTH_CHICKEN1);
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if (temp & FDI_BC_BIFURCATION_SELECT)
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return;
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WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
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WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
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temp |= FDI_BC_BIFURCATION_SELECT;
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DRM_DEBUG_KMS("enabling fdi C rx\n");
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I915_WRITE(SOUTH_CHICKEN1, temp);
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POSTING_READ(SOUTH_CHICKEN1);
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}
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static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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switch (intel_crtc->pipe) {
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case PIPE_A:
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break;
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case PIPE_B:
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if (intel_crtc->config.fdi_lanes > 2)
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WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
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else
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cpt_enable_fdi_bc_bifurcation(dev);
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break;
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case PIPE_C:
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cpt_enable_fdi_bc_bifurcation(dev);
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break;
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default:
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BUG();
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}
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}
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int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
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{
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/*
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@ -5811,9 +5831,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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&intel_crtc->config.fdi_m_n);
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}
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if (IS_IVYBRIDGE(dev))
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ivybridge_update_fdi_bc_bifurcation(intel_crtc);
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ironlake_set_pipeconf(crtc);
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/* Set up the display plane register */
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@ -5881,6 +5898,23 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
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if (!(tmp & PIPECONF_ENABLE))
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return false;
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switch (tmp & PIPECONF_BPC_MASK) {
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case PIPECONF_6BPC:
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pipe_config->pipe_bpp = 18;
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break;
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case PIPECONF_8BPC:
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pipe_config->pipe_bpp = 24;
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break;
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case PIPECONF_10BPC:
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pipe_config->pipe_bpp = 30;
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break;
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case PIPECONF_12BPC:
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pipe_config->pipe_bpp = 36;
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break;
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default:
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break;
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}
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if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
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struct intel_shared_dpll *pll;
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@ -8612,6 +8646,9 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
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PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
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if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
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PIPE_CONF_CHECK_I(pipe_bpp);
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#undef PIPE_CONF_CHECK_X
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#undef PIPE_CONF_CHECK_I
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#undef PIPE_CONF_CHECK_FLAGS
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@ -1401,6 +1401,26 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
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else
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pipe_config->port_clock = 270000;
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}
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if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
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pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
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/*
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* This is a big fat ugly hack.
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*
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* Some machines in UEFI boot mode provide us a VBT that has 18
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* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
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* unknown we fail to light up. Yet the same BIOS boots up with
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* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
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* max, not what it tells us to use.
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*
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* Note: This will still be broken if the eDP panel is not lit
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* up by the BIOS, and thus we can't get the mode at module
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* load.
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*/
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DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
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pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
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dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
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}
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}
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static bool is_edp_psr(struct intel_dp *intel_dp)
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@ -765,6 +765,8 @@ extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
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extern bool
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intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
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extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
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extern void intel_ddi_get_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config);
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extern void intel_display_handle_reset(struct drm_device *dev);
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extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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@ -698,6 +698,22 @@ static const struct dmi_system_id intel_no_lvds[] = {
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DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
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},
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},
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{
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.callback = intel_no_lvds_dmi_callback,
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.ident = "Intel D410PT",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
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DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
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},
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},
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{
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.callback = intel_no_lvds_dmi_callback,
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.ident = "Intel D425KT",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
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DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
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},
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},
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{
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.callback = intel_no_lvds_dmi_callback,
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.ident = "Intel D510MO",
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