Merge remote-tracking branches 'asoc/topic/inntel', 'asoc/topic/input', 'asoc/topic/max98504' and 'asoc/topic/nau8825' into asoc-next
This commit is contained in:
Mark Brown
Коммит
b8f04c1943
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@ -37,6 +37,8 @@ static void arizona_haptics_work(struct work_struct *work)
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struct arizona_haptics,
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work);
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struct arizona *arizona = haptics->arizona;
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struct snd_soc_component *component =
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snd_soc_dapm_to_component(arizona->dapm);
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int ret;
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if (!haptics->arizona->dapm) {
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@ -66,7 +68,7 @@ static void arizona_haptics_work(struct work_struct *work)
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return;
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}
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ret = snd_soc_dapm_enable_pin(arizona->dapm, "HAPTICS");
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ret = snd_soc_component_enable_pin(component, "HAPTICS");
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if (ret != 0) {
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dev_err(arizona->dev, "Failed to start HAPTICS: %d\n",
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ret);
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@ -81,7 +83,7 @@ static void arizona_haptics_work(struct work_struct *work)
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}
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} else {
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/* This disable sequence will be a noop if already enabled */
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ret = snd_soc_dapm_disable_pin(arizona->dapm, "HAPTICS");
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ret = snd_soc_component_disable_pin(component, "HAPTICS");
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if (ret != 0) {
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dev_err(arizona->dev, "Failed to disable HAPTICS: %d\n",
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ret);
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@ -140,11 +142,14 @@ static int arizona_haptics_play(struct input_dev *input, void *data,
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static void arizona_haptics_close(struct input_dev *input)
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{
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struct arizona_haptics *haptics = input_get_drvdata(input);
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struct snd_soc_component *component;
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cancel_work_sync(&haptics->work);
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if (haptics->arizona->dapm)
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snd_soc_dapm_disable_pin(haptics->arizona->dapm, "HAPTICS");
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if (haptics->arizona->dapm) {
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component = snd_soc_dapm_to_component(haptics->arizona->dapm);
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snd_soc_component_disable_pin(component, "HAPTICS");
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}
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}
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static int arizona_haptics_probe(struct platform_device *pdev)
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@ -85,6 +85,7 @@ config SND_SOC_ALL_CODECS
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select SND_SOC_MAX98095 if I2C
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select SND_SOC_MAX98357A if GPIOLIB
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select SND_SOC_MAX98371 if I2C
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select SND_SOC_MAX98504 if I2C
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select SND_SOC_MAX9867 if I2C
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select SND_SOC_MAX98925 if I2C
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select SND_SOC_MAX98926 if I2C
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@ -43,6 +43,8 @@
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#define GAIN_AUGMENT 22500
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#define SIDETONE_BASE 207000
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/* the maximum frequency of CLK_ADC and CLK_DAC */
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#define CLK_DA_AD_MAX 6144000
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static int nau8825_configure_sysclk(struct nau8825 *nau8825,
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int clk_id, unsigned int freq);
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@ -95,6 +97,27 @@ static const struct nau8825_fll_attr fll_pre_scalar[] = {
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{ 8, 0x3 },
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};
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/* over sampling rate */
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struct nau8825_osr_attr {
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unsigned int osr;
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unsigned int clk_src;
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};
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static const struct nau8825_osr_attr osr_dac_sel[] = {
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{ 64, 2 }, /* OSR 64, SRC 1/4 */
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{ 256, 0 }, /* OSR 256, SRC 1 */
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{ 128, 1 }, /* OSR 128, SRC 1/2 */
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{ 0, 0 },
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{ 32, 3 }, /* OSR 32, SRC 1/8 */
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};
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static const struct nau8825_osr_attr osr_adc_sel[] = {
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{ 32, 3 }, /* OSR 32, SRC 1/8 */
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{ 64, 2 }, /* OSR 64, SRC 1/4 */
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{ 128, 1 }, /* OSR 128, SRC 1/2 */
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{ 256, 0 }, /* OSR 256, SRC 1 */
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};
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static const struct reg_default nau8825_reg_defaults[] = {
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{ NAU8825_REG_ENA_CTRL, 0x00ff },
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{ NAU8825_REG_IIC_ADDR_SET, 0x0 },
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@ -1179,15 +1202,64 @@ static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
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{"HPOR", NULL, "Class G"},
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};
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static int nau8825_clock_check(struct nau8825 *nau8825,
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int stream, int rate, int osr)
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{
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int osrate;
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (osr >= ARRAY_SIZE(osr_dac_sel))
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return -EINVAL;
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osrate = osr_dac_sel[osr].osr;
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} else {
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if (osr >= ARRAY_SIZE(osr_adc_sel))
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return -EINVAL;
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osrate = osr_adc_sel[osr].osr;
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}
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if (!osrate || rate * osr > CLK_DA_AD_MAX) {
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dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
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return -EINVAL;
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}
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return 0;
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}
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static int nau8825_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
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unsigned int val_len = 0;
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unsigned int val_len = 0, osr;
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nau8825_sema_acquire(nau8825, 2 * HZ);
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nau8825_sema_acquire(nau8825, 3 * HZ);
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/* CLK_DAC or CLK_ADC = OSR * FS
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* DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
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* multiplied by the audio sample rate (Fs). Note that the OSR and Fs
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* values must be selected such that the maximum frequency is less
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* than 6.144 MHz.
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*/
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr);
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osr &= NAU8825_DAC_OVERSAMPLE_MASK;
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if (nau8825_clock_check(nau8825, substream->stream,
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params_rate(params), osr))
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return -EINVAL;
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regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_DAC_SRC_MASK,
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osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT);
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} else {
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regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr);
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osr &= NAU8825_ADC_SYNC_DOWN_MASK;
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if (nau8825_clock_check(nau8825, substream->stream,
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params_rate(params), osr))
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return -EINVAL;
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regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_ADC_SRC_MASK,
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osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT);
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}
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switch (params_width(params)) {
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case 16:
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@ -1221,7 +1293,7 @@ static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
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unsigned int ctrl1_val = 0, ctrl2_val = 0;
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nau8825_sema_acquire(nau8825, 2 * HZ);
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nau8825_sema_acquire(nau8825, 3 * HZ);
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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@ -1774,9 +1846,10 @@ static void nau8825_init_regs(struct nau8825 *nau8825)
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* (audible hiss). Set it to something better.
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*/
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regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
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NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128);
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NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
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NAU8825_ADC_SYNC_DOWN_64);
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regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
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NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128);
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NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
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/* Disable DACR/L power */
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regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
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NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
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@ -1811,6 +1884,9 @@ static void nau8825_init_regs(struct nau8825 *nau8825)
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NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
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regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
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NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
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/* Disable short Frame Sync detection logic */
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regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
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NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
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}
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static const struct regmap_config nau8825_regmap_config = {
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@ -1919,8 +1995,10 @@ static void nau8825_fll_apply(struct nau8825 *nau8825,
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regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
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NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
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/* Make DSP operate at high speed for better performance. */
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
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NAU8825_FLL_RATIO_MASK, fll_param->ratio);
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NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
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fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
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/* FLL 16-bit fractional input */
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regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
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/* FLL 10-bit integer input */
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@ -1936,19 +2014,22 @@ static void nau8825_fll_apply(struct nau8825 *nau8825,
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regmap_update_bits(nau8825->regmap,
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NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
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if (fll_param->fll_frac) {
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/* set FLL loop filter enable and cutoff frequency at 500Khz */
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
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NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
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NAU8825_FLL_FTR_SW_MASK,
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NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
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NAU8825_FLL_FTR_SW_FILTER);
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
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NAU8825_SDM_EN, NAU8825_SDM_EN);
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NAU8825_SDM_EN | NAU8825_CUTOFF500,
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NAU8825_SDM_EN | NAU8825_CUTOFF500);
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} else {
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/* disable FLL loop filter and cutoff frequency */
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
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NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
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NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
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regmap_update_bits(nau8825->regmap,
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NAU8825_REG_FLL6, NAU8825_SDM_EN, 0);
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
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NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
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}
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}
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@ -2014,6 +2095,9 @@ static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
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NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
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regmap_update_bits(regmap, NAU8825_REG_FLL6,
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NAU8825_DCO_EN, 0);
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/* Make DSP operate as default setting for power saving. */
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regmap_update_bits(regmap, NAU8825_REG_FLL1,
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NAU8825_ICTRL_LATCH_MASK, 0);
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}
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static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
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@ -2038,7 +2122,7 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
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* fered by cross talk process, the driver make the playback
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* preparation halted until cross talk process finish.
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*/
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nau8825_sema_acquire(nau8825, 2 * HZ);
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nau8825_sema_acquire(nau8825, 3 * HZ);
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nau8825_configure_mclk_as_sysclk(regmap);
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/* MCLK not changed by clock tree */
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regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
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@ -2057,10 +2141,13 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
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NAU8825_DCO_EN, NAU8825_DCO_EN);
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regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
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/* Decrease the VCO frequency for power saving */
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/* Decrease the VCO frequency and make DSP operate
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* as default setting for power saving.
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*/
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regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_MCLK_SRC_MASK, 0xf);
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regmap_update_bits(regmap, NAU8825_REG_FLL1,
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NAU8825_ICTRL_LATCH_MASK |
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NAU8825_FLL_RATIO_MASK, 0x10);
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regmap_update_bits(regmap, NAU8825_REG_FLL6,
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NAU8825_SDM_EN, NAU8825_SDM_EN);
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@ -2083,9 +2170,14 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
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* fered by cross talk process, the driver make the playback
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* preparation halted until cross talk process finish.
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*/
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nau8825_sema_acquire(nau8825, 2 * HZ);
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nau8825_sema_acquire(nau8825, 3 * HZ);
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/* Higher FLL reference input frequency can only set lower
|
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* gain error, such as 0000 for input reference from MCLK
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* 12.288Mhz.
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*/
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regmap_update_bits(regmap, NAU8825_REG_FLL3,
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NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK);
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NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
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NAU8825_FLL_CLK_SRC_MCLK | 0);
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/* Release the semaphone. */
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nau8825_sema_release(nau8825);
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|
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@ -2100,9 +2192,17 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
|
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* fered by cross talk process, the driver make the playback
|
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* preparation halted until cross talk process finish.
|
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*/
|
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nau8825_sema_acquire(nau8825, 2 * HZ);
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nau8825_sema_acquire(nau8825, 3 * HZ);
|
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/* If FLL reference input is from low frequency source,
|
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* higher error gain can apply such as 0xf which has
|
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* the most sensitive gain error correction threshold,
|
||||
* Therefore, FLL has the most accurate DCO to
|
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* target frequency.
|
||||
*/
|
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regmap_update_bits(regmap, NAU8825_REG_FLL3,
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NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK);
|
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NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
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NAU8825_FLL_CLK_SRC_BLK |
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(0xf << NAU8825_GAIN_ERR_SFT));
|
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/* Release the semaphone. */
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nau8825_sema_release(nau8825);
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||||
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@ -2118,9 +2218,17 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
|
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* fered by cross talk process, the driver make the playback
|
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* preparation halted until cross talk process finish.
|
||||
*/
|
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nau8825_sema_acquire(nau8825, 2 * HZ);
|
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nau8825_sema_acquire(nau8825, 3 * HZ);
|
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/* If FLL reference input is from low frequency source,
|
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* higher error gain can apply such as 0xf which has
|
||||
* the most sensitive gain error correction threshold,
|
||||
* Therefore, FLL has the most accurate DCO to
|
||||
* target frequency.
|
||||
*/
|
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regmap_update_bits(regmap, NAU8825_REG_FLL3,
|
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NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS);
|
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NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
|
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NAU8825_FLL_CLK_SRC_FS |
|
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(0xf << NAU8825_GAIN_ERR_SFT));
|
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/* Release the semaphone. */
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nau8825_sema_release(nau8825);
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|
||||
|
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@ -115,12 +115,20 @@
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#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT)
|
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#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT)
|
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#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT)
|
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#define NAU8825_CLK_ADC_SRC_SFT 6
|
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#define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT)
|
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#define NAU8825_CLK_DAC_SRC_SFT 4
|
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#define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT)
|
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#define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0)
|
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|
||||
/* FLL1 (0x04) */
|
||||
#define NAU8825_ICTRL_LATCH_SFT 10
|
||||
#define NAU8825_ICTRL_LATCH_MASK (0x7 << NAU8825_ICTRL_LATCH_SFT)
|
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#define NAU8825_FLL_RATIO_MASK (0x7f << 0)
|
||||
|
||||
/* FLL3 (0x06) */
|
||||
#define NAU8825_GAIN_ERR_SFT 12
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#define NAU8825_GAIN_ERR_MASK (0xf << NAU8825_GAIN_ERR_SFT)
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#define NAU8825_FLL_INTEGER_MASK (0x3ff << 0)
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#define NAU8825_FLL_CLK_SRC_SFT 10
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#define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT)
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@ -144,6 +152,7 @@
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/* FLL6 (0x9) */
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#define NAU8825_DCO_EN (0x1 << 15)
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#define NAU8825_SDM_EN (0x1 << 14)
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#define NAU8825_CUTOFF500 (0x1 << 13)
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/* HSD_CTRL (0xc) */
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#define NAU8825_HSD_AUTO_MODE (1 << 6)
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@ -246,6 +255,11 @@
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#define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT)
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#define NAU8825_I2S_BLK_DIV_MASK 0x7
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/* LEFT_TIME_SLOT (0x1e) */
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#define NAU8825_FS_ERR_CMP_SEL_SFT 14
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#define NAU8825_FS_ERR_CMP_SEL_MASK (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT)
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#define NAU8825_DIS_FS_SHORT_DET (1 << 13)
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/* BIQ_CTRL (0x20) */
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#define NAU8825_BIQ_WRT_SFT 4
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#define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT)
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@ -255,6 +269,8 @@
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#define NAU8825_BIQ_PATH_DAC (1 << NAU8825_BIQ_PATH_SFT)
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/* ADC_RATE (0x2b) */
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#define NAU8825_ADC_SINC4_SFT 4
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#define NAU8825_ADC_SINC4_EN (1 << NAU8825_ADC_SINC4_SFT)
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#define NAU8825_ADC_SYNC_DOWN_SFT 0
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#define NAU8825_ADC_SYNC_DOWN_MASK 0x3
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#define NAU8825_ADC_SYNC_DOWN_32 0
|
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