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Memory controller drivers for v5.18 

1. Minor improvements: Mediatek SMI, Freescale/NXP IFC, Tegra20 and
    Tegra30.
 2. Convert Freescale/NXP IFC bindings to dtschema.
 3. Convert LPDDR bindings to dtschema.
 4. Adjust revision ID property in LPDDR2 bindings to match LPDDR3
    bindings.
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Merge tag 'memory-controller-drv-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.18

1. Minor improvements: Mediatek SMI, Freescale/NXP IFC, Tegra20 and
   Tegra30.
2. Convert Freescale/NXP IFC bindings to dtschema.
3. Convert LPDDR bindings to dtschema.
4. Adjust revision ID property in LPDDR2 bindings to match LPDDR3
   bindings.

* tag 'memory-controller-drv-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: Update of_memory lpddr2 revision-id binding
  dt-bindings: memory: lpddr2: Adjust revision ID property to match lpddr3
  memory: of: parse max-freq property
  dt-bindings: memory: lpddr3: deprecate passing timings frequency as unit address
  dt-bindings: memory: lpddr3: deprecate manufacturer ID
  dt-bindings: memory: lpddr3: adjust IO width to spec
  dt-bindings: memory: lpddr3: convert to dtschema
  dt-bindings: memory: lpddr3-timings: convert to dtschema
  dt-bindings: memory: lpddr2-timings: convert to dtschema
  memory: brcmstb_dpfe: fix typo in a comment
  memory: fsl_ifc: populate child devices without relying on simple-bus
  dt-bindings: memory: fsl: convert ifc binding to yaml schema
  memory: mtk-smi: Use ARRAY_SIZE to define MTK_SMI_CLK_NR_MAX

Link: https://lore.kernel.org/r/20220228164313.52931-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-03-01 10:47:13 +01:00
Родитель 254a1864e4 a06bf59d07
Коммит b903f9c55e
14 изменённых файлов: 714 добавлений и 318 удалений
Показать статистику Скачать Patch файл Скачать Diff файл Показать все файлы Свернуть все файлы

135
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml Normal file
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@ -0,0 +1,135 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
const: jedec,lpddr2-timings
max-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
min-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Minimum DDR clock frequency for the speed-bin, in Hz.
tCKESR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in pico seconds.
tDQSCK-max:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
DQS output data access time from CK_t/CK_c in pico seconds.
tDQSCK-max-derated:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
seconds.
tFAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Four-bank activate window in pico seconds.
tRAS-max-ns:
description: |
Row active time in nano seconds.
tRAS-min:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row active time in pico seconds.
tRCD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RAS-to-CAS delay in pico seconds.
tRPab:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (all banks) in pico seconds.
tRRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Active bank A to active bank B in pico seconds.
tRTP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal READ to PRECHARGE command delay in pico seconds.
tWR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
WRITE recovery time in pico seconds.
tWTR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal WRITE-to-READ command delay in pico seconds.
tXP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Exit power-down to next valid command delay in pico seconds.
tZQCL:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Long calibration time in pico seconds.
tZQCS:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Short calibration time in pico seconds.
tZQinit:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Initialization calibration time in pico seconds.
required:
- compatible
- min-freq
- max-freq
additionalProperties: false
examples:
- |
timings {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tRAS-max-ns = <70000>;
tRAS-min = <42000>;
tRPab = <21000>;
tRCD = <18000>;
tRRD = <10000>;
tRTP = <7500>;
tWR = <15000>;
tWTR = <7500>;
tXP = <7500>;
tZQCL = <360000>;
tZQCS = <90000>;
tZQinit = <1000000>;
};

23
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
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@ -30,12 +30,26 @@ properties:
maximum: 255
description: |
Revision 1 value of SDRAM chip. Obtained from device datasheet.
Property is deprecated, use revision-id instead.
deprecated: true
revision-id2:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Revision 2 value of SDRAM chip. Obtained from device datasheet.
Property is deprecated, use revision-id instead.
deprecated: true
revision-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
minItems: 2
maxItems: 2
items:
minimum: 0
maximum: 255
density:
$ref: /schemas/types.yaml#/definitions/uint32
@ -142,14 +156,12 @@ properties:
patternProperties:
"^lpddr2-timings":
type: object
$ref: jedec,lpddr2-timings.yaml
description: |
The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
speed-bins as is required. Please see Documentation/devicetree/
bindings/memory-controllers/ddr/lpddr2-timings.txt for more information
on "lpddr2-timings".
speed-bins as is required.
required:
- compatible
@ -164,8 +176,7 @@ examples:
compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
revision-id1 = <1>;
revision-id2 = <0>;
revision-id = <1 0>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;

157
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
const: jedec,lpddr3-timings
reg:
maxItems: 1
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
Property is deprecated, use max-freq.
deprecated: true
max-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
min-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Minimum DDR clock frequency for the speed-bin, in Hz.
tCKE:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
tCKESR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in pico seconds.
tFAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Four-bank activate window in pico seconds.
tMRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Mode register set command delay in pico seconds.
tR2R-C2C:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
tRAS:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row active time in pico seconds.
tRC:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
ACTIVATE-to-ACTIVATE command period in pico seconds.
tRCD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RAS-to-CAS delay in pico seconds.
tRFC:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Refresh Cycle time in pico seconds.
tRPab:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (all banks) in pico seconds.
tRPpb:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (single banks) in pico seconds.
tRRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Active bank A to active bank B in pico seconds.
tRTP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal READ to PRECHARGE command delay in pico seconds.
tW2W-C2C:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
tWR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
WRITE recovery time in pico seconds.
tWTR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal WRITE-to-READ command delay in pico seconds.
tXP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Exit power-down to next valid command delay in pico seconds.
tXSR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
SELF REFRESH exit to next valid command delay in pico seconds.
required:
- compatible
- min-freq
- max-freq
additionalProperties: false
examples:
- |
lpddr3 {
timings {
compatible = "jedec,lpddr3-timings";
max-freq = <800000000>;
min-freq = <100000000>;
tCKE = <3750>;
tCKESR = <3750>;
tFAW = <25000>;
tMRD = <7000>;
tR2R-C2C = <0>;
tRAS = <23000>;
tRC = <33750>;
tRCD = <10000>;
tRFC = <65000>;
tRPab = <12000>;
tRPpb = <12000>;
tRRD = <6000>;
tRTP = <3750>;
tW2W-C2C = <0>;
tWR = <7500>;
tWTR = <3750>;
tXP = <3750>;
tXSR = <70000>;
};
};

263
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml Normal file
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@ -0,0 +1,263 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
items:
- enum:
- samsung,K3QF2F20DB
- const: jedec,lpddr3
'#address-cells':
const: 1
deprecated: true
density:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Density in megabits of SDRAM chip.
enum:
- 4096
- 8192
- 16384
- 32768
io-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
IO bus width in bits of SDRAM chip.
enum:
- 32
- 16
manufacturer-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Manufacturer ID value read from Mode Register 5. The property is
deprecated, manufacturer should be derived from the compatible.
deprecated: true
revision-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
items:
maximum: 255
description: |
Revision value of SDRAM chip read from Mode Registers 6 and 7.
'#size-cells':
const: 0
deprecated: true
tCKE-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
of clock cycles.
tCKESR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in terms of number of clock cycles.
tDQSCK-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
DQS output data access time from CK_t/CK_c in terms of number of clock
cycles.
tFAW-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
Four-bank activate window in terms of number of clock cycles.
tMRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Mode register set command delay in terms of number of clock cycles.
tR2R-C2C-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Additional READ-to-READ delay in chip-to-chip cases in terms of number
of clock cycles.
tRAS-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
Row active time in terms of number of clock cycles.
tRC-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
tRCD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
RAS-to-CAS delay in terms of number of clock cycles.
tRFC-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Refresh Cycle time in terms of number of clock cycles.
tRL-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
READ data latency in terms of number of clock cycles.
tRPab-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Row precharge time (all banks) in terms of number of clock cycles.
tRPpb-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Row precharge time (single banks) in terms of number of clock cycles.
tRRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Active bank A to active bank B in terms of number of clock cycles.
tRTP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Internal READ to PRECHARGE command delay in terms of number of clock
cycles.
tW2W-C2C-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
of clock cycles.
tWL-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
WRITE data latency in terms of number of clock cycles.
tWR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
WRITE recovery time in terms of number of clock cycles.
tWTR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Internal WRITE-to-READ command delay in terms of number of clock cycles.
tXP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Exit power-down to next valid command delay in terms of number of clock
cycles.
tXSR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 1023
description: |
SELF REFRESH exit to next valid command delay in terms of number of clock
cycles.
patternProperties:
"^timings((-[0-9])+|(@[0-9a-f]+))?$":
$ref: jedec,lpddr3-timings.yaml
description: |
The lpddr3 node may have one or more child nodes with timings.
Each timing node provides AC timing parameters of the device for a given
speed-bin. The user may provide the timings for as many speed-bins as is
required.
required:
- compatible
- density
- io-width
additionalProperties: false
examples:
- |
lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
tCKE-min-tck = <2>;
tCKESR-min-tck = <2>;
tDQSCK-min-tck = <5>;
tFAW-min-tck = <5>;
tMRD-min-tck = <5>;
tR2R-C2C-min-tck = <0>;
tRAS-min-tck = <5>;
tRC-min-tck = <6>;
tRCD-min-tck = <3>;
tRFC-min-tck = <17>;
tRL-min-tck = <14>;
tRPab-min-tck = <2>;
tRPpb-min-tck = <2>;
tRRD-min-tck = <2>;
tRTP-min-tck = <2>;
tW2W-C2C-min-tck = <0>;
tWL-min-tck = <8>;
tWR-min-tck = <7>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tXSR-min-tck = <12>;
timings {
compatible = "jedec,lpddr3-timings";
max-freq = <800000000>;
min-freq = <100000000>;
tCKE = <3750>;
tCKESR = <3750>;
tFAW = <25000>;
tMRD = <7000>;
tR2R-C2C = <0>;
tRAS = <23000>;
tRC = <33750>;
tRCD = <10000>;
tRFC = <65000>;
tRPab = <12000>;
tRPpb = <12000>;
tRRD = <6000>;
tRTP = <3750>;
tW2W-C2C = <0>;
tWR = <7500>;
tWTR = <3750>;
tXP = <3750>;
tXSR = <70000>;
};
};

52
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt
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@ -1,52 +0,0 @@
* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
Required properties:
- compatible : Should be "jedec,lpddr2-timings"
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
Optional properties:
The following properties represent AC timing parameters from the memory
data-sheet of the device for a given speed-bin. All these properties are
of type <u32> and the default unit is ps (pico seconds). Parameters with
a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
- tRCD
- tWR
- tRAS-min
- tRRD
- tWTR
- tXP
- tRTP
- tDQSCK-max
- tFAW
- tZQCS
- tZQinit
- tRPab
- tZQCL
- tCKESR
- tRAS-max-ns
- tDQSCK-max-derated
Example:
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};

58
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
Просмотреть файл

@ -1,58 +0,0 @@
* AC timing parameters of LPDDR3 memories for a given speed-bin.
The structures are based on LPDDR2 and extended where needed.
Required properties:
- compatible : Should be "jedec,lpddr3-timings"
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
Optional properties:
The following properties represent AC timing parameters from the memory
data-sheet of the device for a given speed-bin. All these properties are
of type <u32> and the default unit is ps (pico seconds).
- tRFC
- tRRD
- tRPab
- tRPpb
- tRCD
- tRC
- tRAS
- tWTR
- tWR
- tRTP
- tW2W-C2C
- tR2R-C2C
- tFAW
- tXSR
- tXP
- tCKE
- tCKESR
- tMRD
Example:
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
compatible = "jedec,lpddr3-timings";
reg = <800000000>; /* workaround: it shows max-freq */
min-freq = <100000000>;
tRFC = <65000>;
tRRD = <6000>;
tRPab = <12000>;
tRPpb = <12000>;
tRCD = <10000>;
tRC = <33750>;
tRAS = <23000>;
tWTR = <3750>;
tWR = <7500>;
tRTP = <3750>;
tW2W-C2C = <0>;
tR2R-C2C = <0>;
tFAW = <25000>;
tXSR = <70000>;
tXP = <3750>;
tCKE = <3750>;
tCKESR = <3750>;
tMRD = <7000>;
};

107
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
Просмотреть файл

@ -1,107 +0,0 @@
* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
Required properties:
- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
Example "<vendor>,<type>" values:
"samsung,K3QF2F20DB"
- density : <u32> representing density in Mb (Mega bits)
- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
- #address-cells: Must be set to 1
- #size-cells: Must be set to 0
Optional properties:
- manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
- revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
The following optional properties represent the minimum value of some AC
timing parameters of the DDR device in terms of number of clock cycles.
These values shall be obtained from the device data-sheet.
- tRFC-min-tck
- tRRD-min-tck
- tRPab-min-tck
- tRPpb-min-tck
- tRCD-min-tck
- tRC-min-tck
- tRAS-min-tck
- tWTR-min-tck
- tWR-min-tck
- tRTP-min-tck
- tW2W-C2C-min-tck
- tR2R-C2C-min-tck
- tWL-min-tck
- tDQSCK-min-tck
- tRL-min-tck
- tFAW-min-tck
- tXSR-min-tck
- tXP-min-tck
- tCKE-min-tck
- tCKESR-min-tck
- tMRD-min-tck
Child nodes:
- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
"lpddr3-timings" provides AC timing parameters of the device for
a given speed-bin. Please see
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
for more information on "lpddr3-timings"
Example:
samsung_K3QF2F20DB: lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
manufacturer-id = <1>;
revision-id = <123 234>;
#address-cells = <1>;
#size-cells = <0>;
tRFC-min-tck = <17>;
tRRD-min-tck = <2>;
tRPab-min-tck = <2>;
tRPpb-min-tck = <2>;
tRCD-min-tck = <3>;
tRC-min-tck = <6>;
tRAS-min-tck = <5>;
tWTR-min-tck = <2>;
tWR-min-tck = <7>;
tRTP-min-tck = <2>;
tW2W-C2C-min-tck = <0>;
tR2R-C2C-min-tck = <0>;
tWL-min-tck = <8>;
tDQSCK-min-tck = <5>;
tRL-min-tck = <14>;
tFAW-min-tck = <5>;
tXSR-min-tck = <12>;
tXP-min-tck = <2>;
tCKE-min-tck = <2>;
tCKESR-min-tck = <2>;
tMRD-min-tck = <5>;
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
compatible = "jedec,lpddr3-timings";
/* workaround: 'reg' shows max-freq */
reg = <800000000>;
min-freq = <100000000>;
tRFC = <65000>;
tRRD = <6000>;
tRPab = <12000>;
tRPpb = <12000>;
tRCD = <10000>;
tRC = <33750>;
tRAS = <23000>;
tWTR = <3750>;
tWR = <7500>;
tRTP = <3750>;
tW2W-C2C = <0>;
tR2R-C2C = <0>;
tFAW = <25000>;
tXSR = <70000>;
tXP = <3750>;
tCKE = <3750>;
tCKESR = <3750>;
tMRD = <7000>;
};
}

113
Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml Normal file
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@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FSL/NXP Integrated Flash Controller
maintainers:
- Li Yang <leoyang.li@nxp.com>
description: |
NXP's integrated flash controller (IFC) is an advanced version of the
enhanced local bus controller which includes similar programming and signal
interfaces with an extended feature set. The IFC provides access to multiple
external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
SRAM and other memories where address and data are shared on a bus.
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
const: fsl,ifc
"#address-cells":
enum: [2, 3]
description: |
Should be either two or three. The first cell is the chipselect
number, and the remaining cells are the offset into the chipselect.
"#size-cells":
enum: [1, 2]
description: |
Either one or two, depending on how large each chipselect can be.
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
description: |
IFC may have one or two interrupts. If two interrupt specifiers are
present, the first is the "common" interrupt (CM_EVTER_STAT), and the
second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
little-endian:
type: boolean
description: |
If this property is absent, the big-endian mode will be in use as default
for registers.
ranges:
description: |
Each range corresponds to a single chipselect, and covers the entire
access window as configured.
patternProperties:
"^.*@[a-f0-9]+(,[a-f0-9]+)+$":
type: object
description: |
Child device nodes describe the devices connected to IFC such as NOR (e.g.
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
like FPGAs, CPLDs, etc.
required:
- compatible
- reg
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@ffe1e000 {
compatible = "fsl,ifc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
little-endian;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
<0x1 0x0 0x0 0xffa00000 0x00010000>,
<0x3 0x0 0x0 0xffb00000 0x00020000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 32MB for user data */
reg = <0x0 0x02000000>;
label = "NOR Data";
};
};
};
};

82
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
Просмотреть файл

@ -1,82 +0,0 @@
Integrated Flash Controller
Properties:
- name : Should be ifc
- compatible : should contain "fsl,ifc". The version of the integrated
flash controller can be found in the IFC_REV register at
offset zero.
- #address-cells : Should be either two or three. The first cell is the
chipselect number, and the remaining cells are the
offset into the chipselect.
- #size-cells : Either one or two, depending on how large each chipselect
can be.
- reg : Offset and length of the register set for the device
- interrupts: IFC may have one or two interrupts. If two interrupt
specifiers are present, the first is the "common"
interrupt (CM_EVTER_STAT), and the second is the NAND
interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
- little-endian : If this property is absent, the big-endian mode will
be in use as default for registers.
- ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
Child device nodes describe the devices connected to IFC such as NOR (e.g.
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
like FPGAs, CPLDs, etc.
Example:
ifc@ffe1e000 {
compatible = "fsl,ifc", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
little-endian;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
0x1 0x0 0x0 0xffa00000 0x00010000
0x3 0x0 0x0 0xffb00000 0x00020000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 32MB for user data */
reg = <0x0 0x02000000>;
label = "NOR Data";
};
};
flash@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
};
cpld@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1010rdb-cpld";
reg = <0x3 0x0 0x000001f>;
};
};

3
Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
Просмотреть файл

@ -51,8 +51,7 @@ properties:
$ref: '/schemas/types.yaml#/definitions/phandle'
description: |
phandle of the connected DRAM memory device. For more information please
refer to documentation file:
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
refer to jedec,lpddr3.yaml.
operating-points-v2: true

2
drivers/memory/brcmstb_dpfe.c
Просмотреть файл

@ -424,7 +424,7 @@ static void __finalize_command(struct brcmstb_dpfe_priv *priv)
/*
* It depends on the API version which MBOX register we have to write to
* to signal we are done.
* signal we are done.
*/
release_mbox = (priv->dpfe_api->version < 2)
? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;

9
drivers/memory/fsl_ifc.c
Просмотреть файл

@ -88,6 +88,7 @@ static int fsl_ifc_ctrl_remove(struct platform_device *dev)
{
struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
of_platform_depopulate(&dev->dev);
free_irq(ctrl->nand_irq, ctrl);
free_irq(ctrl->irq, ctrl);
@ -285,8 +286,16 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
}
}
/* legacy dts may still use "simple-bus" compatible */
ret = of_platform_populate(dev->dev.of_node, NULL, NULL,
&dev->dev);
if (ret)
goto err_free_nandirq;
return 0;
err_free_nandirq:
free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
err_free_irq:
free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
err_unmap_nandirq:

3
drivers/memory/mtk-smi.c
Просмотреть файл

@ -94,8 +94,6 @@ enum mtk_smi_type {
MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */
};
#define MTK_SMI_CLK_NR_MAX 4
/* larbs: Require apb/smi clocks while gals is optional. */
static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
#define MTK_SMI_LARB_REQ_CLK_NR 2
@ -106,6 +104,7 @@ static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
* sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
*/
static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
#define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks)
#define MTK_SMI_COM_REQ_CLK_NR 2
#define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX
#define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3

25
drivers/memory/of_memory.c
Просмотреть файл

@ -212,8 +212,10 @@ static int of_lpddr3_do_get_timings(struct device_node *np,
{
int ret;
/* The 'reg' param required since DT has changed, used as 'max-freq' */
ret = of_property_read_u32(np, "reg", &tim->max_freq);
ret = of_property_read_u32(np, "max-freq", &tim->max_freq);
if (ret)
/* Deprecated way of passing max-freq as 'reg' */
ret = of_property_read_u32(np, "reg", &tim->max_freq);
ret |= of_property_read_u32(np, "min-freq", &tim->min_freq);
ret |= of_property_read_u32(np, "tRFC", &tim->tRFC);
ret |= of_property_read_u32(np, "tRRD", &tim->tRRD);
@ -316,14 +318,21 @@ const struct lpddr2_info
struct property *prop;
const char *cp;
int err;
u32 revision_id[2];
err = of_property_read_u32(np, "revision-id1", &info.revision_id1);
if (err)
info.revision_id1 = -ENOENT;
err = of_property_read_u32_array(np, "revision-id", revision_id, 2);
if (!err) {
info.revision_id1 = revision_id[0];
info.revision_id2 = revision_id[1];
} else {
err = of_property_read_u32(np, "revision-id1", &info.revision_id1);
if (err)
info.revision_id1 = -ENOENT;
err = of_property_read_u32(np, "revision-id2", &info.revision_id2);
if (err)
info.revision_id2 = -ENOENT;
err = of_property_read_u32(np, "revision-id2", &info.revision_id2);
if (err)
info.revision_id2 = -ENOENT;
}
err = of_property_read_u32(np, "io-width", &info.io_width);
if (err)