powerpc/85xx: Add phy nodes in SGMII mode for MPC8536/44/72DS & P2020DS
In SGMII riser card different PHY chip are used with different external IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we should add another group of PHY nodes for SGMII mode. For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3. For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1. For P2020DS IRQ5 is used for PHY1~PHY2. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Коммит
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@ -203,6 +203,14 @@
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reg = <1>;
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device_type = "ethernet-phy";
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};
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sgmii_phy0: sgmii-phy@0 {
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interrupts = <6 1 0 0>;
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reg = <0x1d>;
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};
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sgmii_phy1: sgmii-phy@1 {
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interrupts = <6 1 0 0>;
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reg = <0x1c>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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@ -51,6 +51,15 @@
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device_type = "ethernet-phy";
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};
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sgmii_phy0: sgmii-phy@0 {
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interrupts = <6 1 0 0>;
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reg = <0x1c>;
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};
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sgmii_phy1: sgmii-phy@1 {
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interrupts = <6 1 0 0>;
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reg = <0x1d>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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@ -169,6 +169,23 @@
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reg = <0x3>;
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};
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sgmii_phy0: sgmii-phy@0 {
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interrupts = <6 1 0 0>;
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reg = <0x1c>;
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};
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sgmii_phy1: sgmii-phy@1 {
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interrupts = <6 1 0 0>;
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reg = <0x1d>;
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};
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sgmii_phy2: sgmii-phy@2 {
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interrupts = <7 1 0 0>;
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reg = <0x1e>;
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};
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sgmii_phy3: sgmii-phy@3 {
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interrupts = <7 1 0 0>;
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reg = <0x1f>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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@ -150,6 +150,16 @@
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interrupts = <3 1 0 0>;
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reg = <0x2>;
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};
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sgmii_phy1: sgmii-phy@1 {
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interrupts = <5 1 0 0>;
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reg = <0x1c>;
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};
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sgmii_phy2: sgmii-phy@2 {
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interrupts = <5 1 0 0>;
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reg = <0x1d>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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