bus: arm-ccn: Fix XP watchpoint settings bitmask
The code setting XP watchpoint comparator and mask registers should, in order to be fully compliant with specification, zero one or more most significant bits of each field. In both L cases it means zeroing bit 63. The bitmask doing this was wrong, though, zeroing bit 60 instead. Fortunately, due to a lucky coincidence, this turned out to be fairly innocent with the existing hardware. Fixed now. Cc: stable@vger.kernel.org # 3.17+ Signed-off-by: Pawel Moll <pawel.moll@arm.com>
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Родитель
b7c1beb278
Коммит
b928466b21
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@ -1003,7 +1003,7 @@ static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
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/* Comparison values */
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/* Comparison values */
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writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
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writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
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writel((cmp_l >> 32) & 0xefffffff,
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writel((cmp_l >> 32) & 0x7fffffff,
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source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
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source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
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writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
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writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
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writel((cmp_h >> 32) & 0x0fffffff,
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writel((cmp_h >> 32) & 0x0fffffff,
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@ -1011,7 +1011,7 @@ static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
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/* Mask */
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/* Mask */
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writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
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writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
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writel((mask_l >> 32) & 0xefffffff,
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writel((mask_l >> 32) & 0x7fffffff,
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source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
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source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
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writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
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writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
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writel((mask_h >> 32) & 0x0fffffff,
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writel((mask_h >> 32) & 0x0fffffff,
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