drm/meson: Add registers for G12A SoC
This patch adds the new VPU registers added since the Amlogic GXM SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-3-narmstrong@baylibre.com
This commit is contained in:
Neil Armstrong
Родитель
61af6e22ec
Коммит
b93a66faee
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@ -216,6 +216,29 @@
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#define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b
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#define VIU_OSD2_TEST_RDDATA 0x1a4c
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#define VIU_OSD2_PROT_CTRL 0x1a4e
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#define VIU_OSD2_MALI_UNPACK_CTRL 0x1abd
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#define VIU_OSD2_DIMM_CTRL 0x1acf
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#define VIU_OSD3_CTRL_STAT 0x3d80
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#define VIU_OSD3_CTRL_STAT2 0x3d81
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#define VIU_OSD3_COLOR_ADDR 0x3d82
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#define VIU_OSD3_COLOR 0x3d83
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#define VIU_OSD3_TCOLOR_AG0 0x3d84
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#define VIU_OSD3_TCOLOR_AG1 0x3d85
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#define VIU_OSD3_TCOLOR_AG2 0x3d86
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#define VIU_OSD3_TCOLOR_AG3 0x3d87
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#define VIU_OSD3_BLK0_CFG_W0 0x3d88
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#define VIU_OSD3_BLK0_CFG_W1 0x3d8c
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#define VIU_OSD3_BLK0_CFG_W2 0x3d90
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#define VIU_OSD3_BLK0_CFG_W3 0x3d94
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#define VIU_OSD3_BLK0_CFG_W4 0x3d98
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#define VIU_OSD3_BLK1_CFG_W4 0x3d99
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#define VIU_OSD3_BLK2_CFG_W4 0x3d9a
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#define VIU_OSD3_FIFO_CTRL_STAT 0x3d9c
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#define VIU_OSD3_TEST_RDDATA 0x3d9d
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#define VIU_OSD3_PROT_CTRL 0x3d9e
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#define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f
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#define VIU_OSD3_DIMM_CTRL 0x3da0
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#define VD1_IF0_GEN_REG 0x1a50
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#define VD1_IF0_CANVAS0 0x1a51
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@ -287,6 +310,27 @@
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#define VIU_OSD1_MATRIX_COEF31_32 0x1a9e
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#define VIU_OSD1_MATRIX_COEF40_41 0x1a9f
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#define VD1_IF0_GEN_REG3 0x1aa7
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#define VIU_OSD_BLENDO_H_START_END 0x1aa9
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#define VIU_OSD_BLENDO_V_START_END 0x1aaa
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#define VIU_OSD_BLEND_GEN_CTRL0 0x1aab
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#define VIU_OSD_BLEND_GEN_CTRL1 0x1aac
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#define VIU_OSD_BLEND_DUMMY_DATA 0x1aad
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#define VIU_OSD_BLEND_CURRENT_XY 0x1aae
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#define VIU_OSD2_MATRIX_CTRL 0x1ab0
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#define VIU_OSD2_MATRIX_COEF00_01 0x1ab1
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#define VIU_OSD2_MATRIX_COEF02_10 0x1ab2
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#define VIU_OSD2_MATRIX_COEF11_12 0x1ab3
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#define VIU_OSD2_MATRIX_COEF20_21 0x1ab4
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#define VIU_OSD2_MATRIX_COEF22 0x1ab5
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#define VIU_OSD2_MATRIX_OFFSET0_1 0x1ab6
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#define VIU_OSD2_MATRIX_OFFSET2 0x1ab7
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#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 0x1ab8
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#define VIU_OSD2_MATRIX_PRE_OFFSET2 0x1ab9
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#define VIU_OSD2_MATRIX_PROBE_COLOR 0x1aba
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#define VIU_OSD2_MATRIX_HL_COLOR 0x1abb
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#define VIU_OSD2_MATRIX_PROBE_POS 0x1abc
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#define VIU_OSD1_EOTF_CTL 0x1ad4
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#define VIU_OSD1_EOTF_COEF00_01 0x1ad5
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#define VIU_OSD1_EOTF_COEF02_10 0x1ad6
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@ -481,6 +525,82 @@
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#define VPP_OSD_SCALE_COEF 0x1dcd
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#define VPP_INT_LINE_NUM 0x1dce
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#define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60
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#define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61
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#define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62
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#define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63
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#define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64
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#define VPP_WRAP_OSD1_MATRIX_COEF13_14 0x3d65
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#define VPP_WRAP_OSD1_MATRIX_COEF23_24 0x3d66
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#define VPP_WRAP_OSD1_MATRIX_COEF15_25 0x3d67
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#define VPP_WRAP_OSD1_MATRIX_CLIP 0x3d68
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#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69
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#define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a
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#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b
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#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c
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#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d
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#define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70
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#define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71
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#define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72
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#define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73
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#define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74
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#define VPP_WRAP_OSD2_MATRIX_COEF13_14 0x3d75
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#define VPP_WRAP_OSD2_MATRIX_COEF23_24 0x3d76
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#define VPP_WRAP_OSD2_MATRIX_COEF15_25 0x3d77
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#define VPP_WRAP_OSD2_MATRIX_CLIP 0x3d78
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#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79
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#define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a
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#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b
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#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c
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#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d
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#define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0
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#define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1
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#define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2
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#define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3
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#define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4
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#define VPP_WRAP_OSD3_MATRIX_COEF13_14 0x3db5
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#define VPP_WRAP_OSD3_MATRIX_COEF23_24 0x3db6
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#define VPP_WRAP_OSD3_MATRIX_COEF15_25 0x3db7
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#define VPP_WRAP_OSD3_MATRIX_CLIP 0x3db8
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#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9
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#define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba
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#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb
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#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc
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#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
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/* osd2 scaler */
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#define OSD2_VSC_PHASE_STEP 0x3d00
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#define OSD2_VSC_INI_PHASE 0x3d01
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#define OSD2_VSC_CTRL0 0x3d02
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#define OSD2_HSC_PHASE_STEP 0x3d03
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#define OSD2_HSC_INI_PHASE 0x3d04
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#define OSD2_HSC_CTRL0 0x3d05
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#define OSD2_HSC_INI_PAT_CTRL 0x3d06
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#define OSD2_SC_DUMMY_DATA 0x3d07
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#define OSD2_SC_CTRL0 0x3d08
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#define OSD2_SCI_WH_M1 0x3d09
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#define OSD2_SCO_H_START_END 0x3d0a
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#define OSD2_SCO_V_START_END 0x3d0b
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#define OSD2_SCALE_COEF_IDX 0x3d18
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#define OSD2_SCALE_COEF 0x3d19
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/* osd34 scaler */
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#define OSD34_SCALE_COEF_IDX 0x3d1e
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#define OSD34_SCALE_COEF 0x3d1f
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#define OSD34_VSC_PHASE_STEP 0x3d20
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#define OSD34_VSC_INI_PHASE 0x3d21
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#define OSD34_VSC_CTRL0 0x3d22
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#define OSD34_HSC_PHASE_STEP 0x3d23
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#define OSD34_HSC_INI_PHASE 0x3d24
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#define OSD34_HSC_CTRL0 0x3d25
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#define OSD34_HSC_INI_PAT_CTRL 0x3d26
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#define OSD34_SC_DUMMY_DATA 0x3d27
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#define OSD34_SC_CTRL0 0x3d28
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#define OSD34_SCI_WH_M1 0x3d29
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#define OSD34_SCO_H_START_END 0x3d2a
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#define OSD34_SCO_V_START_END 0x3d2b
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/* viu2 */
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#define VIU2_ADDR_START 0x1e00
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#define VIU2_ADDR_END 0x1eff
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@ -1400,4 +1520,131 @@
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#define OSDSR_YBIC_VCOEF0 0x3149
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#define OSDSR_CBIC_VCOEF0 0x314a
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/* osd afbcd on gxtvbb */
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#define OSD1_AFBCD_ENABLE 0x31a0
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#define OSD1_AFBCD_MODE 0x31a1
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#define OSD1_AFBCD_SIZE_IN 0x31a2
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#define OSD1_AFBCD_HDR_PTR 0x31a3
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#define OSD1_AFBCD_FRAME_PTR 0x31a4
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#define OSD1_AFBCD_CHROMA_PTR 0x31a5
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#define OSD1_AFBCD_CONV_CTRL 0x31a6
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#define OSD1_AFBCD_STATUS 0x31a8
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#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9
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#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa
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#define VIU_MISC_CTRL1 0x1a07
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/* add for gxm and 962e dv core2 */
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#define DOLBY_CORE2A_SWAP_CTRL1 0x3434
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#define DOLBY_CORE2A_SWAP_CTRL2 0x3435
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/* osd afbc on g12a */
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#define VPU_MAFBC_BLOCK_ID 0x3a00
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#define VPU_MAFBC_IRQ_RAW_STATUS 0x3a01
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#define VPU_MAFBC_IRQ_CLEAR 0x3a02
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#define VPU_MAFBC_IRQ_MASK 0x3a03
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#define VPU_MAFBC_IRQ_STATUS 0x3a04
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#define VPU_MAFBC_COMMAND 0x3a05
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#define VPU_MAFBC_STATUS 0x3a06
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#define VPU_MAFBC_SURFACE_CFG 0x3a07
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/* osd afbc on g12a */
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#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10
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#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11
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#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12
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#define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a13
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#define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a14
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#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a15
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#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 0x3a16
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#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 0x3a17
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#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 0x3a18
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#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 0x3a19
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#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a
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#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b
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#define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c
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#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a30
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#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a31
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#define VPU_MAFBC_FORMAT_SPECIFIER_S1 0x3a32
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#define VPU_MAFBC_BUFFER_WIDTH_S1 0x3a33
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#define VPU_MAFBC_BUFFER_HEIGHT_S1 0x3a34
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#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 0x3a35
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#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 0x3a36
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#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 0x3a37
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#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 0x3a38
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#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 0x3a39
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#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 0x3a3a
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#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 0x3a3b
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#define VPU_MAFBC_PREFETCH_CFG_S1 0x3a3c
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#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 0x3a50
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#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 0x3a51
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#define VPU_MAFBC_FORMAT_SPECIFIER_S2 0x3a52
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#define VPU_MAFBC_BUFFER_WIDTH_S2 0x3a53
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#define VPU_MAFBC_BUFFER_HEIGHT_S2 0x3a54
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#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 0x3a55
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#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 0x3a56
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#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 0x3a57
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#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 0x3a58
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#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 0x3a59
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#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 0x3a5a
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#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 0x3a5b
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#define VPU_MAFBC_PREFETCH_CFG_S2 0x3a5c
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#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 0x3a70
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#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 0x3a71
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#define VPU_MAFBC_FORMAT_SPECIFIER_S3 0x3a72
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#define VPU_MAFBC_BUFFER_WIDTH_S3 0x3a73
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#define VPU_MAFBC_BUFFER_HEIGHT_S3 0x3a74
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#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 0x3a75
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#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 0x3a76
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#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 0x3a77
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#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 0x3a78
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#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 0x3a79
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#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 0x3a7a
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#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b
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#define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c
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#define DOLBY_PATH_CTRL 0x1a0c
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#define OSD_PATH_MISC_CTRL 0x1a0e
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#define MALI_AFBCD_TOP_CTRL 0x1a0f
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#define VIU_OSD_BLEND_CTRL 0x39b0
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#define VIU_OSD_BLEND_CTRL1 0x39c0
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#define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1
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#define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2
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#define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3
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#define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4
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#define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5
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#define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6
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#define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7
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#define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8
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#define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9
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#define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba
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#define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb
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#define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc
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#define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf
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#define VPP_OUT_H_V_SIZE 0x1da5
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#define VPP_VD2_HDR_IN_SIZE 0x1df0
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#define VPP_OSD1_IN_SIZE 0x1df1
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#define VPP_GCLK_CTRL2 0x1df2
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#define VD2_PPS_DUMMY_DATA 0x1df4
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#define VPP_OSD1_BLD_H_SCOPE 0x1df5
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#define VPP_OSD1_BLD_V_SCOPE 0x1df6
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#define VPP_OSD2_BLD_H_SCOPE 0x1df7
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#define VPP_OSD2_BLD_V_SCOPE 0x1df8
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#define VPP_WRBAK_CTRL 0x1df9
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#define VPP_SLEEP_CTRL 0x1dfa
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#define VD1_BLEND_SRC_CTRL 0x1dfb
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#define VD2_BLEND_SRC_CTRL 0x1dfc
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#define OSD1_BLEND_SRC_CTRL 0x1dfd
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#define OSD2_BLEND_SRC_CTRL 0x1dfe
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#define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968
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#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969
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#define VPP_RDARB_MODE 0x3978
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#define VPP_RDARB_REQEN_SLV 0x3979
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#define VPU_RDARB_MODE_L2C1 0x279d
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#endif /* __MESON_REGISTERS_H */
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