rtw89: pci: add pci attributes to configure operating mode
Refine operating mode function to support variant chips. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220325060055.58482-3-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
Родитель
740c431c22
Коммит
b9467e94b1
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@ -1917,6 +1917,33 @@ static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev)
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B_AX_SIC_EN_FORCE_CLKREQ);
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}
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static void rtw89_pci_set_io_rcy(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_pci_info *info = rtwdev->pci_info;
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u32 val32;
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if (rtwdev->chip->chip_id != RTL8852C)
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return;
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if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) {
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val32 = FIELD_PREP(B_AX_PCIE_WDT_TIMER_M1_MASK,
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info->io_rcy_tmr);
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rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_M1, val32);
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rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_M2, val32);
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rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_E0, val32);
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rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1);
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rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2);
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rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0);
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} else {
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rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1);
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rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2);
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rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0);
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}
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rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_S1, B_AX_PCIE_IO_RCY_WDT_MODE_S1);
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}
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static void rtw89_pci_set_dbg(struct rtw89_dev *rtwdev)
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{
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if (rtwdev->chip->chip_id == RTL8852C)
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@ -1952,6 +1979,95 @@ static void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev)
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B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX);
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}
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static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_pci_info *info = rtwdev->pci_info;
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enum mac_ax_bd_trunc_mode txbd_trunc_mode = info->txbd_trunc_mode;
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enum mac_ax_bd_trunc_mode rxbd_trunc_mode = info->rxbd_trunc_mode;
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enum mac_ax_rxbd_mode rxbd_mode = info->rxbd_mode;
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enum mac_ax_tag_mode tag_mode = info->tag_mode;
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enum mac_ax_wd_dma_intvl wd_dma_idle_intvl = info->wd_dma_idle_intvl;
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enum mac_ax_wd_dma_intvl wd_dma_act_intvl = info->wd_dma_act_intvl;
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enum mac_ax_tx_burst tx_burst = info->tx_burst;
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enum mac_ax_rx_burst rx_burst = info->rx_burst;
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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u8 cv = rtwdev->hal.cv;
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u32 val32;
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if (txbd_trunc_mode == MAC_AX_BD_TRUNC) {
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if (chip_id == RTL8852A && cv == CHIP_CBV)
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rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE);
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} else if (txbd_trunc_mode == MAC_AX_BD_NORM) {
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if (chip_id == RTL8852A || chip_id == RTL8852B)
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rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE);
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}
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if (rxbd_trunc_mode == MAC_AX_BD_TRUNC) {
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if (chip_id == RTL8852A && cv == CHIP_CBV)
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rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE);
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} else if (rxbd_trunc_mode == MAC_AX_BD_NORM) {
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if (chip_id == RTL8852A || chip_id == RTL8852B)
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rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE);
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}
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if (rxbd_mode == MAC_AX_RXBD_PKT) {
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rtw89_write32_clr(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit);
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} else if (rxbd_mode == MAC_AX_RXBD_SEP) {
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rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit);
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if (chip_id == RTL8852A || chip_id == RTL8852B)
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2,
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B_AX_PCIE_RX_APPLEN_MASK, 0);
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}
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if (chip_id == RTL8852A || chip_id == RTL8852B) {
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, tx_burst);
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, rx_burst);
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} else if (chip_id == RTL8852C) {
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rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_TXDMA_MASK, tx_burst);
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rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_RXDMA_MASK, rx_burst);
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}
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if (chip_id == RTL8852A || chip_id == RTL8852B) {
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if (tag_mode == MAC_AX_TAG_SGL) {
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val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) &
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~B_AX_LATENCY_CONTROL;
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rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, val32);
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} else if (tag_mode == MAC_AX_TAG_MULTI) {
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val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) |
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B_AX_LATENCY_CONTROL;
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rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, val32);
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}
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}
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rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask,
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info->multi_tag_num);
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if (chip_id == RTL8852A || chip_id == RTL8852B) {
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE,
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wd_dma_idle_intvl);
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT,
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wd_dma_act_intvl);
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} else if (chip_id == RTL8852C) {
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rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_IDLE_V1_MASK,
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wd_dma_idle_intvl);
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rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_ACT_V1_MASK,
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wd_dma_act_intvl);
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}
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if (txbd_trunc_mode == MAC_AX_BD_TRUNC) {
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rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING,
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B_AX_HOST_ADDR_INFO_8B_SEL);
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rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH);
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} else if (txbd_trunc_mode == MAC_AX_BD_NORM) {
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rtw89_write32_clr(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING,
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B_AX_HOST_ADDR_INFO_8B_SEL);
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rtw89_write32_set(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH);
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}
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return 0;
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}
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static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev)
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{
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if (rtwdev->chip->chip_id == RTL8852A) {
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@ -1995,6 +2111,7 @@ static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)
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rtw89_pci_autoload_hang(rtwdev);
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rtw89_pci_l12_vmain(rtwdev);
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rtw89_pci_set_sic(rtwdev);
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rtw89_pci_set_io_rcy(rtwdev);
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rtw89_pci_set_dbg(rtwdev);
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if (rtwdev->chip->chip_id == RTL8852A) {
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@ -2025,21 +2142,7 @@ static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)
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}
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rtw89_pci_clr_idx_all(rtwdev);
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/* configure TX/RX op modes */
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rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE |
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B_AX_RX_TRUNC_MODE);
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rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RXBD_MODE);
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, 7);
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, 3);
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/* multi-tag mode */
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rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_LATENCY_CONTROL);
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rtw89_write32_mask(rtwdev, R_AX_PCIE_EXP_CTRL, B_AX_MAX_TAG_NUM,
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RTW89_MAC_TAG_NUM_8);
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE,
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RTW89_MAC_WD_DMA_INTVL_256NS);
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rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT,
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RTW89_MAC_WD_DMA_INTVL_256NS);
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rtw89_pci_mode_op(rtwdev);
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/* fill TRX BD indexes */
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rtw89_pci_ops_reset(rtwdev);
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@ -490,6 +490,105 @@ enum rtw89_pcie_clkdly_hw {
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PCIE_CLKDLY_HW_200US = 0x5,
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};
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enum mac_ax_bd_trunc_mode {
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MAC_AX_BD_NORM,
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MAC_AX_BD_TRUNC,
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MAC_AX_BD_DEF = 0xFE
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};
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enum mac_ax_rxbd_mode {
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MAC_AX_RXBD_PKT,
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MAC_AX_RXBD_SEP,
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MAC_AX_RXBD_DEF = 0xFE
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};
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enum mac_ax_tag_mode {
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MAC_AX_TAG_SGL,
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MAC_AX_TAG_MULTI,
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MAC_AX_TAG_DEF = 0xFE
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};
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enum mac_ax_tx_burst {
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MAC_AX_TX_BURST_16B = 0,
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MAC_AX_TX_BURST_32B = 1,
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MAC_AX_TX_BURST_64B = 2,
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MAC_AX_TX_BURST_V1_64B = 0,
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MAC_AX_TX_BURST_128B = 3,
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MAC_AX_TX_BURST_V1_128B = 1,
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MAC_AX_TX_BURST_256B = 4,
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MAC_AX_TX_BURST_V1_256B = 2,
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MAC_AX_TX_BURST_512B = 5,
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MAC_AX_TX_BURST_1024B = 6,
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MAC_AX_TX_BURST_2048B = 7,
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MAC_AX_TX_BURST_DEF = 0xFE
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};
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enum mac_ax_rx_burst {
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MAC_AX_RX_BURST_16B = 0,
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MAC_AX_RX_BURST_32B = 1,
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MAC_AX_RX_BURST_64B = 2,
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MAC_AX_RX_BURST_V1_64B = 0,
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MAC_AX_RX_BURST_128B = 3,
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MAC_AX_RX_BURST_V1_128B = 1,
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MAC_AX_RX_BURST_V1_256B = 0,
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MAC_AX_RX_BURST_DEF = 0xFE
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};
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enum mac_ax_wd_dma_intvl {
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MAC_AX_WD_DMA_INTVL_0S,
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MAC_AX_WD_DMA_INTVL_256NS,
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MAC_AX_WD_DMA_INTVL_512NS,
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MAC_AX_WD_DMA_INTVL_768NS,
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MAC_AX_WD_DMA_INTVL_1US,
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MAC_AX_WD_DMA_INTVL_1_5US,
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MAC_AX_WD_DMA_INTVL_2US,
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MAC_AX_WD_DMA_INTVL_4US,
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MAC_AX_WD_DMA_INTVL_8US,
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MAC_AX_WD_DMA_INTVL_16US,
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MAC_AX_WD_DMA_INTVL_DEF = 0xFE
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};
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enum mac_ax_multi_tag_num {
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MAC_AX_TAG_NUM_1,
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MAC_AX_TAG_NUM_2,
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MAC_AX_TAG_NUM_3,
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MAC_AX_TAG_NUM_4,
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MAC_AX_TAG_NUM_5,
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MAC_AX_TAG_NUM_6,
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MAC_AX_TAG_NUM_7,
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MAC_AX_TAG_NUM_8,
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MAC_AX_TAG_NUM_DEF = 0xFE
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};
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enum mac_ax_lbc_tmr {
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MAC_AX_LBC_TMR_8US = 0,
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MAC_AX_LBC_TMR_16US,
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MAC_AX_LBC_TMR_32US,
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MAC_AX_LBC_TMR_64US,
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MAC_AX_LBC_TMR_128US,
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MAC_AX_LBC_TMR_256US,
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MAC_AX_LBC_TMR_512US,
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MAC_AX_LBC_TMR_1MS,
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MAC_AX_LBC_TMR_2MS,
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MAC_AX_LBC_TMR_4MS,
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MAC_AX_LBC_TMR_8MS,
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MAC_AX_LBC_TMR_DEF = 0xFE
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};
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enum mac_ax_pcie_func_ctrl {
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MAC_AX_PCIE_DISABLE = 0,
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MAC_AX_PCIE_ENABLE = 1,
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MAC_AX_PCIE_DEFAULT = 0xFE,
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MAC_AX_PCIE_IGNORE = 0xFF
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};
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enum mac_ax_io_rcy_tmr {
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MAC_AX_IO_RCY_ANA_TMR_2MS = 24000,
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MAC_AX_IO_RCY_ANA_TMR_4MS = 48000,
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MAC_AX_IO_RCY_ANA_TMR_6MS = 72000,
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MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
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};
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struct rtw89_pci_ch_dma_addr {
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u32 num;
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u32 idx;
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@ -504,6 +603,21 @@ struct rtw89_pci_ch_dma_addr_set {
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};
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struct rtw89_pci_info {
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enum mac_ax_bd_trunc_mode txbd_trunc_mode;
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enum mac_ax_bd_trunc_mode rxbd_trunc_mode;
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enum mac_ax_rxbd_mode rxbd_mode;
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enum mac_ax_tag_mode tag_mode;
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enum mac_ax_tx_burst tx_burst;
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enum mac_ax_rx_burst rx_burst;
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enum mac_ax_wd_dma_intvl wd_dma_idle_intvl;
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enum mac_ax_wd_dma_intvl wd_dma_act_intvl;
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enum mac_ax_multi_tag_num multi_tag_num;
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enum mac_ax_pcie_func_ctrl lbc_en;
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enum mac_ax_lbc_tmr lbc_tmr;
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enum mac_ax_pcie_func_ctrl autok_en;
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enum mac_ax_pcie_func_ctrl io_rcy_en;
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enum mac_ax_io_rcy_tmr io_rcy_tmr;
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u32 init_cfg_reg;
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u32 txhci_en_bit;
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u32 rxhci_en_bit;
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@ -9,6 +9,21 @@
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#include "rtw8852a.h"
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static const struct rtw89_pci_info rtw8852a_pci_info = {
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.txbd_trunc_mode = MAC_AX_BD_TRUNC,
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.rxbd_trunc_mode = MAC_AX_BD_TRUNC,
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.rxbd_mode = MAC_AX_RXBD_PKT,
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.tag_mode = MAC_AX_TAG_MULTI,
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.tx_burst = MAC_AX_TX_BURST_2048B,
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.rx_burst = MAC_AX_RX_BURST_128B,
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.wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS,
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.wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS,
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.multi_tag_num = MAC_AX_TAG_NUM_8,
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.lbc_en = MAC_AX_PCIE_ENABLE,
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.lbc_tmr = MAC_AX_LBC_TMR_2MS,
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.autok_en = MAC_AX_PCIE_DISABLE,
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.io_rcy_en = MAC_AX_PCIE_DISABLE,
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.io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_6MS,
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.init_cfg_reg = R_AX_PCIE_INIT_CFG1,
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.txhci_en_bit = B_AX_TXHCI_EN,
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.rxhci_en_bit = B_AX_RXHCI_EN,
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@ -10,6 +10,21 @@
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#include "rtw8852c.h"
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static const struct rtw89_pci_info rtw8852c_pci_info = {
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.txbd_trunc_mode = MAC_AX_BD_TRUNC,
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.rxbd_trunc_mode = MAC_AX_BD_TRUNC,
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.rxbd_mode = MAC_AX_RXBD_PKT,
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.tag_mode = MAC_AX_TAG_MULTI,
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.tx_burst = MAC_AX_TX_BURST_V1_256B,
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.rx_burst = MAC_AX_RX_BURST_V1_128B,
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.wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS,
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.wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS,
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.multi_tag_num = MAC_AX_TAG_NUM_8,
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.lbc_en = MAC_AX_PCIE_ENABLE,
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.lbc_tmr = MAC_AX_LBC_TMR_2MS,
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.autok_en = MAC_AX_PCIE_DISABLE,
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.io_rcy_en = MAC_AX_PCIE_ENABLE,
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.io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_6MS,
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.init_cfg_reg = R_AX_HAXI_INIT_CFG1,
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.txhci_en_bit = B_AX_TXHCI_EN_V1,
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.rxhci_en_bit = B_AX_RXHCI_EN_V1,
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Ссылка в новой задаче